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Searched refs:BIT2 (Results 1 – 38 of 38) sorted by relevance

/linux-4.1.27/drivers/scsi/
Ddc395x.h73 #define BIT2 0x00000004 macro
80 #define FORMATING_MEDIA BIT2
86 #define ASPI_SUPPORT BIT2
122 #define RESET_DONE BIT2
130 #define OVER_RUN BIT2
140 #define RESET_DEV0 BIT2
175 #define WIDE_NEGO_ENABLE BIT2
631 #define RST_SCSI_BUS BIT2
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
161 #define RCR_AM BIT2
217 #define SCR_TxEncEnable BIT2
240 #define IMR_VIDOK BIT2
247 #define TPPoll_VIQ BIT2
287 #define AcmHw_ViqEn BIT2
295 #define AcmFw_VoqStatus BIT2
348 #define BW_OPMODE_20MHZ BIT2
377 #define RRSR_5_5M BIT2
/linux-4.1.27/drivers/staging/rtl8192u/
Dr8192U_hw.h158 #define RCR_AM BIT2 // Accept multicast packet
185 #define SCR_TxEncEnable BIT2 //Enable Tx Encryption
231 #define AcmHw_ViqEn BIT2
286 #define BW_OPMODE_20MHZ BIT2
309 #define RRSR_5_5M BIT2
Dr8192U.h48 #define BIT2 0x00000004 macro
92 #define COMP_INIT BIT2 /* Driver initialization/halt/reset. */
/linux-4.1.27/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h28 #define BIT2 0x00000004 macro
542 #define CMD_EFUSE_PATCH BIT2
553 #define RRSR_5_5M BIT2
578 #define BW_OPMODE_20MHZ BIT2
612 #define WOW_MAGIC BIT2 /* Magic packet */
640 #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */
703 #define StopBE BIT2
730 #define RCR_AM BIT2 /* Accept multicast packet */
1202 #define SDIO_HIMR_TXERR_MSK BIT2
1228 #define SDIO_HISR_TXERR BIT2
[all …]
Drtw_sreset.h35 #define USB_WRITE_PORT_FAIL BIT2
Dodm_debug.h62 #define ODM_COMP_DYNAMIC_TXPWR BIT2
Dodm.h419 ODM_BB_DYNAMIC_TXPWR = BIT2,
465 ODM_RF_TX_C = BIT2,
503 ODM_SCAN = BIT2,
517 ODM_WM_A = BIT2,
DHal8188EPhyCfg.h90 WIRELESS_MODE_A = BIT2,
Dosdep_service.h90 #define BIT2 0x00000004 macro
Dhal_intf.h30 RTW_SDIO = BIT2,
/linux-4.1.27/drivers/video/fbdev/via/
Ddvi.c349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
Dshare.h30 #define BIT2 0x04 macro
Dhw.c964 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
2073 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); in viafb_set_dpa_gfx()
Dviafbdev.c1131 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2; in viafb_dvp0_proc_show()
1177 reg_val << 2, BIT2); in viafb_dvp0_proc_write()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h48 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
545 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
/linux-4.1.27/drivers/staging/rtl8192e/
Drtl819x_Qos.h24 #define BIT2 0x00000004 macro
240 #define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2)
241 #define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2)
Drtllib.h127 #define RT_RF_OFF_LEVL_PCI_D3 BIT2
/linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h50 #define BIT2 0x00000004 macro
Dhalbtcoutsrc.h98 #define INTF_NOTIFY BIT2
103 #define ALGO_BT_MONITOR BIT2
115 #define WIFI_HS_CONNECTED BIT2
Dhalbtc8821a2ant.h35 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
Dhalbtc8723b2ant.h38 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
Dhalbtc8723b1ant.h35 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
Dhalbtc8192e2ant.h35 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
Dhalbtc8821a1ant.h37 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
Dhalbtc8821a2ant.c3745 if (!(coex_sta->bt_info_ext & BIT2)) { in ex_halbtc8821a2ant_bt_info_notify()
/linux-4.1.27/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h6 #define BIT2 0x00000004 macro
384 #define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2)
385 #define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2)
/linux-4.1.27/drivers/staging/rtl8188eu/core/
Drtw_efuse.c419 if (!(word_en&BIT2)) { in Efuse_WordEnableDataWrite()
427 badworden &= (~BIT2); in Efuse_WordEnableDataWrite()
747 if (((pTargetPkt->word_en & BIT2) == 0) && in wordEnMatched()
748 ((pCurPkt->word_en & BIT2) == 0)) in wordEnMatched()
749 match_word_en &= ~BIT2; /* enable word 2 */ in wordEnMatched()
/linux-4.1.27/drivers/char/pcmcia/
Dsynclink_cs.c301 #define IRQ_DCD BIT2 // carrier detect status change
308 #define CEC BIT2 // command executing
313 #define PVR_RI BIT2
690 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { in wait_command_complete()
1192 if (gis & (BIT3 | BIT2)) in mgslpc_isr()
1239 if (pis & BIT2) in mgslpc_isr()
2960 val |= BIT2; in enable_auxclk()
3032 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); in loopback_enable()
3103 val |= BIT2; in hdlc_mode()
3126 val |= BIT4 | BIT2; in hdlc_mode()
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/linux-4.1.27/drivers/staging/rtl8188eu/hal/
Dodm_RTL8188E.c173 phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); in dm_fast_training_init()
236 dm_fat_tbl->antsel_c[mac_id] = (target_ant&BIT2)>>2; in update_tx_ant_88eu()
Drtl8188e_hal_init.c109 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); in _8051Reset88E()
110 usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2)); in _8051Reset88E()
/linux-4.1.27/include/uapi/linux/
Dsynclink.h20 #define BIT2 0x0004 macro
/linux-4.1.27/drivers/tty/
Dsynclink_gt.c220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
2033 if (status & BIT2) { in cts_change()
2303 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
3936 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3985 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
4010 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
4032 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
4035 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4052 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4081 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
[all …]
Dsynclink.c494 #define TRANSMIT_DATA BIT2
512 #define RXSTATUS_ABORT BIT2
513 #define RXSTATUS_PARITY_ERROR BIT2
551 #define TXSTATUS_ALL_SENT BIT2
571 #define MISCSTATUS_DPLL_NO_SYNC BIT2
597 #define SICR_DPLL_NO_SYNC BIT2
631 #define TXSTATUS_ALL_SENT BIT2
1653 if ( status & BIT2 ) { in mgsl_isr_transmit_dma()
5452 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); in usc_process_rxoverrun_sync()
5541 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); in usc_start_receiver()
[all …]
Dsynclinkmp.c426 #define CDCD BIT2
442 #define CRCE BIT2
2589 if (status & BIT2 << shift) in synclinkmp_interrupt()
2598 if (dmastatus & BIT2 << shift) in synclinkmp_interrupt()
4416 case 7: RegValue |= BIT4 + BIT2; break; in async_mode()
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4553 RegValue |= BIT2 + BIT1; in hdlc_mode()
4757 if ( !(status & BIT2)) in get_signals()
4915 status &= ~BIT2; in rx_get_frame()
4929 if (status & (BIT6+BIT5+BIT3+BIT2)) { in rx_get_frame()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h386 #define RRSR_5_5M BIT2
521 #define WOW_MAGIC BIT2 /* Magic packet */
/linux-4.1.27/drivers/scsi/lpfc/
Dlpfc_hw4.h676 #define LPFC_SLI4_INTR2 BIT2