1/*
2 * skl-tplg-interface.h - Intel DSP FW private data interface
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *	    Nilofer, Samreen <samreen.nilofer@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 */
18
19#ifndef __HDA_TPLG_INTERFACE_H__
20#define __HDA_TPLG_INTERFACE_H__
21
22/*
23 * Default types range from 0~12. type can range from 0 to 0xff
24 * SST types start at higher to avoid any overlapping in future
25 */
26#define SOC_CONTROL_TYPE_HDA_SST_ALGO_PARAMS	0x100
27#define SOC_CONTROL_TYPE_HDA_SST_MUX		0x101
28#define SOC_CONTROL_TYPE_HDA_SST_MIX		0x101
29#define SOC_CONTROL_TYPE_HDA_SST_BYTE		0x103
30
31#define HDA_SST_CFG_MAX	900 /* size of copier cfg*/
32#define MAX_IN_QUEUE 8
33#define MAX_OUT_QUEUE 8
34
35/* Event types goes here */
36/* Reserve event type 0 for no event handlers */
37enum skl_event_types {
38	SKL_EVENT_NONE = 0,
39	SKL_MIXER_EVENT,
40	SKL_MUX_EVENT,
41	SKL_VMIXER_EVENT,
42	SKL_PGA_EVENT
43};
44
45/**
46 * enum skl_ch_cfg - channel configuration
47 *
48 * @SKL_CH_CFG_MONO:	One channel only
49 * @SKL_CH_CFG_STEREO:	L & R
50 * @SKL_CH_CFG_2_1:	L, R & LFE
51 * @SKL_CH_CFG_3_0:	L, C & R
52 * @SKL_CH_CFG_3_1:	L, C, R & LFE
53 * @SKL_CH_CFG_QUATRO:	L, R, Ls & Rs
54 * @SKL_CH_CFG_4_0:	L, C, R & Cs
55 * @SKL_CH_CFG_5_0:	L, C, R, Ls & Rs
56 * @SKL_CH_CFG_5_1:	L, C, R, Ls, Rs & LFE
57 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
58 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
59 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
60 * @SKL_CH_CFG_INVALID:	Invalid
61 */
62enum skl_ch_cfg {
63	SKL_CH_CFG_MONO = 0,
64	SKL_CH_CFG_STEREO = 1,
65	SKL_CH_CFG_2_1 = 2,
66	SKL_CH_CFG_3_0 = 3,
67	SKL_CH_CFG_3_1 = 4,
68	SKL_CH_CFG_QUATRO = 5,
69	SKL_CH_CFG_4_0 = 6,
70	SKL_CH_CFG_5_0 = 7,
71	SKL_CH_CFG_5_1 = 8,
72	SKL_CH_CFG_DUAL_MONO = 9,
73	SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
74	SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
75	SKL_CH_CFG_INVALID
76};
77
78enum skl_module_type {
79	SKL_MODULE_TYPE_MIXER = 0,
80	SKL_MODULE_TYPE_COPIER,
81	SKL_MODULE_TYPE_UPDWMIX,
82	SKL_MODULE_TYPE_SRCINT
83};
84
85enum skl_core_affinity {
86	SKL_AFFINITY_CORE_0 = 0,
87	SKL_AFFINITY_CORE_1,
88	SKL_AFFINITY_CORE_MAX
89};
90
91enum skl_pipe_conn_type {
92	SKL_PIPE_CONN_TYPE_NONE = 0,
93	SKL_PIPE_CONN_TYPE_FE,
94	SKL_PIPE_CONN_TYPE_BE
95};
96
97enum skl_hw_conn_type {
98	SKL_CONN_NONE = 0,
99	SKL_CONN_SOURCE = 1,
100	SKL_CONN_SINK = 2
101};
102
103enum skl_dev_type {
104	SKL_DEVICE_BT = 0x0,
105	SKL_DEVICE_DMIC = 0x1,
106	SKL_DEVICE_I2S = 0x2,
107	SKL_DEVICE_SLIMBUS = 0x3,
108	SKL_DEVICE_HDALINK = 0x4,
109	SKL_DEVICE_HDAHOST = 0x5,
110	SKL_DEVICE_NONE
111};
112
113struct skl_dfw_module_pin {
114	u16 module_id;
115	u16 instance_id;
116} __packed;
117
118struct skl_dfw_module_fmt {
119	u32 channels;
120	u32 freq;
121	u32 bit_depth;
122	u32 valid_bit_depth;
123	u32 ch_cfg;
124} __packed;
125
126struct skl_dfw_module_caps {
127	u32 caps_size;
128	u32 caps[HDA_SST_CFG_MAX];
129};
130
131struct skl_dfw_pipe {
132	u8 pipe_id;
133	u8 pipe_priority;
134	u16 conn_type;
135	u32 memory_pages;
136} __packed;
137
138struct skl_dfw_module {
139	u16 module_id;
140	u16 instance_id;
141	u32 max_mcps;
142	u8 core_id;
143	u8 max_in_queue;
144	u8 max_out_queue;
145	u8 is_loadable;
146	u8 conn_type;
147	u8 dev_type;
148	u8 hw_conn_type;
149	u8 time_slot;
150	u32 obs;
151	u32 ibs;
152	u32 params_fixup;
153	u32 converter;
154	u32 module_type;
155	u32 vbus_id;
156	u8 is_dynamic_in_pin;
157	u8 is_dynamic_out_pin;
158	struct skl_dfw_pipe pipe;
159	struct skl_dfw_module_fmt in_fmt;
160	struct skl_dfw_module_fmt out_fmt;
161	struct skl_dfw_module_pin in_pin[MAX_IN_QUEUE];
162	struct skl_dfw_module_pin out_pin[MAX_OUT_QUEUE];
163	struct skl_dfw_module_caps caps;
164} __packed;
165
166struct skl_dfw_algo_data {
167	u32 max;
168	char *params;
169} __packed;
170
171#endif
172