1/* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33#include <linux/init.h> 34#include <linux/io.h> 35#include <linux/module.h> 36#include <linux/interrupt.h> 37#include <linux/clk.h> 38#include <linux/device.h> 39#include <linux/delay.h> 40#include <linux/slab.h> 41#include <linux/spinlock.h> 42#include <linux/of.h> 43#include <linux/of_address.h> 44#include <linux/of_irq.h> 45#include <linux/of_platform.h> 46 47#include <sound/core.h> 48#include <sound/pcm.h> 49#include <sound/pcm_params.h> 50#include <sound/initval.h> 51#include <sound/soc.h> 52#include <sound/dmaengine_pcm.h> 53 54#include "fsl_ssi.h" 55#include "imx-pcm.h" 56 57/** 58 * FSLSSI_I2S_RATES: sample rates supported by the I2S 59 * 60 * This driver currently only supports the SSI running in I2S slave mode, 61 * which means the codec determines the sample rate. Therefore, we tell 62 * ALSA that we support all rates and let the codec driver decide what rates 63 * are really supported. 64 */ 65#define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS 66 67/** 68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 69 * 70 * The SSI has a limitation in that the samples must be in the same byte 71 * order as the host CPU. This is because when multiple bytes are written 72 * to the STX register, the bytes and bits must be written in the same 73 * order. The STX is a shift register, so all the bits need to be aligned 74 * (bit-endianness must match byte-endianness). Processors typically write 75 * the bits within a byte in the same order that the bytes of a word are 76 * written in. So if the host CPU is big-endian, then only big-endian 77 * samples will be written to STX properly. 78 */ 79#ifdef __BIG_ENDIAN 80#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 83#else 84#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 87#endif 88 89#define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 92#define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 95 96enum fsl_ssi_type { 97 FSL_SSI_MCP8610, 98 FSL_SSI_MX21, 99 FSL_SSI_MX35, 100 FSL_SSI_MX51, 101}; 102 103struct fsl_ssi_reg_val { 104 u32 sier; 105 u32 srcr; 106 u32 stcr; 107 u32 scr; 108}; 109 110struct fsl_ssi_rxtx_reg_val { 111 struct fsl_ssi_reg_val rx; 112 struct fsl_ssi_reg_val tx; 113}; 114 115static const struct reg_default fsl_ssi_reg_defaults[] = { 116 {0x10, 0x00000000}, 117 {0x18, 0x00003003}, 118 {0x1c, 0x00000200}, 119 {0x20, 0x00000200}, 120 {0x24, 0x00040000}, 121 {0x28, 0x00040000}, 122 {0x38, 0x00000000}, 123 {0x48, 0x00000000}, 124 {0x4c, 0x00000000}, 125 {0x54, 0x00000000}, 126 {0x58, 0x00000000}, 127}; 128 129static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 130{ 131 switch (reg) { 132 case CCSR_SSI_SACCEN: 133 case CCSR_SSI_SACCDIS: 134 return false; 135 default: 136 return true; 137 } 138} 139 140static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 141{ 142 switch (reg) { 143 case CCSR_SSI_STX0: 144 case CCSR_SSI_STX1: 145 case CCSR_SSI_SRX0: 146 case CCSR_SSI_SRX1: 147 case CCSR_SSI_SISR: 148 case CCSR_SSI_SFCSR: 149 case CCSR_SSI_SACADD: 150 case CCSR_SSI_SACDAT: 151 case CCSR_SSI_SATAG: 152 case CCSR_SSI_SACCST: 153 return true; 154 default: 155 return false; 156 } 157} 158 159static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 160{ 161 switch (reg) { 162 case CCSR_SSI_SRX0: 163 case CCSR_SSI_SRX1: 164 case CCSR_SSI_SACCST: 165 return false; 166 default: 167 return true; 168 } 169} 170 171static const struct regmap_config fsl_ssi_regconfig = { 172 .max_register = CCSR_SSI_SACCDIS, 173 .reg_bits = 32, 174 .val_bits = 32, 175 .reg_stride = 4, 176 .val_format_endian = REGMAP_ENDIAN_NATIVE, 177 .reg_defaults = fsl_ssi_reg_defaults, 178 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults), 179 .readable_reg = fsl_ssi_readable_reg, 180 .volatile_reg = fsl_ssi_volatile_reg, 181 .writeable_reg = fsl_ssi_writeable_reg, 182 .cache_type = REGCACHE_RBTREE, 183}; 184 185struct fsl_ssi_soc_data { 186 bool imx; 187 bool offline_config; 188 u32 sisr_write_mask; 189}; 190 191/** 192 * fsl_ssi_private: per-SSI private data 193 * 194 * @reg: Pointer to the regmap registers 195 * @irq: IRQ of this SSI 196 * @cpu_dai_drv: CPU DAI driver for this device 197 * 198 * @dai_fmt: DAI configuration this device is currently used with 199 * @i2s_mode: i2s and network mode configuration of the device. Is used to 200 * switch between normal and i2s/network mode 201 * mode depending on the number of channels 202 * @use_dma: DMA is used or FIQ with stream filter 203 * @use_dual_fifo: DMA with support for both FIFOs used 204 * @fifo_deph: Depth of the SSI FIFOs 205 * @rxtx_reg_val: Specific register settings for receive/transmit configuration 206 * 207 * @clk: SSI clock 208 * @baudclk: SSI baud clock for master mode 209 * @baudclk_streams: Active streams that are using baudclk 210 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk 211 * 212 * @dma_params_tx: DMA transmit parameters 213 * @dma_params_rx: DMA receive parameters 214 * @ssi_phys: physical address of the SSI registers 215 * 216 * @fiq_params: FIQ stream filtering parameters 217 * 218 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card 219 * 220 * @dbg_stats: Debugging statistics 221 * 222 * @soc: SoC specific data 223 */ 224struct fsl_ssi_private { 225 struct regmap *regs; 226 int irq; 227 struct snd_soc_dai_driver cpu_dai_drv; 228 229 unsigned int dai_fmt; 230 u8 i2s_mode; 231 bool use_dma; 232 bool use_dual_fifo; 233 bool has_ipg_clk_name; 234 unsigned int fifo_depth; 235 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 236 237 struct clk *clk; 238 struct clk *baudclk; 239 unsigned int baudclk_streams; 240 unsigned int bitclk_freq; 241 242 /*regcache for SFCSR*/ 243 u32 regcache_sfcsr; 244 245 /* DMA params */ 246 struct snd_dmaengine_dai_dma_data dma_params_tx; 247 struct snd_dmaengine_dai_dma_data dma_params_rx; 248 dma_addr_t ssi_phys; 249 250 /* params for non-dma FIQ stream filtered mode */ 251 struct imx_pcm_fiq_params fiq_params; 252 253 /* Used when using fsl-ssi as sound-card. This is only used by ppc and 254 * should be replaced with simple-sound-card. */ 255 struct platform_device *pdev; 256 257 struct fsl_ssi_dbg dbg_stats; 258 259 const struct fsl_ssi_soc_data *soc; 260}; 261 262/* 263 * imx51 and later SoCs have a slightly different IP that allows the 264 * SSI configuration while the SSI unit is running. 265 * 266 * More important, it is necessary on those SoCs to configure the 267 * sperate TX/RX DMA bits just before starting the stream 268 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 269 * sends any DMA requests to the SDMA unit, otherwise it is not defined 270 * how the SDMA unit handles the DMA request. 271 * 272 * SDMA units are present on devices starting at imx35 but the imx35 273 * reference manual states that the DMA bits should not be changed 274 * while the SSI unit is running (SSIEN). So we support the necessary 275 * online configuration of fsl-ssi starting at imx51. 276 */ 277 278static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 279 .imx = false, 280 .offline_config = true, 281 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 282 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 283 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 284}; 285 286static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 287 .imx = true, 288 .offline_config = true, 289 .sisr_write_mask = 0, 290}; 291 292static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 293 .imx = true, 294 .offline_config = true, 295 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 296 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 297 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 298}; 299 300static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 301 .imx = true, 302 .offline_config = false, 303 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 304 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 305}; 306 307static const struct of_device_id fsl_ssi_ids[] = { 308 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 309 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 310 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 311 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 312 {} 313}; 314MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 315 316static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 317{ 318 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 319 SND_SOC_DAIFMT_AC97; 320} 321 322static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) 323{ 324 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 325 SND_SOC_DAIFMT_CBS_CFS; 326} 327 328static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) 329{ 330 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 331 SND_SOC_DAIFMT_CBM_CFS; 332} 333/** 334 * fsl_ssi_isr: SSI interrupt handler 335 * 336 * Although it's possible to use the interrupt handler to send and receive 337 * data to/from the SSI, we use the DMA instead. Programming is more 338 * complicated, but the performance is much better. 339 * 340 * This interrupt handler is used only to gather statistics. 341 * 342 * @irq: IRQ of the SSI device 343 * @dev_id: pointer to the ssi_private structure for this SSI device 344 */ 345static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 346{ 347 struct fsl_ssi_private *ssi_private = dev_id; 348 struct regmap *regs = ssi_private->regs; 349 __be32 sisr; 350 __be32 sisr2; 351 352 /* We got an interrupt, so read the status register to see what we 353 were interrupted for. We mask it with the Interrupt Enable register 354 so that we only check for events that we're interested in. 355 */ 356 regmap_read(regs, CCSR_SSI_SISR, &sisr); 357 358 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 359 /* Clear the bits that we set */ 360 if (sisr2) 361 regmap_write(regs, CCSR_SSI_SISR, sisr2); 362 363 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 364 365 return IRQ_HANDLED; 366} 367 368/* 369 * Enable/Disable all rx/tx config flags at once. 370 */ 371static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 372 bool enable) 373{ 374 struct regmap *regs = ssi_private->regs; 375 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 376 377 if (enable) { 378 regmap_update_bits(regs, CCSR_SSI_SIER, 379 vals->rx.sier | vals->tx.sier, 380 vals->rx.sier | vals->tx.sier); 381 regmap_update_bits(regs, CCSR_SSI_SRCR, 382 vals->rx.srcr | vals->tx.srcr, 383 vals->rx.srcr | vals->tx.srcr); 384 regmap_update_bits(regs, CCSR_SSI_STCR, 385 vals->rx.stcr | vals->tx.stcr, 386 vals->rx.stcr | vals->tx.stcr); 387 } else { 388 regmap_update_bits(regs, CCSR_SSI_SRCR, 389 vals->rx.srcr | vals->tx.srcr, 0); 390 regmap_update_bits(regs, CCSR_SSI_STCR, 391 vals->rx.stcr | vals->tx.stcr, 0); 392 regmap_update_bits(regs, CCSR_SSI_SIER, 393 vals->rx.sier | vals->tx.sier, 0); 394 } 395} 396 397/* 398 * Calculate the bits that have to be disabled for the current stream that is 399 * getting disabled. This keeps the bits enabled that are necessary for the 400 * second stream to work if 'stream_active' is true. 401 * 402 * Detailed calculation: 403 * These are the values that need to be active after disabling. For non-active 404 * second stream, this is 0: 405 * vals_stream * !!stream_active 406 * 407 * The following computes the overall differences between the setup for the 408 * to-disable stream and the active stream, a simple XOR: 409 * vals_disable ^ (vals_stream * !!(stream_active)) 410 * 411 * The full expression adds a mask on all values we care about 412 */ 413#define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 414 ((vals_disable) & \ 415 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 416 417/* 418 * Enable/Disable a ssi configuration. You have to pass either 419 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 420 */ 421static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 422 struct fsl_ssi_reg_val *vals) 423{ 424 struct regmap *regs = ssi_private->regs; 425 struct fsl_ssi_reg_val *avals; 426 int nr_active_streams; 427 u32 scr_val; 428 int keep_active; 429 430 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 431 432 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 433 !!(scr_val & CCSR_SSI_SCR_RE); 434 435 if (nr_active_streams - 1 > 0) 436 keep_active = 1; 437 else 438 keep_active = 0; 439 440 /* Find the other direction values rx or tx which we do not want to 441 * modify */ 442 if (&ssi_private->rxtx_reg_val.rx == vals) 443 avals = &ssi_private->rxtx_reg_val.tx; 444 else 445 avals = &ssi_private->rxtx_reg_val.rx; 446 447 /* If vals should be disabled, start with disabling the unit */ 448 if (!enable) { 449 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 450 keep_active); 451 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 452 } 453 454 /* 455 * We are running on a SoC which does not support online SSI 456 * reconfiguration, so we have to enable all necessary flags at once 457 * even if we do not use them later (capture and playback configuration) 458 */ 459 if (ssi_private->soc->offline_config) { 460 if ((enable && !nr_active_streams) || 461 (!enable && !keep_active)) 462 fsl_ssi_rxtx_config(ssi_private, enable); 463 464 goto config_done; 465 } 466 467 /* 468 * Configure single direction units while the SSI unit is running 469 * (online configuration) 470 */ 471 if (enable) { 472 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 473 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 474 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 475 } else { 476 u32 sier; 477 u32 srcr; 478 u32 stcr; 479 480 /* 481 * Disabling the necessary flags for one of rx/tx while the 482 * other stream is active is a little bit more difficult. We 483 * have to disable only those flags that differ between both 484 * streams (rx XOR tx) and that are set in the stream that is 485 * disabled now. Otherwise we could alter flags of the other 486 * stream 487 */ 488 489 /* These assignments are simply vals without bits set in avals*/ 490 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 491 keep_active); 492 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 493 keep_active); 494 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 495 keep_active); 496 497 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 498 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 499 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 500 } 501 502config_done: 503 /* Enabling of subunits is done after configuration */ 504 if (enable) 505 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 506} 507 508 509static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 510{ 511 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 512} 513 514static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 515{ 516 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 517} 518 519/* 520 * Setup rx/tx register values used to enable/disable the streams. These will 521 * be used later in fsl_ssi_config to setup the streams without the need to 522 * check for all different SSI modes. 523 */ 524static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 525{ 526 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 527 528 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 529 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 530 reg->rx.scr = 0; 531 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 532 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 533 reg->tx.scr = 0; 534 535 if (!fsl_ssi_is_ac97(ssi_private)) { 536 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 537 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 538 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 539 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 540 } 541 542 if (ssi_private->use_dma) { 543 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 544 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 545 } else { 546 reg->rx.sier |= CCSR_SSI_SIER_RIE; 547 reg->tx.sier |= CCSR_SSI_SIER_TIE; 548 } 549 550 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 551 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 552} 553 554static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 555{ 556 struct regmap *regs = ssi_private->regs; 557 558 /* 559 * Setup the clock control register 560 */ 561 regmap_write(regs, CCSR_SSI_STCCR, 562 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 563 regmap_write(regs, CCSR_SSI_SRCCR, 564 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 565 566 /* 567 * Enable AC97 mode and startup the SSI 568 */ 569 regmap_write(regs, CCSR_SSI_SACNT, 570 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 571 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 572 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 573 574 /* 575 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 576 * codec before a stream is started. 577 */ 578 regmap_update_bits(regs, CCSR_SSI_SCR, 579 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 580 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 581 582 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 583} 584 585/** 586 * fsl_ssi_startup: create a new substream 587 * 588 * This is the first function called when a stream is opened. 589 * 590 * If this is the first stream open, then grab the IRQ and program most of 591 * the SSI registers. 592 */ 593static int fsl_ssi_startup(struct snd_pcm_substream *substream, 594 struct snd_soc_dai *dai) 595{ 596 struct snd_soc_pcm_runtime *rtd = substream->private_data; 597 struct fsl_ssi_private *ssi_private = 598 snd_soc_dai_get_drvdata(rtd->cpu_dai); 599 int ret; 600 601 ret = clk_prepare_enable(ssi_private->clk); 602 if (ret) 603 return ret; 604 605 /* When using dual fifo mode, it is safer to ensure an even period 606 * size. If appearing to an odd number while DMA always starts its 607 * task from fifo0, fifo1 would be neglected at the end of each 608 * period. But SSI would still access fifo1 with an invalid data. 609 */ 610 if (ssi_private->use_dual_fifo) 611 snd_pcm_hw_constraint_step(substream->runtime, 0, 612 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 613 614 return 0; 615} 616 617/** 618 * fsl_ssi_shutdown: shutdown the SSI 619 * 620 */ 621static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 622 struct snd_soc_dai *dai) 623{ 624 struct snd_soc_pcm_runtime *rtd = substream->private_data; 625 struct fsl_ssi_private *ssi_private = 626 snd_soc_dai_get_drvdata(rtd->cpu_dai); 627 628 clk_disable_unprepare(ssi_private->clk); 629 630} 631 632/** 633 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock 634 * 635 * Note: This function can be only called when using SSI as DAI master 636 * 637 * Quick instruction for parameters: 638 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels 639 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. 640 */ 641static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 642 struct snd_soc_dai *cpu_dai, 643 struct snd_pcm_hw_params *hw_params) 644{ 645 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 646 struct regmap *regs = ssi_private->regs; 647 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 648 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 649 unsigned long clkrate, baudrate, tmprate; 650 u64 sub, savesub = 100000; 651 unsigned int freq; 652 bool baudclk_is_used; 653 654 /* Prefer the explicitly set bitclock frequency */ 655 if (ssi_private->bitclk_freq) 656 freq = ssi_private->bitclk_freq; 657 else 658 freq = params_channels(hw_params) * 32 * params_rate(hw_params); 659 660 /* Don't apply it to any non-baudclk circumstance */ 661 if (IS_ERR(ssi_private->baudclk)) 662 return -EINVAL; 663 664 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); 665 666 /* It should be already enough to divide clock by setting pm alone */ 667 psr = 0; 668 div2 = 0; 669 670 factor = (div2 + 1) * (7 * psr + 1) * 2; 671 672 for (i = 0; i < 255; i++) { 673 tmprate = freq * factor * (i + 1); 674 675 if (baudclk_is_used) 676 clkrate = clk_get_rate(ssi_private->baudclk); 677 else 678 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 679 680 /* 681 * Hardware limitation: The bclk rate must be 682 * never greater than 1/5 IPG clock rate 683 */ 684 if (clkrate * 5 > clk_get_rate(ssi_private->clk)) 685 continue; 686 687 clkrate /= factor; 688 afreq = clkrate / (i + 1); 689 690 if (freq == afreq) 691 sub = 0; 692 else if (freq / afreq == 1) 693 sub = freq - afreq; 694 else if (afreq / freq == 1) 695 sub = afreq - freq; 696 else 697 continue; 698 699 /* Calculate the fraction */ 700 sub *= 100000; 701 do_div(sub, freq); 702 703 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 704 baudrate = tmprate; 705 savesub = sub; 706 pm = i; 707 } 708 709 /* We are lucky */ 710 if (savesub == 0) 711 break; 712 } 713 714 /* No proper pm found if it is still remaining the initial value */ 715 if (pm == 999) { 716 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 717 return -EINVAL; 718 } 719 720 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 721 (psr ? CCSR_SSI_SxCCR_PSR : 0); 722 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 723 CCSR_SSI_SxCCR_PSR; 724 725 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 726 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 727 else 728 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 729 730 if (!baudclk_is_used) { 731 ret = clk_set_rate(ssi_private->baudclk, baudrate); 732 if (ret) { 733 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 734 return -EINVAL; 735 } 736 } 737 738 return 0; 739} 740 741static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 742 int clk_id, unsigned int freq, int dir) 743{ 744 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 745 746 ssi_private->bitclk_freq = freq; 747 748 return 0; 749} 750 751/** 752 * fsl_ssi_hw_params - program the sample size 753 * 754 * Most of the SSI registers have been programmed in the startup function, 755 * but the word length must be programmed here. Unfortunately, programming 756 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 757 * cause a problem with supporting simultaneous playback and capture. If 758 * the SSI is already playing a stream, then that stream may be temporarily 759 * stopped when you start capture. 760 * 761 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 762 * clock master. 763 */ 764static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 765 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 766{ 767 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 768 struct regmap *regs = ssi_private->regs; 769 unsigned int channels = params_channels(hw_params); 770 unsigned int sample_size = 771 snd_pcm_format_width(params_format(hw_params)); 772 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 773 int ret; 774 u32 scr_val; 775 int enabled; 776 777 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 778 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 779 780 /* 781 * If we're in synchronous mode, and the SSI is already enabled, 782 * then STCCR is already set properly. 783 */ 784 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 785 return 0; 786 787 if (fsl_ssi_is_i2s_master(ssi_private)) { 788 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); 789 if (ret) 790 return ret; 791 792 /* Do not enable the clock if it is already enabled */ 793 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { 794 ret = clk_prepare_enable(ssi_private->baudclk); 795 if (ret) 796 return ret; 797 798 ssi_private->baudclk_streams |= BIT(substream->stream); 799 } 800 } 801 802 if (!fsl_ssi_is_ac97(ssi_private)) { 803 u8 i2smode; 804 /* 805 * Switch to normal net mode in order to have a frame sync 806 * signal every 32 bits instead of 16 bits 807 */ 808 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) 809 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 810 CCSR_SSI_SCR_NET; 811 else 812 i2smode = ssi_private->i2s_mode; 813 814 regmap_update_bits(regs, CCSR_SSI_SCR, 815 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 816 channels == 1 ? 0 : i2smode); 817 } 818 819 /* 820 * FIXME: The documentation says that SxCCR[WL] should not be 821 * modified while the SSI is enabled. The only time this can 822 * happen is if we're trying to do simultaneous playback and 823 * capture in asynchronous mode. Unfortunately, I have been enable 824 * to get that to work at all on the P1022DS. Therefore, we don't 825 * bother to disable/enable the SSI when setting SxCCR[WL], because 826 * the SSI will stop anyway. Maybe one day, this will get fixed. 827 */ 828 829 /* In synchronous mode, the SSI uses STCCR for capture */ 830 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 831 ssi_private->cpu_dai_drv.symmetric_rates) 832 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 833 wl); 834 else 835 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 836 wl); 837 838 return 0; 839} 840 841static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 842 struct snd_soc_dai *cpu_dai) 843{ 844 struct snd_soc_pcm_runtime *rtd = substream->private_data; 845 struct fsl_ssi_private *ssi_private = 846 snd_soc_dai_get_drvdata(rtd->cpu_dai); 847 848 if (fsl_ssi_is_i2s_master(ssi_private) && 849 ssi_private->baudclk_streams & BIT(substream->stream)) { 850 clk_disable_unprepare(ssi_private->baudclk); 851 ssi_private->baudclk_streams &= ~BIT(substream->stream); 852 } 853 854 return 0; 855} 856 857static int _fsl_ssi_set_dai_fmt(struct device *dev, 858 struct fsl_ssi_private *ssi_private, 859 unsigned int fmt) 860{ 861 struct regmap *regs = ssi_private->regs; 862 u32 strcr = 0, stcr, srcr, scr, mask; 863 u8 wm; 864 865 ssi_private->dai_fmt = fmt; 866 867 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { 868 dev_err(dev, "baudclk is missing which is necessary for master mode\n"); 869 return -EINVAL; 870 } 871 872 fsl_ssi_setup_reg_vals(ssi_private); 873 874 regmap_read(regs, CCSR_SSI_SCR, &scr); 875 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 876 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 877 878 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 879 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 880 CCSR_SSI_STCR_TEFS; 881 regmap_read(regs, CCSR_SSI_STCR, &stcr); 882 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 883 stcr &= ~mask; 884 srcr &= ~mask; 885 886 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 887 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 888 case SND_SOC_DAIFMT_I2S: 889 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 890 case SND_SOC_DAIFMT_CBM_CFS: 891 case SND_SOC_DAIFMT_CBS_CFS: 892 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 893 regmap_update_bits(regs, CCSR_SSI_STCCR, 894 CCSR_SSI_SxCCR_DC_MASK, 895 CCSR_SSI_SxCCR_DC(2)); 896 regmap_update_bits(regs, CCSR_SSI_SRCCR, 897 CCSR_SSI_SxCCR_DC_MASK, 898 CCSR_SSI_SxCCR_DC(2)); 899 break; 900 case SND_SOC_DAIFMT_CBM_CFM: 901 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 /* Data on rising edge of bclk, frame low, 1clk before data */ 908 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 909 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 910 break; 911 case SND_SOC_DAIFMT_LEFT_J: 912 /* Data on rising edge of bclk, frame high */ 913 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 914 break; 915 case SND_SOC_DAIFMT_DSP_A: 916 /* Data on rising edge of bclk, frame high, 1clk before data */ 917 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 918 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 919 break; 920 case SND_SOC_DAIFMT_DSP_B: 921 /* Data on rising edge of bclk, frame high */ 922 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 923 CCSR_SSI_STCR_TXBIT0; 924 break; 925 case SND_SOC_DAIFMT_AC97: 926 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 927 break; 928 default: 929 return -EINVAL; 930 } 931 scr |= ssi_private->i2s_mode; 932 933 /* DAI clock inversion */ 934 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 935 case SND_SOC_DAIFMT_NB_NF: 936 /* Nothing to do for both normal cases */ 937 break; 938 case SND_SOC_DAIFMT_IB_NF: 939 /* Invert bit clock */ 940 strcr ^= CCSR_SSI_STCR_TSCKP; 941 break; 942 case SND_SOC_DAIFMT_NB_IF: 943 /* Invert frame clock */ 944 strcr ^= CCSR_SSI_STCR_TFSI; 945 break; 946 case SND_SOC_DAIFMT_IB_IF: 947 /* Invert both clocks */ 948 strcr ^= CCSR_SSI_STCR_TSCKP; 949 strcr ^= CCSR_SSI_STCR_TFSI; 950 break; 951 default: 952 return -EINVAL; 953 } 954 955 /* DAI clock master masks */ 956 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 957 case SND_SOC_DAIFMT_CBS_CFS: 958 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 959 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 960 break; 961 case SND_SOC_DAIFMT_CBM_CFM: 962 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 963 break; 964 case SND_SOC_DAIFMT_CBM_CFS: 965 strcr &= ~CCSR_SSI_STCR_TXDIR; 966 strcr |= CCSR_SSI_STCR_TFDIR; 967 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 968 break; 969 default: 970 if (!fsl_ssi_is_ac97(ssi_private)) 971 return -EINVAL; 972 } 973 974 stcr |= strcr; 975 srcr |= strcr; 976 977 if (ssi_private->cpu_dai_drv.symmetric_rates 978 || fsl_ssi_is_ac97(ssi_private)) { 979 /* Need to clear RXDIR when using SYNC or AC97 mode */ 980 srcr &= ~CCSR_SSI_SRCR_RXDIR; 981 scr |= CCSR_SSI_SCR_SYN; 982 } 983 984 regmap_write(regs, CCSR_SSI_STCR, stcr); 985 regmap_write(regs, CCSR_SSI_SRCR, srcr); 986 regmap_write(regs, CCSR_SSI_SCR, scr); 987 988 /* 989 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't 990 * use FIFO 1. We program the transmit water to signal a DMA transfer 991 * if there are only two (or fewer) elements left in the FIFO. Two 992 * elements equals one frame (left channel, right channel). This value, 993 * however, depends on the depth of the transmit buffer. 994 * 995 * We set the watermark on the same level as the DMA burstsize. For 996 * fiq it is probably better to use the biggest possible watermark 997 * size. 998 */ 999 if (ssi_private->use_dma) 1000 wm = ssi_private->fifo_depth - 2; 1001 else 1002 wm = ssi_private->fifo_depth; 1003 1004 regmap_write(regs, CCSR_SSI_SFCSR, 1005 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 1006 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 1007 1008 if (ssi_private->use_dual_fifo) { 1009 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 1010 CCSR_SSI_SRCR_RFEN1); 1011 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 1012 CCSR_SSI_STCR_TFEN1); 1013 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 1014 CCSR_SSI_SCR_TCH_EN); 1015 } 1016 1017 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1018 fsl_ssi_setup_ac97(ssi_private); 1019 1020 return 0; 1021 1022} 1023 1024/** 1025 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 1026 */ 1027static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 1028{ 1029 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1030 1031 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); 1032} 1033 1034/** 1035 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 1036 * 1037 * Note: This function can be only called when using SSI as DAI master 1038 */ 1039static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 1040 u32 rx_mask, int slots, int slot_width) 1041{ 1042 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1043 struct regmap *regs = ssi_private->regs; 1044 u32 val; 1045 1046 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1047 regmap_read(regs, CCSR_SSI_SCR, &val); 1048 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 1049 if (val && slots < 2) { 1050 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1051 return -EINVAL; 1052 } 1053 1054 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 1055 CCSR_SSI_SxCCR_DC(slots)); 1056 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 1057 CCSR_SSI_SxCCR_DC(slots)); 1058 1059 /* The register SxMSKs needs SSI to provide essential clock due to 1060 * hardware design. So we here temporarily enable SSI to set them. 1061 */ 1062 regmap_read(regs, CCSR_SSI_SCR, &val); 1063 val &= CCSR_SSI_SCR_SSIEN; 1064 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 1065 CCSR_SSI_SCR_SSIEN); 1066 1067 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1068 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1069 1070 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1071 1072 return 0; 1073} 1074 1075/** 1076 * fsl_ssi_trigger: start and stop the DMA transfer. 1077 * 1078 * This function is called by ALSA to start, stop, pause, and resume the DMA 1079 * transfer of data. 1080 * 1081 * The DMA channel is in external master start and pause mode, which 1082 * means the SSI completely controls the flow of data. 1083 */ 1084static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1085 struct snd_soc_dai *dai) 1086{ 1087 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1088 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1089 struct regmap *regs = ssi_private->regs; 1090 1091 switch (cmd) { 1092 case SNDRV_PCM_TRIGGER_START: 1093 case SNDRV_PCM_TRIGGER_RESUME: 1094 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1095 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1096 fsl_ssi_tx_config(ssi_private, true); 1097 else 1098 fsl_ssi_rx_config(ssi_private, true); 1099 break; 1100 1101 case SNDRV_PCM_TRIGGER_STOP: 1102 case SNDRV_PCM_TRIGGER_SUSPEND: 1103 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1104 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1105 fsl_ssi_tx_config(ssi_private, false); 1106 else 1107 fsl_ssi_rx_config(ssi_private, false); 1108 break; 1109 1110 default: 1111 return -EINVAL; 1112 } 1113 1114 if (fsl_ssi_is_ac97(ssi_private)) { 1115 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1116 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1117 else 1118 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1119 } 1120 1121 return 0; 1122} 1123 1124static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1125{ 1126 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 1127 1128 if (ssi_private->soc->imx && ssi_private->use_dma) { 1129 dai->playback_dma_data = &ssi_private->dma_params_tx; 1130 dai->capture_dma_data = &ssi_private->dma_params_rx; 1131 } 1132 1133 return 0; 1134} 1135 1136static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1137 .startup = fsl_ssi_startup, 1138 .shutdown = fsl_ssi_shutdown, 1139 .hw_params = fsl_ssi_hw_params, 1140 .hw_free = fsl_ssi_hw_free, 1141 .set_fmt = fsl_ssi_set_dai_fmt, 1142 .set_sysclk = fsl_ssi_set_dai_sysclk, 1143 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1144 .trigger = fsl_ssi_trigger, 1145}; 1146 1147/* Template for the CPU dai driver structure */ 1148static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1149 .probe = fsl_ssi_dai_probe, 1150 .playback = { 1151 .stream_name = "CPU-Playback", 1152 .channels_min = 1, 1153 .channels_max = 2, 1154 .rates = FSLSSI_I2S_RATES, 1155 .formats = FSLSSI_I2S_FORMATS, 1156 }, 1157 .capture = { 1158 .stream_name = "CPU-Capture", 1159 .channels_min = 1, 1160 .channels_max = 2, 1161 .rates = FSLSSI_I2S_RATES, 1162 .formats = FSLSSI_I2S_FORMATS, 1163 }, 1164 .ops = &fsl_ssi_dai_ops, 1165}; 1166 1167static const struct snd_soc_component_driver fsl_ssi_component = { 1168 .name = "fsl-ssi", 1169}; 1170 1171static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1172 .bus_control = true, 1173 .probe = fsl_ssi_dai_probe, 1174 .playback = { 1175 .stream_name = "AC97 Playback", 1176 .channels_min = 2, 1177 .channels_max = 2, 1178 .rates = SNDRV_PCM_RATE_8000_48000, 1179 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1180 }, 1181 .capture = { 1182 .stream_name = "AC97 Capture", 1183 .channels_min = 2, 1184 .channels_max = 2, 1185 .rates = SNDRV_PCM_RATE_48000, 1186 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1187 }, 1188 .ops = &fsl_ssi_dai_ops, 1189}; 1190 1191 1192static struct fsl_ssi_private *fsl_ac97_data; 1193 1194static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1195 unsigned short val) 1196{ 1197 struct regmap *regs = fsl_ac97_data->regs; 1198 unsigned int lreg; 1199 unsigned int lval; 1200 int ret; 1201 1202 if (reg > 0x7f) 1203 return; 1204 1205 ret = clk_prepare_enable(fsl_ac97_data->clk); 1206 if (ret) { 1207 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1208 ret); 1209 return; 1210 } 1211 1212 lreg = reg << 12; 1213 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1214 1215 lval = val << 4; 1216 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1217 1218 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1219 CCSR_SSI_SACNT_WR); 1220 udelay(100); 1221 1222 clk_disable_unprepare(fsl_ac97_data->clk); 1223} 1224 1225static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1226 unsigned short reg) 1227{ 1228 struct regmap *regs = fsl_ac97_data->regs; 1229 1230 unsigned short val = -1; 1231 u32 reg_val; 1232 unsigned int lreg; 1233 int ret; 1234 1235 ret = clk_prepare_enable(fsl_ac97_data->clk); 1236 if (ret) { 1237 pr_err("ac97 read clk_prepare_enable failed: %d\n", 1238 ret); 1239 return -1; 1240 } 1241 1242 lreg = (reg & 0x7f) << 12; 1243 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1244 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1245 CCSR_SSI_SACNT_RD); 1246 1247 udelay(100); 1248 1249 regmap_read(regs, CCSR_SSI_SACDAT, ®_val); 1250 val = (reg_val >> 4) & 0xffff; 1251 1252 clk_disable_unprepare(fsl_ac97_data->clk); 1253 1254 return val; 1255} 1256 1257static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1258 .read = fsl_ssi_ac97_read, 1259 .write = fsl_ssi_ac97_write, 1260}; 1261 1262/** 1263 * Make every character in a string lower-case 1264 */ 1265static void make_lowercase(char *s) 1266{ 1267 char *p = s; 1268 char c; 1269 1270 while ((c = *p)) { 1271 if ((c >= 'A') && (c <= 'Z')) 1272 *p = c + ('a' - 'A'); 1273 p++; 1274 } 1275} 1276 1277static int fsl_ssi_imx_probe(struct platform_device *pdev, 1278 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1279{ 1280 struct device_node *np = pdev->dev.of_node; 1281 u32 dmas[4]; 1282 int ret; 1283 1284 if (ssi_private->has_ipg_clk_name) 1285 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); 1286 else 1287 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1288 if (IS_ERR(ssi_private->clk)) { 1289 ret = PTR_ERR(ssi_private->clk); 1290 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1291 return ret; 1292 } 1293 1294 if (!ssi_private->has_ipg_clk_name) { 1295 ret = clk_prepare_enable(ssi_private->clk); 1296 if (ret) { 1297 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1298 return ret; 1299 } 1300 } 1301 1302 /* For those SLAVE implementations, we ignore non-baudclk cases 1303 * and, instead, abandon MASTER mode that needs baud clock. 1304 */ 1305 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1306 if (IS_ERR(ssi_private->baudclk)) 1307 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1308 PTR_ERR(ssi_private->baudclk)); 1309 1310 /* 1311 * We have burstsize be "fifo_depth - 2" to match the SSI 1312 * watermark setting in fsl_ssi_startup(). 1313 */ 1314 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; 1315 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; 1316 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; 1317 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; 1318 1319 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1320 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1321 ssi_private->use_dual_fifo = true; 1322 /* When using dual fifo mode, we need to keep watermark 1323 * as even numbers due to dma script limitation. 1324 */ 1325 ssi_private->dma_params_tx.maxburst &= ~0x1; 1326 ssi_private->dma_params_rx.maxburst &= ~0x1; 1327 } 1328 1329 if (!ssi_private->use_dma) { 1330 1331 /* 1332 * Some boards use an incompatible codec. To get it 1333 * working, we are using imx-fiq-pcm-audio, that 1334 * can handle those codecs. DMA is not possible in this 1335 * situation. 1336 */ 1337 1338 ssi_private->fiq_params.irq = ssi_private->irq; 1339 ssi_private->fiq_params.base = iomem; 1340 ssi_private->fiq_params.dma_params_rx = 1341 &ssi_private->dma_params_rx; 1342 ssi_private->fiq_params.dma_params_tx = 1343 &ssi_private->dma_params_tx; 1344 1345 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1346 if (ret) 1347 goto error_pcm; 1348 } else { 1349 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1350 if (ret) 1351 goto error_pcm; 1352 } 1353 1354 return 0; 1355 1356error_pcm: 1357 1358 if (!ssi_private->has_ipg_clk_name) 1359 clk_disable_unprepare(ssi_private->clk); 1360 return ret; 1361} 1362 1363static void fsl_ssi_imx_clean(struct platform_device *pdev, 1364 struct fsl_ssi_private *ssi_private) 1365{ 1366 if (!ssi_private->use_dma) 1367 imx_pcm_fiq_exit(pdev); 1368 if (!ssi_private->has_ipg_clk_name) 1369 clk_disable_unprepare(ssi_private->clk); 1370} 1371 1372static int fsl_ssi_probe(struct platform_device *pdev) 1373{ 1374 struct fsl_ssi_private *ssi_private; 1375 int ret = 0; 1376 struct device_node *np = pdev->dev.of_node; 1377 const struct of_device_id *of_id; 1378 const char *p, *sprop; 1379 const uint32_t *iprop; 1380 struct resource *res; 1381 void __iomem *iomem; 1382 char name[64]; 1383 1384 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1385 if (!of_id || !of_id->data) 1386 return -EINVAL; 1387 1388 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1389 GFP_KERNEL); 1390 if (!ssi_private) { 1391 dev_err(&pdev->dev, "could not allocate DAI object\n"); 1392 return -ENOMEM; 1393 } 1394 1395 ssi_private->soc = of_id->data; 1396 1397 sprop = of_get_property(np, "fsl,mode", NULL); 1398 if (sprop) { 1399 if (!strcmp(sprop, "ac97-slave")) 1400 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; 1401 } 1402 1403 ssi_private->use_dma = !of_property_read_bool(np, 1404 "fsl,fiq-stream-filter"); 1405 1406 if (fsl_ssi_is_ac97(ssi_private)) { 1407 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1408 sizeof(fsl_ssi_ac97_dai)); 1409 1410 fsl_ac97_data = ssi_private; 1411 1412 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1413 if (ret) { 1414 dev_err(&pdev->dev, "could not set AC'97 ops\n"); 1415 return ret; 1416 } 1417 } else { 1418 /* Initialize this copy of the CPU DAI driver structure */ 1419 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1420 sizeof(fsl_ssi_dai_template)); 1421 } 1422 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1423 1424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1425 iomem = devm_ioremap_resource(&pdev->dev, res); 1426 if (IS_ERR(iomem)) 1427 return PTR_ERR(iomem); 1428 ssi_private->ssi_phys = res->start; 1429 1430 ret = of_property_match_string(np, "clock-names", "ipg"); 1431 if (ret < 0) { 1432 ssi_private->has_ipg_clk_name = false; 1433 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1434 &fsl_ssi_regconfig); 1435 } else { 1436 ssi_private->has_ipg_clk_name = true; 1437 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1438 "ipg", iomem, &fsl_ssi_regconfig); 1439 } 1440 if (IS_ERR(ssi_private->regs)) { 1441 dev_err(&pdev->dev, "Failed to init register map\n"); 1442 return PTR_ERR(ssi_private->regs); 1443 } 1444 1445 ssi_private->irq = platform_get_irq(pdev, 0); 1446 if (ssi_private->irq < 0) { 1447 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1448 return ssi_private->irq; 1449 } 1450 1451 /* Are the RX and the TX clocks locked? */ 1452 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1453 if (!fsl_ssi_is_ac97(ssi_private)) 1454 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1455 1456 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1457 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1458 } 1459 1460 /* Determine the FIFO depth. */ 1461 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1462 if (iprop) 1463 ssi_private->fifo_depth = be32_to_cpup(iprop); 1464 else 1465 /* Older 8610 DTs didn't have the fifo-depth property */ 1466 ssi_private->fifo_depth = 8; 1467 1468 dev_set_drvdata(&pdev->dev, ssi_private); 1469 1470 if (ssi_private->soc->imx) { 1471 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); 1472 if (ret) 1473 return ret; 1474 } 1475 1476 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1477 &ssi_private->cpu_dai_drv, 1); 1478 if (ret) { 1479 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1480 goto error_asoc_register; 1481 } 1482 1483 if (ssi_private->use_dma) { 1484 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1485 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1486 ssi_private); 1487 if (ret < 0) { 1488 dev_err(&pdev->dev, "could not claim irq %u\n", 1489 ssi_private->irq); 1490 goto error_asoc_register; 1491 } 1492 } 1493 1494 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1495 if (ret) 1496 goto error_asoc_register; 1497 1498 /* 1499 * If codec-handle property is missing from SSI node, we assume 1500 * that the machine driver uses new binding which does not require 1501 * SSI driver to trigger machine driver's probe. 1502 */ 1503 if (!of_get_property(np, "codec-handle", NULL)) 1504 goto done; 1505 1506 /* Trigger the machine driver's probe function. The platform driver 1507 * name of the machine driver is taken from /compatible property of the 1508 * device tree. We also pass the address of the CPU DAI driver 1509 * structure. 1510 */ 1511 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1512 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1513 p = strrchr(sprop, ','); 1514 if (p) 1515 sprop = p + 1; 1516 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1517 make_lowercase(name); 1518 1519 ssi_private->pdev = 1520 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1521 if (IS_ERR(ssi_private->pdev)) { 1522 ret = PTR_ERR(ssi_private->pdev); 1523 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1524 goto error_sound_card; 1525 } 1526 1527done: 1528 if (ssi_private->dai_fmt) 1529 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, 1530 ssi_private->dai_fmt); 1531 1532 if (fsl_ssi_is_ac97(ssi_private)) { 1533 u32 ssi_idx; 1534 1535 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1536 if (ret) { 1537 dev_err(&pdev->dev, "cannot get SSI index property\n"); 1538 goto error_sound_card; 1539 } 1540 1541 ssi_private->pdev = 1542 platform_device_register_data(NULL, 1543 "ac97-codec", ssi_idx, NULL, 0); 1544 if (IS_ERR(ssi_private->pdev)) { 1545 ret = PTR_ERR(ssi_private->pdev); 1546 dev_err(&pdev->dev, 1547 "failed to register AC97 codec platform: %d\n", 1548 ret); 1549 goto error_sound_card; 1550 } 1551 } 1552 1553 return 0; 1554 1555error_sound_card: 1556 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1557 1558error_asoc_register: 1559 if (ssi_private->soc->imx) 1560 fsl_ssi_imx_clean(pdev, ssi_private); 1561 1562 return ret; 1563} 1564 1565static int fsl_ssi_remove(struct platform_device *pdev) 1566{ 1567 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1568 1569 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1570 1571 if (ssi_private->pdev) 1572 platform_device_unregister(ssi_private->pdev); 1573 1574 if (ssi_private->soc->imx) 1575 fsl_ssi_imx_clean(pdev, ssi_private); 1576 1577 if (fsl_ssi_is_ac97(ssi_private)) 1578 snd_soc_set_ac97_ops(NULL); 1579 1580 return 0; 1581} 1582 1583#ifdef CONFIG_PM_SLEEP 1584static int fsl_ssi_suspend(struct device *dev) 1585{ 1586 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1587 struct regmap *regs = ssi_private->regs; 1588 1589 regmap_read(regs, CCSR_SSI_SFCSR, 1590 &ssi_private->regcache_sfcsr); 1591 1592 regcache_cache_only(regs, true); 1593 regcache_mark_dirty(regs); 1594 1595 return 0; 1596} 1597 1598static int fsl_ssi_resume(struct device *dev) 1599{ 1600 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1601 struct regmap *regs = ssi_private->regs; 1602 1603 regcache_cache_only(regs, false); 1604 1605 regmap_update_bits(regs, CCSR_SSI_SFCSR, 1606 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1607 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1608 ssi_private->regcache_sfcsr); 1609 1610 return regcache_sync(regs); 1611} 1612#endif /* CONFIG_PM_SLEEP */ 1613 1614static const struct dev_pm_ops fsl_ssi_pm = { 1615 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1616}; 1617 1618static struct platform_driver fsl_ssi_driver = { 1619 .driver = { 1620 .name = "fsl-ssi-dai", 1621 .of_match_table = fsl_ssi_ids, 1622 .pm = &fsl_ssi_pm, 1623 }, 1624 .probe = fsl_ssi_probe, 1625 .remove = fsl_ssi_remove, 1626}; 1627 1628module_platform_driver(fsl_ssi_driver); 1629 1630MODULE_ALIAS("platform:fsl-ssi-dai"); 1631MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1632MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1633MODULE_LICENSE("GPL v2"); 1634