1/*
2 *
3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/clocksource.h>
21#include <linux/completion.h>
22#include <linux/delay.h>
23#include <linux/dma-mapping.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/mutex.h>
31#include <linux/of_device.h>
32#include <linux/slab.h>
33#include <linux/time.h>
34
35#include <sound/core.h>
36#include <sound/initval.h>
37
38#include "hda_codec.h"
39#include "hda_controller.h"
40
41/* Defines for Nvidia Tegra HDA support */
42#define HDA_BAR0           0x8000
43
44#define HDA_CFG_CMD        0x1004
45#define HDA_CFG_BAR0       0x1010
46
47#define HDA_ENABLE_IO_SPACE       (1 << 0)
48#define HDA_ENABLE_MEM_SPACE      (1 << 1)
49#define HDA_ENABLE_BUS_MASTER     (1 << 2)
50#define HDA_ENABLE_SERR           (1 << 8)
51#define HDA_DISABLE_INTR          (1 << 10)
52#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
53#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)
54
55/* IPFS */
56#define HDA_IPFS_CONFIG           0x180
57#define HDA_IPFS_EN_FPCI          0x1
58
59#define HDA_IPFS_FPCI_BAR0        0x80
60#define HDA_FPCI_BAR0_START       0x40
61
62#define HDA_IPFS_INTR_MASK        0x188
63#define HDA_IPFS_EN_INTR          (1 << 16)
64
65/* max number of SDs */
66#define NUM_CAPTURE_SD 1
67#define NUM_PLAYBACK_SD 1
68
69struct hda_tegra {
70	struct azx chip;
71	struct device *dev;
72	struct clk *hda_clk;
73	struct clk *hda2codec_2x_clk;
74	struct clk *hda2hdmi_clk;
75	void __iomem *regs;
76	struct work_struct probe_work;
77};
78
79#ifdef CONFIG_PM
80static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
81module_param(power_save, bint, 0644);
82MODULE_PARM_DESC(power_save,
83		 "Automatic power-saving timeout (in seconds, 0 = disable).");
84#else
85#define power_save	0
86#endif
87
88/*
89 * DMA page allocation ops.
90 */
91static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
92			   struct snd_dma_buffer *buf)
93{
94	return snd_dma_alloc_pages(type, bus->dev, size, buf);
95}
96
97static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
98{
99	snd_dma_free_pages(buf);
100}
101
102static int substream_alloc_pages(struct azx *chip,
103				 struct snd_pcm_substream *substream,
104				 size_t size)
105{
106	return snd_pcm_lib_malloc_pages(substream, size);
107}
108
109static int substream_free_pages(struct azx *chip,
110				struct snd_pcm_substream *substream)
111{
112	return snd_pcm_lib_free_pages(substream);
113}
114
115/*
116 * Register access ops. Tegra HDA register access is DWORD only.
117 */
118static void hda_tegra_writel(u32 value, u32 *addr)
119{
120	writel(value, addr);
121}
122
123static u32 hda_tegra_readl(u32 *addr)
124{
125	return readl(addr);
126}
127
128static void hda_tegra_writew(u16 value, u16 *addr)
129{
130	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
131	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
132	u32 v;
133
134	v = readl(dword_addr);
135	v &= ~(0xffff << shift);
136	v |= value << shift;
137	writel(v, dword_addr);
138}
139
140static u16 hda_tegra_readw(u16 *addr)
141{
142	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
143	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
144	u32 v;
145
146	v = readl(dword_addr);
147	return (v >> shift) & 0xffff;
148}
149
150static void hda_tegra_writeb(u8 value, u8 *addr)
151{
152	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
153	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
154	u32 v;
155
156	v = readl(dword_addr);
157	v &= ~(0xff << shift);
158	v |= value << shift;
159	writel(v, dword_addr);
160}
161
162static u8 hda_tegra_readb(u8 *addr)
163{
164	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
165	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
166	u32 v;
167
168	v = readl(dword_addr);
169	return (v >> shift) & 0xff;
170}
171
172static const struct hdac_io_ops hda_tegra_io_ops = {
173	.reg_writel = hda_tegra_writel,
174	.reg_readl = hda_tegra_readl,
175	.reg_writew = hda_tegra_writew,
176	.reg_readw = hda_tegra_readw,
177	.reg_writeb = hda_tegra_writeb,
178	.reg_readb = hda_tegra_readb,
179	.dma_alloc_pages = dma_alloc_pages,
180	.dma_free_pages = dma_free_pages,
181};
182
183static const struct hda_controller_ops hda_tegra_ops = {
184	.substream_alloc_pages = substream_alloc_pages,
185	.substream_free_pages = substream_free_pages,
186};
187
188static void hda_tegra_init(struct hda_tegra *hda)
189{
190	u32 v;
191
192	/* Enable PCI access */
193	v = readl(hda->regs + HDA_IPFS_CONFIG);
194	v |= HDA_IPFS_EN_FPCI;
195	writel(v, hda->regs + HDA_IPFS_CONFIG);
196
197	/* Enable MEM/IO space and bus master */
198	v = readl(hda->regs + HDA_CFG_CMD);
199	v &= ~HDA_DISABLE_INTR;
200	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
201		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
202	writel(v, hda->regs + HDA_CFG_CMD);
203
204	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
205	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
206	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
207
208	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
209	v |= HDA_IPFS_EN_INTR;
210	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
211}
212
213static int hda_tegra_enable_clocks(struct hda_tegra *data)
214{
215	int rc;
216
217	rc = clk_prepare_enable(data->hda_clk);
218	if (rc)
219		return rc;
220	rc = clk_prepare_enable(data->hda2codec_2x_clk);
221	if (rc)
222		goto disable_hda;
223	rc = clk_prepare_enable(data->hda2hdmi_clk);
224	if (rc)
225		goto disable_codec_2x;
226
227	return 0;
228
229disable_codec_2x:
230	clk_disable_unprepare(data->hda2codec_2x_clk);
231disable_hda:
232	clk_disable_unprepare(data->hda_clk);
233	return rc;
234}
235
236#ifdef CONFIG_PM_SLEEP
237static void hda_tegra_disable_clocks(struct hda_tegra *data)
238{
239	clk_disable_unprepare(data->hda2hdmi_clk);
240	clk_disable_unprepare(data->hda2codec_2x_clk);
241	clk_disable_unprepare(data->hda_clk);
242}
243
244/*
245 * power management
246 */
247static int hda_tegra_suspend(struct device *dev)
248{
249	struct snd_card *card = dev_get_drvdata(dev);
250	struct azx *chip = card->private_data;
251	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
252
253	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
254
255	azx_stop_chip(chip);
256	azx_enter_link_reset(chip);
257	hda_tegra_disable_clocks(hda);
258
259	return 0;
260}
261
262static int hda_tegra_resume(struct device *dev)
263{
264	struct snd_card *card = dev_get_drvdata(dev);
265	struct azx *chip = card->private_data;
266	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
267
268	hda_tegra_enable_clocks(hda);
269
270	hda_tegra_init(hda);
271
272	azx_init_chip(chip, 1);
273
274	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
275
276	return 0;
277}
278#endif /* CONFIG_PM_SLEEP */
279
280static const struct dev_pm_ops hda_tegra_pm = {
281	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
282};
283
284static int hda_tegra_dev_disconnect(struct snd_device *device)
285{
286	struct azx *chip = device->device_data;
287
288	chip->bus.shutdown = 1;
289	return 0;
290}
291
292/*
293 * destructor
294 */
295static int hda_tegra_dev_free(struct snd_device *device)
296{
297	struct azx *chip = device->device_data;
298	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
299
300	cancel_work_sync(&hda->probe_work);
301	if (azx_bus(chip)->chip_init) {
302		azx_stop_all_streams(chip);
303		azx_stop_chip(chip);
304	}
305
306	azx_free_stream_pages(chip);
307	azx_free_streams(chip);
308	snd_hdac_bus_exit(azx_bus(chip));
309
310	return 0;
311}
312
313static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
314{
315	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
316	struct hdac_bus *bus = azx_bus(chip);
317	struct device *dev = hda->dev;
318	struct resource *res;
319	int err;
320
321	hda->hda_clk = devm_clk_get(dev, "hda");
322	if (IS_ERR(hda->hda_clk)) {
323		dev_err(dev, "failed to get hda clock\n");
324		return PTR_ERR(hda->hda_clk);
325	}
326	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
327	if (IS_ERR(hda->hda2codec_2x_clk)) {
328		dev_err(dev, "failed to get hda2codec_2x clock\n");
329		return PTR_ERR(hda->hda2codec_2x_clk);
330	}
331	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
332	if (IS_ERR(hda->hda2hdmi_clk)) {
333		dev_err(dev, "failed to get hda2hdmi clock\n");
334		return PTR_ERR(hda->hda2hdmi_clk);
335	}
336
337	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
338	hda->regs = devm_ioremap_resource(dev, res);
339	if (IS_ERR(hda->regs))
340		return PTR_ERR(hda->regs);
341
342	bus->remap_addr = hda->regs + HDA_BAR0;
343	bus->addr = res->start + HDA_BAR0;
344
345	err = hda_tegra_enable_clocks(hda);
346	if (err) {
347		dev_err(dev, "failed to get enable clocks\n");
348		return err;
349	}
350
351	hda_tegra_init(hda);
352
353	return 0;
354}
355
356static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
357{
358	struct hdac_bus *bus = azx_bus(chip);
359	struct snd_card *card = chip->card;
360	int err;
361	unsigned short gcap;
362	int irq_id = platform_get_irq(pdev, 0);
363
364	err = hda_tegra_init_chip(chip, pdev);
365	if (err)
366		return err;
367
368	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
369			     IRQF_SHARED, KBUILD_MODNAME, chip);
370	if (err) {
371		dev_err(chip->card->dev,
372			"unable to request IRQ %d, disabling device\n",
373			irq_id);
374		return err;
375	}
376	bus->irq = irq_id;
377
378	synchronize_irq(bus->irq);
379
380	gcap = azx_readw(chip, GCAP);
381	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
382
383	/* read number of streams from GCAP register instead of using
384	 * hardcoded value
385	 */
386	chip->capture_streams = (gcap >> 8) & 0x0f;
387	chip->playback_streams = (gcap >> 12) & 0x0f;
388	if (!chip->playback_streams && !chip->capture_streams) {
389		/* gcap didn't give any info, switching to old method */
390		chip->playback_streams = NUM_PLAYBACK_SD;
391		chip->capture_streams = NUM_CAPTURE_SD;
392	}
393	chip->capture_index_offset = 0;
394	chip->playback_index_offset = chip->capture_streams;
395	chip->num_streams = chip->playback_streams + chip->capture_streams;
396
397	/* initialize streams */
398	err = azx_init_streams(chip);
399	if (err < 0) {
400		dev_err(card->dev, "failed to initialize streams: %d\n", err);
401		return err;
402	}
403
404	err = azx_alloc_stream_pages(chip);
405	if (err < 0) {
406		dev_err(card->dev, "failed to allocate stream pages: %d\n",
407			err);
408		return err;
409	}
410
411	/* initialize chip */
412	azx_init_chip(chip, 1);
413
414	/* codec detection */
415	if (!bus->codec_mask) {
416		dev_err(card->dev, "no codecs found!\n");
417		return -ENODEV;
418	}
419
420	strcpy(card->driver, "tegra-hda");
421	strcpy(card->shortname, "tegra-hda");
422	snprintf(card->longname, sizeof(card->longname),
423		 "%s at 0x%lx irq %i",
424		 card->shortname, bus->addr, bus->irq);
425
426	return 0;
427}
428
429/*
430 * constructor
431 */
432
433static void hda_tegra_probe_work(struct work_struct *work);
434
435static int hda_tegra_create(struct snd_card *card,
436			    unsigned int driver_caps,
437			    struct hda_tegra *hda)
438{
439	static struct snd_device_ops ops = {
440		.dev_disconnect = hda_tegra_dev_disconnect,
441		.dev_free = hda_tegra_dev_free,
442	};
443	struct azx *chip;
444	int err;
445
446	chip = &hda->chip;
447
448	mutex_init(&chip->open_mutex);
449	chip->card = card;
450	chip->ops = &hda_tegra_ops;
451	chip->driver_caps = driver_caps;
452	chip->driver_type = driver_caps & 0xff;
453	chip->dev_index = 0;
454	INIT_LIST_HEAD(&chip->pcm_list);
455
456	chip->codec_probe_mask = -1;
457
458	chip->single_cmd = false;
459	chip->snoop = true;
460
461	INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
462
463	err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
464	if (err < 0)
465		return err;
466
467	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
468	if (err < 0) {
469		dev_err(card->dev, "Error creating device\n");
470		return err;
471	}
472
473	return 0;
474}
475
476static const struct of_device_id hda_tegra_match[] = {
477	{ .compatible = "nvidia,tegra30-hda" },
478	{},
479};
480MODULE_DEVICE_TABLE(of, hda_tegra_match);
481
482static int hda_tegra_probe(struct platform_device *pdev)
483{
484	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY |
485					  AZX_DCAPS_CORBRP_SELF_CLEAR;
486	struct snd_card *card;
487	struct azx *chip;
488	struct hda_tegra *hda;
489	int err;
490
491	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
492	if (!hda)
493		return -ENOMEM;
494	hda->dev = &pdev->dev;
495	chip = &hda->chip;
496
497	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
498			   THIS_MODULE, 0, &card);
499	if (err < 0) {
500		dev_err(&pdev->dev, "Error creating card!\n");
501		return err;
502	}
503
504	err = hda_tegra_create(card, driver_flags, hda);
505	if (err < 0)
506		goto out_free;
507	card->private_data = chip;
508
509	dev_set_drvdata(&pdev->dev, card);
510	schedule_work(&hda->probe_work);
511
512	return 0;
513
514out_free:
515	snd_card_free(card);
516	return err;
517}
518
519static void hda_tegra_probe_work(struct work_struct *work)
520{
521	struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
522	struct azx *chip = &hda->chip;
523	struct platform_device *pdev = to_platform_device(hda->dev);
524	int err;
525
526	err = hda_tegra_first_init(chip, pdev);
527	if (err < 0)
528		goto out_free;
529
530	/* create codec instances */
531	err = azx_probe_codecs(chip, 0);
532	if (err < 0)
533		goto out_free;
534
535	err = azx_codec_configure(chip);
536	if (err < 0)
537		goto out_free;
538
539	err = snd_card_register(chip->card);
540	if (err < 0)
541		goto out_free;
542
543	chip->running = 1;
544	snd_hda_set_power_save(&chip->bus, power_save * 1000);
545
546 out_free:
547	return; /* no error return from async probe */
548}
549
550static int hda_tegra_remove(struct platform_device *pdev)
551{
552	return snd_card_free(dev_get_drvdata(&pdev->dev));
553}
554
555static void hda_tegra_shutdown(struct platform_device *pdev)
556{
557	struct snd_card *card = dev_get_drvdata(&pdev->dev);
558	struct azx *chip;
559
560	if (!card)
561		return;
562	chip = card->private_data;
563	if (chip && chip->running)
564		azx_stop_chip(chip);
565}
566
567static struct platform_driver tegra_platform_hda = {
568	.driver = {
569		.name = "tegra-hda",
570		.pm = &hda_tegra_pm,
571		.of_match_table = hda_tegra_match,
572	},
573	.probe = hda_tegra_probe,
574	.remove = hda_tegra_remove,
575	.shutdown = hda_tegra_shutdown,
576};
577module_platform_driver(tegra_platform_hda);
578
579MODULE_DESCRIPTION("Tegra HDA bus driver");
580MODULE_LICENSE("GPL v2");
581