1/* 2 * Copyright (c) 2014 Intel Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#if !defined(OPA_PORT_INFO_H) 34#define OPA_PORT_INFO_H 35 36/* Temporary until HFI driver is updated */ 37#ifndef USE_PI_LED_ENABLE 38#define USE_PI_LED_ENABLE 0 39#endif 40 41#define OPA_PORT_LINK_MODE_NOP 0 /* No change */ 42#define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */ 43 44#define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */ 45#define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ 46#define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */ 47#define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */ 48#define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */ 49 50#define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */ 51#define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ 52#define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */ 53#define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */ 54#define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */ 55 56/* Link Down / Neighbor Link Down Reason; indicated as follows: */ 57#define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */ 58#define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 59#define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2 60#define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3 61#define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4 62#define OPA_LINKDOWN_REASON_BAD_SLID 5 63#define OPA_LINKDOWN_REASON_BAD_DLID 6 64#define OPA_LINKDOWN_REASON_BAD_L2 7 65#define OPA_LINKDOWN_REASON_BAD_SC 8 66#define OPA_LINKDOWN_REASON_RCV_ERROR_8 9 67#define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10 68#define OPA_LINKDOWN_REASON_RCV_ERROR_10 11 69#define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12 70#define OPA_LINKDOWN_REASON_PREEMPT_VL15 13 71#define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14 72#define OPA_LINKDOWN_REASON_RCV_ERROR_14 15 73#define OPA_LINKDOWN_REASON_RCV_ERROR_15 16 74#define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17 75#define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18 76#define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19 77#define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20 78#define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21 79#define OPA_LINKDOWN_REASON_BAD_PREEMPT 22 80#define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23 81#define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24 82#define OPA_LINKDOWN_REASON_RCV_ERROR_24 25 83#define OPA_LINKDOWN_REASON_RCV_ERROR_25 26 84#define OPA_LINKDOWN_REASON_RCV_ERROR_26 27 85#define OPA_LINKDOWN_REASON_RCV_ERROR_27 28 86#define OPA_LINKDOWN_REASON_RCV_ERROR_28 29 87#define OPA_LINKDOWN_REASON_RCV_ERROR_29 30 88#define OPA_LINKDOWN_REASON_RCV_ERROR_30 31 89#define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32 90#define OPA_LINKDOWN_REASON_UNKNOWN 33 91/* 34 -reserved */ 92#define OPA_LINKDOWN_REASON_REBOOT 35 93#define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36 94/* 37-38 reserved */ 95#define OPA_LINKDOWN_REASON_FM_BOUNCE 39 96#define OPA_LINKDOWN_REASON_SPEED_POLICY 40 97#define OPA_LINKDOWN_REASON_WIDTH_POLICY 41 98/* 42-48 reserved */ 99#define OPA_LINKDOWN_REASON_DISCONNECTED 49 100#define OPA_LINKDOWN_REASONLOCAL_MEDIA_NOT_INSTALLED 50 101#define OPA_LINKDOWN_REASON_NOT_INSTALLED 51 102#define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52 103/* 53 reserved */ 104#define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54 105/* 55 reserved */ 106#define OPA_LINKDOWN_REASON_POWER_POLICY 56 107#define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57 108#define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58 109/* 59 reserved */ 110#define OPA_LINKDOWN_REASON_SWITCH_MGMT 60 111#define OPA_LINKDOWN_REASON_SMA_DISABLED 61 112/* 62 reserved */ 113#define OPA_LINKDOWN_REASON_TRANSIENT 63 114/* 64-255 reserved */ 115 116/* OPA Link Init reason; indicated as follows: */ 117/* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */ 118#define OPA_LINKINIT_REASON_NOP 0 119#define OPA_LINKINIT_REASON_LINKUP (1 << 4) 120#define OPA_LINKINIT_REASON_FLAPPING (2 << 4) 121#define OPA_LINKINIT_REASON_CLEAR (8 << 4) 122#define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4) 123#define OPA_LINKINIT_QUARANTINED (9 << 4) 124#define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4) 125 126#define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 127#define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 128#define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 129 130#define OPA_LINK_WIDTH_1X 0x0001 131#define OPA_LINK_WIDTH_2X 0x0002 132#define OPA_LINK_WIDTH_3X 0x0004 133#define OPA_LINK_WIDTH_4X 0x0008 134 135#define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) 136#define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) 137#define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5) 138#define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4) 139#define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3) 140/* reserved (1 << 2) */ 141#define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1) 142#define OPA_CAP_MASK3_IsVLrSupported (1 << 0) 143 144/** 145 * new MTU values 146 */ 147enum { 148 OPA_MTU_8192 = 6, 149 OPA_MTU_10240 = 7, 150}; 151 152enum { 153 OPA_PORT_PHYS_CONF_DISCONNECTED = 0, 154 OPA_PORT_PHYS_CONF_STANDARD = 1, 155 OPA_PORT_PHYS_CONF_FIXED = 2, 156 OPA_PORT_PHYS_CONF_VARIABLE = 3, 157 OPA_PORT_PHYS_CONF_SI_PHOTO = 4 158}; 159 160enum port_info_field_masks { 161 /* vl.cap */ 162 OPA_PI_MASK_VL_CAP = 0x1F, 163 /* port_states.ledenable_offlinereason */ 164 OPA_PI_MASK_OFFLINE_REASON = 0x0F, 165 OPA_PI_MASK_LED_ENABLE = 0x40, 166 /* port_states.unsleepstate_downdefstate */ 167 OPA_PI_MASK_UNSLEEP_STATE = 0xF0, 168 OPA_PI_MASK_DOWNDEF_STATE = 0x0F, 169 /* port_states.portphysstate_portstate */ 170 OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0, 171 OPA_PI_MASK_PORT_STATE = 0x0F, 172 /* port_phys_conf */ 173 OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F, 174 /* collectivemask_multicastmask */ 175 OPA_PI_MASK_COLLECT_MASK = 0x38, 176 OPA_PI_MASK_MULTICAST_MASK = 0x07, 177 /* mkeyprotect_lmc */ 178 OPA_PI_MASK_MKEY_PROT_BIT = 0xC0, 179 OPA_PI_MASK_LMC = 0x0F, 180 /* smsl */ 181 OPA_PI_MASK_SMSL = 0x1F, 182 /* partenforce_filterraw */ 183 /* Filter Raw In/Out bits 1 and 2 were removed */ 184 OPA_PI_MASK_LINKINIT_REASON = 0xF0, 185 OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08, 186 OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04, 187 /* operational_vls */ 188 OPA_PI_MASK_OPERATIONAL_VL = 0x1F, 189 /* sa_qp */ 190 OPA_PI_MASK_SA_QP = 0x00FFFFFF, 191 /* sm_trap_qp */ 192 OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF, 193 /* localphy_overrun_errors */ 194 OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0, 195 OPA_PI_MASK_OVERRUN_ERRORS = 0x0F, 196 /* clientrereg_subnettimeout */ 197 OPA_PI_MASK_CLIENT_REREGISTER = 0x80, 198 OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F, 199 /* port_link_mode */ 200 OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10), 201 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5), 202 OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0), 203 /* port_link_crc_mode */ 204 OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00, 205 OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0, 206 OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F, 207 /* port_mode */ 208 OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001, 209 OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002, 210 OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004, 211 OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008, 212 OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010, 213 OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020, 214 OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040, 215 /* flit_control.interleave */ 216 OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12), 217 OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10), 218 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5), 219 OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0), 220 221 /* port_error_action */ 222 OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000, 223 /* 7 bits reserved */ 224 OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000, 225 OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000, 226 OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000, 227 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000, 228 OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000, 229 OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000, 230 OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000, 231 OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000, 232 /* 2 bits reserved */ 233 OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000, 234 OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000, 235 OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800, 236 /* 1 bit reserved */ 237 OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200, 238 /* 1 bit reserved */ 239 OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080, 240 OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040, 241 OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020, 242 OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010, 243 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008, 244 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004, 245 OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002, 246 OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001, 247 248 /* pass_through.res_drctl */ 249 OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01, 250 251 /* buffer_units */ 252 OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11), 253 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), 254 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3), 255 OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0), 256 257 /* neigh_mtu.pvlx_to_mtu */ 258 OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0, 259 OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F, 260 261 /* neigh_mtu.vlstall_hoq_life */ 262 OPA_PI_MASK_VL_STALL = (0x03 << 5), 263 OPA_PI_MASK_HOQ_LIFE = (0x1F << 0), 264 265 /* port_neigh_mode */ 266 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3), 267 OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2), 268 OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0), 269 270 /* resptime_value */ 271 OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F, 272 273 /* mtucap */ 274 OPA_PI_MASK_MTU_CAP = 0x0F, 275}; 276 277#if USE_PI_LED_ENABLE 278struct opa_port_states { 279 u8 reserved; 280 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */ 281 u8 reserved2; 282 u8 portphysstate_portstate; /* 4 bits, 4 bits */ 283}; 284#define PI_LED_ENABLE_SUP 1 285#else 286struct opa_port_states { 287 u8 reserved; 288 u8 offline_reason; /* 2 res, 6 bits */ 289 u8 reserved2; 290 u8 portphysstate_portstate; /* 4 bits, 4 bits */ 291}; 292#define PI_LED_ENABLE_SUP 0 293#endif 294 295struct opa_port_state_info { 296 struct opa_port_states port_states; 297 __be16 link_width_downgrade_tx_active; 298 __be16 link_width_downgrade_rx_active; 299}; 300 301struct opa_port_info { 302 __be32 lid; 303 __be32 flow_control_mask; 304 305 struct { 306 u8 res; /* was inittype */ 307 u8 cap; /* 3 res, 5 bits */ 308 __be16 high_limit; 309 __be16 preempt_limit; 310 u8 arb_high_cap; 311 u8 arb_low_cap; 312 } vl; 313 314 struct opa_port_states port_states; 315 u8 port_phys_conf; /* 4 res, 4 bits */ 316 u8 collectivemask_multicastmask; /* 2 res, 3, 3 */ 317 u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */ 318 u8 smsl; /* 3 res, 5 bits */ 319 320 u8 partenforce_filterraw; /* bit fields */ 321 u8 operational_vls; /* 3 res, 5 bits */ 322 __be16 pkey_8b; 323 __be16 pkey_10b; 324 __be16 mkey_violations; 325 326 __be16 pkey_violations; 327 __be16 qkey_violations; 328 __be32 sm_trap_qp; /* 8 bits, 24 bits */ 329 330 __be32 sa_qp; /* 8 bits, 24 bits */ 331 u8 neigh_port_num; 332 u8 link_down_reason; 333 u8 neigh_link_down_reason; 334 u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */ 335 336 struct { 337 __be16 supported; 338 __be16 enabled; 339 __be16 active; 340 } link_speed; 341 struct { 342 __be16 supported; 343 __be16 enabled; 344 __be16 active; 345 } link_width; 346 struct { 347 __be16 supported; 348 __be16 enabled; 349 __be16 tx_active; 350 __be16 rx_active; 351 } link_width_downgrade; 352 __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */ 353 __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */ 354 355 __be16 port_mode; /* 9 res, bit fields */ 356 struct { 357 __be16 supported; 358 __be16 enabled; 359 } port_packet_format; 360 struct { 361 __be16 interleave; /* 2 res, 2,2,5,5 */ 362 struct { 363 __be16 min_initial; 364 __be16 min_tail; 365 u8 large_pkt_limit; 366 u8 small_pkt_limit; 367 u8 max_small_pkt_limit; 368 u8 preemption_limit; 369 } preemption; 370 } flit_control; 371 372 __be32 reserved4; 373 __be32 port_error_action; /* bit field */ 374 375 struct { 376 u8 egress_port; 377 u8 res_drctl; /* 7 res, 1 */ 378 } pass_through; 379 __be16 mkey_lease_period; 380 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */ 381 382 __be32 reserved5; 383 __be32 sm_lid; 384 385 __be64 mkey; 386 387 __be64 subnet_prefix; 388 389 struct { 390 u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */ 391 } neigh_mtu; 392 393 struct { 394 u8 vlstall_hoqlife; /* 3 bits, 5 bits */ 395 } xmit_q[OPA_MAX_VLS]; 396 397 struct { 398 u8 addr[16]; 399 } ipaddr_ipv6; 400 401 struct { 402 u8 addr[4]; 403 } ipaddr_ipv4; 404 405 u32 reserved6; 406 u32 reserved7; 407 u32 reserved8; 408 409 __be64 neigh_node_guid; 410 411 __be32 ib_cap_mask; 412 __be16 reserved9; /* was ib_cap_mask2 */ 413 __be16 opa_cap_mask; 414 415 __be32 reserved10; /* was link_roundtrip_latency */ 416 __be16 overall_buffer_space; 417 __be16 reserved11; /* was max_credit_hint */ 418 419 __be16 diag_code; 420 struct { 421 u8 buffer; 422 u8 wire; 423 } replay_depth; 424 u8 port_neigh_mode; 425 u8 mtucap; /* 4 res, 4 bits */ 426 427 u8 resptimevalue; /* 3 res, 5 bits */ 428 u8 local_port_num; 429 u8 reserved12; 430 u8 reserved13; /* was guid_cap */ 431} __attribute__ ((packed)); 432 433#endif /* OPA_PORT_INFO_H */ 434