1/*
2 * tc358743 - Toshiba HDMI to CSI-2 bridge
3 *
4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5 * reserved.
6 *
7 * This program is free software; you may redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 * SOFTWARE.
19 *
20 */
21
22/*
23 * References (c = chapter, p = page):
24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
26 */
27
28#ifndef _TC358743_
29#define _TC358743_
30
31enum tc358743_ddc5v_delays {
32	DDC5V_DELAY_0_MS,
33	DDC5V_DELAY_50_MS,
34	DDC5V_DELAY_100_MS,
35	DDC5V_DELAY_200_MS,
36};
37
38enum tc358743_hdmi_detection_delay {
39	HDMI_MODE_DELAY_0_MS,
40	HDMI_MODE_DELAY_25_MS,
41	HDMI_MODE_DELAY_50_MS,
42	HDMI_MODE_DELAY_100_MS,
43};
44
45struct tc358743_platform_data {
46	/* System clock connected to REFCLK (pin H5) */
47	u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
48
49	/* DDC +5V debounce delay to avoid spurious interrupts when the cable
50	 * is connected.
51	 * Sets DDC5V_MODE in register DDC_CTL.
52	 * Default: DDC5V_DELAY_0_MS
53	 */
54	enum tc358743_ddc5v_delays ddc5v_delay;
55
56	bool enable_hdcp;
57
58	/*
59	 * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
60	 * level to somewhere in the middle (e.g. 300), so it can cover speed
61	 * mismatches in input and output ports.
62	 */
63	u16 fifo_level;
64
65	/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
66	u16 pll_prd;
67	u16 pll_fbd;
68
69	/* CSI
70	 * Calculate CSI parameters with REF_02 for the highest resolution your
71	 * CSI interface can handle. The driver will adjust the number of CSI
72	 * lanes in use according to the pixel clock.
73	 *
74	 * The values in brackets are calculated with REF_02 when the number of
75	 * bps pr lane is 823.5 MHz, and can serve as a starting point.
76	 */
77	u32 lineinitcnt;	/* (0x00001770) */
78	u32 lptxtimecnt;	/* (0x00000005) */
79	u32 tclk_headercnt;	/* (0x00001d04) */
80	u32 tclk_trailcnt;	/* (0x00000000) */
81	u32 ths_headercnt;	/* (0x00000505) */
82	u32 twakeup;		/* (0x00004650) */
83	u32 tclk_postcnt;	/* (0x00000000) */
84	u32 ths_trailcnt;	/* (0x00000004) */
85	u32 hstxvregcnt;	/* (0x00000005) */
86
87	/* DVI->HDMI detection delay to avoid unnecessary switching between DVI
88	 * and HDMI mode.
89	 * Sets HDMI_DET_V in register HDMI_DET.
90	 * Default: HDMI_MODE_DELAY_0_MS
91	 */
92	enum tc358743_hdmi_detection_delay hdmi_detection_delay;
93
94	/* Reset PHY automatically when TMDS clock goes from DC to AC.
95	 * Sets PHY_AUTO_RST2 in register PHY_CTL2.
96	 * Default: false
97	 */
98	bool hdmi_phy_auto_reset_tmds_detected;
99
100	/* Reset PHY automatically when TMDS clock passes 21 MHz.
101	 * Sets PHY_AUTO_RST3 in register PHY_CTL2.
102	 * Default: false
103	 */
104	bool hdmi_phy_auto_reset_tmds_in_range;
105
106	/* Reset PHY automatically when TMDS clock is detected.
107	 * Sets PHY_AUTO_RST4 in register PHY_CTL2.
108	 * Default: false
109	 */
110	bool hdmi_phy_auto_reset_tmds_valid;
111
112	/* Reset HDMI PHY automatically when hsync period is out of range.
113	 * Sets H_PI_RST in register HV_RST.
114	 * Default: false
115	 */
116	bool hdmi_phy_auto_reset_hsync_out_of_range;
117
118	/* Reset HDMI PHY automatically when vsync period is out of range.
119	 * Sets V_PI_RST in register HV_RST.
120	 * Default: false
121	 */
122	bool hdmi_phy_auto_reset_vsync_out_of_range;
123};
124
125/* custom controls */
126/* Audio sample rate in Hz */
127#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
128/* Audio present status */
129#define TC358743_CID_AUDIO_PRESENT       (V4L2_CID_USER_TC358743_BASE + 1)
130
131#endif
132