1/*
2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
3 *
4 *  Copyright (C) 2012 Samsung Electrnoics
5 *  SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22 */
23
24#ifndef __LINUX_MFD_MAX77693_PRIV_H
25#define __LINUX_MFD_MAX77693_PRIV_H
26
27#include <linux/i2c.h>
28
29#define MAX77693_REG_INVALID		(0xff)
30
31/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
32enum max77693_pmic_reg {
33	MAX77693_LED_REG_IFLASH1			= 0x00,
34	MAX77693_LED_REG_IFLASH2			= 0x01,
35	MAX77693_LED_REG_ITORCH				= 0x02,
36	MAX77693_LED_REG_ITORCHTIMER			= 0x03,
37	MAX77693_LED_REG_FLASH_TIMER			= 0x04,
38	MAX77693_LED_REG_FLASH_EN			= 0x05,
39	MAX77693_LED_REG_MAX_FLASH1			= 0x06,
40	MAX77693_LED_REG_MAX_FLASH2			= 0x07,
41	MAX77693_LED_REG_MAX_FLASH3			= 0x08,
42	MAX77693_LED_REG_MAX_FLASH4			= 0x09,
43	MAX77693_LED_REG_VOUT_CNTL			= 0x0A,
44	MAX77693_LED_REG_VOUT_FLASH1			= 0x0B,
45	MAX77693_LED_REG_VOUT_FLASH2			= 0x0C,
46	MAX77693_LED_REG_FLASH_INT			= 0x0E,
47	MAX77693_LED_REG_FLASH_INT_MASK			= 0x0F,
48	MAX77693_LED_REG_FLASH_STATUS			= 0x10,
49
50	MAX77693_PMIC_REG_PMIC_ID1			= 0x20,
51	MAX77693_PMIC_REG_PMIC_ID2			= 0x21,
52	MAX77693_PMIC_REG_INTSRC			= 0x22,
53	MAX77693_PMIC_REG_INTSRC_MASK			= 0x23,
54	MAX77693_PMIC_REG_TOPSYS_INT			= 0x24,
55	MAX77693_PMIC_REG_TOPSYS_INT_MASK		= 0x26,
56	MAX77693_PMIC_REG_TOPSYS_STAT			= 0x28,
57	MAX77693_PMIC_REG_MAINCTRL1			= 0x2A,
58	MAX77693_PMIC_REG_LSCNFG			= 0x2B,
59
60	MAX77693_CHG_REG_CHG_INT			= 0xB0,
61	MAX77693_CHG_REG_CHG_INT_MASK			= 0xB1,
62	MAX77693_CHG_REG_CHG_INT_OK			= 0xB2,
63	MAX77693_CHG_REG_CHG_DETAILS_00			= 0xB3,
64	MAX77693_CHG_REG_CHG_DETAILS_01			= 0xB4,
65	MAX77693_CHG_REG_CHG_DETAILS_02			= 0xB5,
66	MAX77693_CHG_REG_CHG_DETAILS_03			= 0xB6,
67	MAX77693_CHG_REG_CHG_CNFG_00			= 0xB7,
68	MAX77693_CHG_REG_CHG_CNFG_01			= 0xB8,
69	MAX77693_CHG_REG_CHG_CNFG_02			= 0xB9,
70	MAX77693_CHG_REG_CHG_CNFG_03			= 0xBA,
71	MAX77693_CHG_REG_CHG_CNFG_04			= 0xBB,
72	MAX77693_CHG_REG_CHG_CNFG_05			= 0xBC,
73	MAX77693_CHG_REG_CHG_CNFG_06			= 0xBD,
74	MAX77693_CHG_REG_CHG_CNFG_07			= 0xBE,
75	MAX77693_CHG_REG_CHG_CNFG_08			= 0xBF,
76	MAX77693_CHG_REG_CHG_CNFG_09			= 0xC0,
77	MAX77693_CHG_REG_CHG_CNFG_10			= 0xC1,
78	MAX77693_CHG_REG_CHG_CNFG_11			= 0xC2,
79	MAX77693_CHG_REG_CHG_CNFG_12			= 0xC3,
80	MAX77693_CHG_REG_CHG_CNFG_13			= 0xC4,
81	MAX77693_CHG_REG_CHG_CNFG_14			= 0xC5,
82	MAX77693_CHG_REG_SAFEOUT_CTRL			= 0xC6,
83
84	MAX77693_PMIC_REG_END,
85};
86
87/* MAX77693 ITORCH register */
88#define TORCH_IOUT1_SHIFT	0
89#define TORCH_IOUT2_SHIFT	4
90#define TORCH_IOUT_MASK(x)	(0xf << (x))
91#define TORCH_IOUT_MIN		15625
92#define TORCH_IOUT_MAX		250000
93#define TORCH_IOUT_STEP		15625
94
95/* MAX77693 IFLASH1 and IFLASH2 registers */
96#define FLASH_IOUT_MIN		15625
97#define FLASH_IOUT_MAX_1LED	1000000
98#define FLASH_IOUT_MAX_2LEDS	625000
99#define FLASH_IOUT_STEP		15625
100
101/* MAX77693 TORCH_TIMER register */
102#define TORCH_TMR_NO_TIMER	0x40
103#define TORCH_TIMEOUT_MIN	262000
104#define TORCH_TIMEOUT_MAX	15728000
105
106/* MAX77693 FLASH_TIMER register */
107#define FLASH_TMR_LEVEL		0x80
108#define FLASH_TIMEOUT_MIN	62500
109#define FLASH_TIMEOUT_MAX	1000000
110#define FLASH_TIMEOUT_STEP	62500
111
112/* MAX77693 FLASH_EN register */
113#define FLASH_EN_OFF		0x0
114#define FLASH_EN_FLASH		0x1
115#define FLASH_EN_TORCH		0x2
116#define FLASH_EN_ON		0x3
117#define FLASH_EN_SHIFT(x)	(6 - (x) * 2)
118#define TORCH_EN_SHIFT(x)	(2 - (x) * 2)
119
120/* MAX77693 MAX_FLASH1 register */
121#define MAX_FLASH1_MAX_FL_EN	0x80
122#define MAX_FLASH1_VSYS_MIN	2400
123#define MAX_FLASH1_VSYS_MAX	3400
124#define MAX_FLASH1_VSYS_STEP	33
125
126/* MAX77693 VOUT_CNTL register */
127#define FLASH_BOOST_FIXED	0x04
128#define FLASH_BOOST_LEDNUM_2	0x80
129
130/* MAX77693 VOUT_FLASH1 register */
131#define FLASH_VOUT_MIN		3300
132#define FLASH_VOUT_MAX		5500
133#define FLASH_VOUT_STEP		25
134#define FLASH_VOUT_RMIN		0x0c
135
136/* MAX77693 FLASH_STATUS register */
137#define FLASH_STATUS_FLASH_ON	BIT(3)
138#define FLASH_STATUS_TORCH_ON	BIT(2)
139
140/* MAX77693 FLASH_INT register */
141#define FLASH_INT_FLED2_OPEN	BIT(0)
142#define FLASH_INT_FLED2_SHORT	BIT(1)
143#define FLASH_INT_FLED1_OPEN	BIT(2)
144#define FLASH_INT_FLED1_SHORT	BIT(3)
145#define FLASH_INT_OVER_CURRENT	BIT(4)
146
147/* Fast charge timer in in hours */
148#define DEFAULT_FAST_CHARGE_TIMER		4
149/* microamps */
150#define DEFAULT_TOP_OFF_THRESHOLD_CURRENT	150000
151/* minutes */
152#define DEFAULT_TOP_OFF_TIMER			30
153/* microvolts */
154#define DEFAULT_CONSTANT_VOLT			4200000
155/* microvolts */
156#define DEFAULT_MIN_SYSTEM_VOLT			3600000
157/* celsius */
158#define DEFAULT_THERMAL_REGULATION_TEMP		100
159/* microamps */
160#define DEFAULT_BATTERY_OVERCURRENT		3500000
161/* microvolts */
162#define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT	4300000
163
164/* MAX77693_CHG_REG_CHG_INT_OK register */
165#define CHG_INT_OK_BYP_SHIFT		0
166#define CHG_INT_OK_BAT_SHIFT		3
167#define CHG_INT_OK_CHG_SHIFT		4
168#define CHG_INT_OK_CHGIN_SHIFT		6
169#define CHG_INT_OK_DETBAT_SHIFT		7
170#define CHG_INT_OK_BYP_MASK		BIT(CHG_INT_OK_BYP_SHIFT)
171#define CHG_INT_OK_BAT_MASK		BIT(CHG_INT_OK_BAT_SHIFT)
172#define CHG_INT_OK_CHG_MASK		BIT(CHG_INT_OK_CHG_SHIFT)
173#define CHG_INT_OK_CHGIN_MASK		BIT(CHG_INT_OK_CHGIN_SHIFT)
174#define CHG_INT_OK_DETBAT_MASK		BIT(CHG_INT_OK_DETBAT_SHIFT)
175
176/* MAX77693_CHG_REG_CHG_DETAILS_00 register */
177#define CHG_DETAILS_00_CHGIN_SHIFT	5
178#define CHG_DETAILS_00_CHGIN_MASK	(0x3 << CHG_DETAILS_00_CHGIN_SHIFT)
179
180/* MAX77693_CHG_REG_CHG_DETAILS_01 register */
181#define CHG_DETAILS_01_CHG_SHIFT	0
182#define CHG_DETAILS_01_BAT_SHIFT	4
183#define CHG_DETAILS_01_TREG_SHIFT	7
184#define CHG_DETAILS_01_CHG_MASK		(0xf << CHG_DETAILS_01_CHG_SHIFT)
185#define CHG_DETAILS_01_BAT_MASK		(0x7 << CHG_DETAILS_01_BAT_SHIFT)
186#define CHG_DETAILS_01_TREG_MASK	BIT(7)
187
188/* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */
189enum max77693_charger_charging_state {
190	MAX77693_CHARGING_PREQUALIFICATION	= 0x0,
191	MAX77693_CHARGING_FAST_CONST_CURRENT,
192	MAX77693_CHARGING_FAST_CONST_VOLTAGE,
193	MAX77693_CHARGING_TOP_OFF,
194	MAX77693_CHARGING_DONE,
195	MAX77693_CHARGING_HIGH_TEMP,
196	MAX77693_CHARGING_TIMER_EXPIRED,
197	MAX77693_CHARGING_THERMISTOR_SUSPEND,
198	MAX77693_CHARGING_OFF,
199	MAX77693_CHARGING_RESERVED,
200	MAX77693_CHARGING_OVER_TEMP,
201	MAX77693_CHARGING_WATCHDOG_EXPIRED,
202};
203
204/* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */
205enum max77693_charger_battery_state {
206	MAX77693_BATTERY_NOBAT			= 0x0,
207	/* Dead-battery or low-battery prequalification */
208	MAX77693_BATTERY_PREQUALIFICATION,
209	MAX77693_BATTERY_TIMER_EXPIRED,
210	MAX77693_BATTERY_GOOD,
211	MAX77693_BATTERY_LOWVOLTAGE,
212	MAX77693_BATTERY_OVERVOLTAGE,
213	MAX77693_BATTERY_OVERCURRENT,
214	MAX77693_BATTERY_RESERVED,
215};
216
217/* MAX77693_CHG_REG_CHG_DETAILS_02 register */
218#define CHG_DETAILS_02_BYP_SHIFT	0
219#define CHG_DETAILS_02_BYP_MASK		(0xf << CHG_DETAILS_02_BYP_SHIFT)
220
221/* MAX77693 CHG_CNFG_00 register */
222#define CHG_CNFG_00_CHG_MASK		0x1
223#define CHG_CNFG_00_BUCK_MASK		0x4
224
225/* MAX77693_CHG_REG_CHG_CNFG_01 register */
226#define CHG_CNFG_01_FCHGTIME_SHIFT	0
227#define CHG_CNFG_01_CHGRSTRT_SHIFT	4
228#define CHG_CNFG_01_PQEN_SHIFT		7
229#define CHG_CNFG_01_FCHGTIME_MASK	(0x7 << CHG_CNFG_01_FCHGTIME_SHIFT)
230#define CHG_CNFG_01_CHGRSTRT_MASK	(0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT)
231#define CHG_CNFG_01_PQEN_MAKS		BIT(CHG_CNFG_01_PQEN_SHIFT)
232
233/* MAX77693_CHG_REG_CHG_CNFG_03 register */
234#define CHG_CNFG_03_TOITH_SHIFT		0
235#define CHG_CNFG_03_TOTIME_SHIFT	3
236#define CHG_CNFG_03_TOITH_MASK		(0x7 << CHG_CNFG_03_TOITH_SHIFT)
237#define CHG_CNFG_03_TOTIME_MASK		(0x7 << CHG_CNFG_03_TOTIME_SHIFT)
238
239/* MAX77693_CHG_REG_CHG_CNFG_04 register */
240#define CHG_CNFG_04_CHGCVPRM_SHIFT	0
241#define CHG_CNFG_04_MINVSYS_SHIFT	5
242#define CHG_CNFG_04_CHGCVPRM_MASK	(0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT)
243#define CHG_CNFG_04_MINVSYS_MASK	(0x7 << CHG_CNFG_04_MINVSYS_SHIFT)
244
245/* MAX77693_CHG_REG_CHG_CNFG_06 register */
246#define CHG_CNFG_06_CHGPROT_SHIFT	2
247#define CHG_CNFG_06_CHGPROT_MASK	(0x3 << CHG_CNFG_06_CHGPROT_SHIFT)
248
249/* MAX77693_CHG_REG_CHG_CNFG_07 register */
250#define CHG_CNFG_07_REGTEMP_SHIFT	5
251#define CHG_CNFG_07_REGTEMP_MASK	(0x3 << CHG_CNFG_07_REGTEMP_SHIFT)
252
253/* MAX77693_CHG_REG_CHG_CNFG_12 register */
254#define CHG_CNFG_12_B2SOVRC_SHIFT	0
255#define CHG_CNFG_12_VCHGINREG_SHIFT	3
256#define CHG_CNFG_12_B2SOVRC_MASK	(0x7 << CHG_CNFG_12_B2SOVRC_SHIFT)
257#define CHG_CNFG_12_VCHGINREG_MASK	(0x3 << CHG_CNFG_12_VCHGINREG_SHIFT)
258
259/* MAX77693 CHG_CNFG_09 Register */
260#define CHG_CNFG_09_CHGIN_ILIM_MASK	0x7F
261
262/* MAX77693 CHG_CTRL Register */
263#define SAFEOUT_CTRL_SAFEOUT1_MASK	0x3
264#define SAFEOUT_CTRL_SAFEOUT2_MASK	0xC
265#define SAFEOUT_CTRL_ENSAFEOUT1_MASK	0x40
266#define SAFEOUT_CTRL_ENSAFEOUT2_MASK	0x80
267
268/* Slave addr = 0x4A: MUIC */
269enum max77693_muic_reg {
270	MAX77693_MUIC_REG_ID		= 0x00,
271	MAX77693_MUIC_REG_INT1		= 0x01,
272	MAX77693_MUIC_REG_INT2		= 0x02,
273	MAX77693_MUIC_REG_INT3		= 0x03,
274	MAX77693_MUIC_REG_STATUS1	= 0x04,
275	MAX77693_MUIC_REG_STATUS2	= 0x05,
276	MAX77693_MUIC_REG_STATUS3	= 0x06,
277	MAX77693_MUIC_REG_INTMASK1	= 0x07,
278	MAX77693_MUIC_REG_INTMASK2	= 0x08,
279	MAX77693_MUIC_REG_INTMASK3	= 0x09,
280	MAX77693_MUIC_REG_CDETCTRL1	= 0x0A,
281	MAX77693_MUIC_REG_CDETCTRL2	= 0x0B,
282	MAX77693_MUIC_REG_CTRL1		= 0x0C,
283	MAX77693_MUIC_REG_CTRL2		= 0x0D,
284	MAX77693_MUIC_REG_CTRL3		= 0x0E,
285
286	MAX77693_MUIC_REG_END,
287};
288
289/* MAX77693 INTMASK1~2 Register */
290#define INTMASK1_ADC1K_SHIFT		3
291#define INTMASK1_ADCERR_SHIFT		2
292#define INTMASK1_ADCLOW_SHIFT		1
293#define INTMASK1_ADC_SHIFT		0
294#define INTMASK1_ADC1K_MASK		(1 << INTMASK1_ADC1K_SHIFT)
295#define INTMASK1_ADCERR_MASK		(1 << INTMASK1_ADCERR_SHIFT)
296#define INTMASK1_ADCLOW_MASK		(1 << INTMASK1_ADCLOW_SHIFT)
297#define INTMASK1_ADC_MASK		(1 << INTMASK1_ADC_SHIFT)
298
299#define INTMASK2_VIDRM_SHIFT		5
300#define INTMASK2_VBVOLT_SHIFT		4
301#define INTMASK2_DXOVP_SHIFT		3
302#define INTMASK2_DCDTMR_SHIFT		2
303#define INTMASK2_CHGDETRUN_SHIFT	1
304#define INTMASK2_CHGTYP_SHIFT		0
305#define INTMASK2_VIDRM_MASK		(1 << INTMASK2_VIDRM_SHIFT)
306#define INTMASK2_VBVOLT_MASK		(1 << INTMASK2_VBVOLT_SHIFT)
307#define INTMASK2_DXOVP_MASK		(1 << INTMASK2_DXOVP_SHIFT)
308#define INTMASK2_DCDTMR_MASK		(1 << INTMASK2_DCDTMR_SHIFT)
309#define INTMASK2_CHGDETRUN_MASK		(1 << INTMASK2_CHGDETRUN_SHIFT)
310#define INTMASK2_CHGTYP_MASK		(1 << INTMASK2_CHGTYP_SHIFT)
311
312/* MAX77693 MUIC - STATUS1~3 Register */
313#define MAX77693_STATUS1_ADC_SHIFT		0
314#define MAX77693_STATUS1_ADCLOW_SHIFT		5
315#define MAX77693_STATUS1_ADCERR_SHIFT		6
316#define MAX77693_STATUS1_ADC1K_SHIFT		7
317#define MAX77693_STATUS1_ADC_MASK		(0x1f << MAX77693_STATUS1_ADC_SHIFT)
318#define MAX77693_STATUS1_ADCLOW_MASK		BIT(MAX77693_STATUS1_ADCLOW_SHIFT)
319#define MAX77693_STATUS1_ADCERR_MASK		BIT(MAX77693_STATUS1_ADCERR_SHIFT)
320#define MAX77693_STATUS1_ADC1K_MASK		BIT(MAX77693_STATUS1_ADC1K_SHIFT)
321
322#define MAX77693_STATUS2_CHGTYP_SHIFT		0
323#define MAX77693_STATUS2_CHGDETRUN_SHIFT	3
324#define MAX77693_STATUS2_DCDTMR_SHIFT		4
325#define MAX77693_STATUS2_DXOVP_SHIFT		5
326#define MAX77693_STATUS2_VBVOLT_SHIFT		6
327#define MAX77693_STATUS2_VIDRM_SHIFT		7
328#define MAX77693_STATUS2_CHGTYP_MASK		(0x7 << MAX77693_STATUS2_CHGTYP_SHIFT)
329#define MAX77693_STATUS2_CHGDETRUN_MASK		BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT)
330#define MAX77693_STATUS2_DCDTMR_MASK		BIT(MAX77693_STATUS2_DCDTMR_SHIFT)
331#define MAX77693_STATUS2_DXOVP_MASK		BIT(MAX77693_STATUS2_DXOVP_SHIFT)
332#define MAX77693_STATUS2_VBVOLT_MASK		BIT(MAX77693_STATUS2_VBVOLT_SHIFT)
333#define MAX77693_STATUS2_VIDRM_MASK		BIT(MAX77693_STATUS2_VIDRM_SHIFT)
334
335#define MAX77693_STATUS3_OVP_SHIFT		2
336#define MAX77693_STATUS3_OVP_MASK		BIT(MAX77693_STATUS3_OVP_SHIFT)
337
338/* MAX77693 CDETCTRL1~2 register */
339#define CDETCTRL1_CHGDETEN_SHIFT	(0)
340#define CDETCTRL1_CHGTYPMAN_SHIFT	(1)
341#define CDETCTRL1_DCDEN_SHIFT		(2)
342#define CDETCTRL1_DCD2SCT_SHIFT		(3)
343#define CDETCTRL1_CDDELAY_SHIFT		(4)
344#define CDETCTRL1_DCDCPL_SHIFT		(5)
345#define CDETCTRL1_CDPDET_SHIFT		(7)
346#define CDETCTRL1_CHGDETEN_MASK		(0x1 << CDETCTRL1_CHGDETEN_SHIFT)
347#define CDETCTRL1_CHGTYPMAN_MASK	(0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
348#define CDETCTRL1_DCDEN_MASK		(0x1 << CDETCTRL1_DCDEN_SHIFT)
349#define CDETCTRL1_DCD2SCT_MASK		(0x1 << CDETCTRL1_DCD2SCT_SHIFT)
350#define CDETCTRL1_CDDELAY_MASK		(0x1 << CDETCTRL1_CDDELAY_SHIFT)
351#define CDETCTRL1_DCDCPL_MASK		(0x1 << CDETCTRL1_DCDCPL_SHIFT)
352#define CDETCTRL1_CDPDET_MASK		(0x1 << CDETCTRL1_CDPDET_SHIFT)
353
354#define CDETCTRL2_VIDRMEN_SHIFT		(1)
355#define CDETCTRL2_DXOVPEN_SHIFT		(3)
356#define CDETCTRL2_VIDRMEN_MASK		(0x1 << CDETCTRL2_VIDRMEN_SHIFT)
357#define CDETCTRL2_DXOVPEN_MASK		(0x1 << CDETCTRL2_DXOVPEN_SHIFT)
358
359/* MAX77693 MUIC - CONTROL1~3 register */
360#define COMN1SW_SHIFT			(0)
361#define COMP2SW_SHIFT			(3)
362#define COMN1SW_MASK			(0x7 << COMN1SW_SHIFT)
363#define COMP2SW_MASK			(0x7 << COMP2SW_SHIFT)
364#define COMP_SW_MASK			(COMP2SW_MASK | COMN1SW_MASK)
365#define MAX77693_CONTROL1_SW_USB	((1 << COMP2SW_SHIFT) \
366						| (1 << COMN1SW_SHIFT))
367#define MAX77693_CONTROL1_SW_AUDIO	((2 << COMP2SW_SHIFT) \
368						| (2 << COMN1SW_SHIFT))
369#define MAX77693_CONTROL1_SW_UART	((3 << COMP2SW_SHIFT) \
370						| (3 << COMN1SW_SHIFT))
371#define MAX77693_CONTROL1_SW_OPEN	((0 << COMP2SW_SHIFT) \
372						| (0 << COMN1SW_SHIFT))
373
374#define MAX77693_CONTROL2_LOWPWR_SHIFT		0
375#define MAX77693_CONTROL2_ADCEN_SHIFT		1
376#define MAX77693_CONTROL2_CPEN_SHIFT		2
377#define MAX77693_CONTROL2_SFOUTASRT_SHIFT	3
378#define MAX77693_CONTROL2_SFOUTORD_SHIFT	4
379#define MAX77693_CONTROL2_ACCDET_SHIFT		5
380#define MAX77693_CONTROL2_USBCPINT_SHIFT	6
381#define MAX77693_CONTROL2_RCPS_SHIFT		7
382#define MAX77693_CONTROL2_LOWPWR_MASK		BIT(MAX77693_CONTROL2_LOWPWR_SHIFT)
383#define MAX77693_CONTROL2_ADCEN_MASK		BIT(MAX77693_CONTROL2_ADCEN_SHIFT)
384#define MAX77693_CONTROL2_CPEN_MASK		BIT(MAX77693_CONTROL2_CPEN_SHIFT)
385#define MAX77693_CONTROL2_SFOUTASRT_MASK	BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT)
386#define MAX77693_CONTROL2_SFOUTORD_MASK		BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT)
387#define MAX77693_CONTROL2_ACCDET_MASK		BIT(MAX77693_CONTROL2_ACCDET_SHIFT)
388#define MAX77693_CONTROL2_USBCPINT_MASK		BIT(MAX77693_CONTROL2_USBCPINT_SHIFT)
389#define MAX77693_CONTROL2_RCPS_MASK		BIT(MAX77693_CONTROL2_RCPS_SHIFT)
390
391#define MAX77693_CONTROL3_JIGSET_SHIFT		0
392#define MAX77693_CONTROL3_BTLDSET_SHIFT		2
393#define MAX77693_CONTROL3_ADCDBSET_SHIFT	4
394#define MAX77693_CONTROL3_JIGSET_MASK		(0x3 << MAX77693_CONTROL3_JIGSET_SHIFT)
395#define MAX77693_CONTROL3_BTLDSET_MASK		(0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT)
396#define MAX77693_CONTROL3_ADCDBSET_MASK		(0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT)
397
398/* Slave addr = 0x90: Haptic */
399enum max77693_haptic_reg {
400	MAX77693_HAPTIC_REG_STATUS		= 0x00,
401	MAX77693_HAPTIC_REG_CONFIG1		= 0x01,
402	MAX77693_HAPTIC_REG_CONFIG2		= 0x02,
403	MAX77693_HAPTIC_REG_CONFIG_CHNL		= 0x03,
404	MAX77693_HAPTIC_REG_CONFG_CYC1		= 0x04,
405	MAX77693_HAPTIC_REG_CONFG_CYC2		= 0x05,
406	MAX77693_HAPTIC_REG_CONFIG_PER1		= 0x06,
407	MAX77693_HAPTIC_REG_CONFIG_PER2		= 0x07,
408	MAX77693_HAPTIC_REG_CONFIG_PER3		= 0x08,
409	MAX77693_HAPTIC_REG_CONFIG_PER4		= 0x09,
410	MAX77693_HAPTIC_REG_CONFIG_DUTY1	= 0x0A,
411	MAX77693_HAPTIC_REG_CONFIG_DUTY2	= 0x0B,
412	MAX77693_HAPTIC_REG_CONFIG_PWM1		= 0x0C,
413	MAX77693_HAPTIC_REG_CONFIG_PWM2		= 0x0D,
414	MAX77693_HAPTIC_REG_CONFIG_PWM3		= 0x0E,
415	MAX77693_HAPTIC_REG_CONFIG_PWM4		= 0x0F,
416	MAX77693_HAPTIC_REG_REV			= 0x10,
417
418	MAX77693_HAPTIC_REG_END,
419};
420
421/* max77693-pmic LSCNFG configuraton register */
422#define MAX77693_PMIC_LOW_SYS_MASK      0x80
423#define MAX77693_PMIC_LOW_SYS_SHIFT     7
424
425/* max77693-haptic configuration register */
426#define MAX77693_CONFIG2_MODE           7
427#define MAX77693_CONFIG2_MEN            6
428#define MAX77693_CONFIG2_HTYP           5
429
430enum max77693_irq_source {
431	LED_INT = 0,
432	TOPSYS_INT,
433	CHG_INT,
434	MUIC_INT1,
435	MUIC_INT2,
436	MUIC_INT3,
437
438	MAX77693_IRQ_GROUP_NR,
439};
440
441#define SRC_IRQ_CHARGER			BIT(0)
442#define SRC_IRQ_TOP			BIT(1)
443#define SRC_IRQ_FLASH			BIT(2)
444#define SRC_IRQ_MUIC			BIT(3)
445#define SRC_IRQ_ALL			(SRC_IRQ_CHARGER | SRC_IRQ_TOP \
446						| SRC_IRQ_FLASH | SRC_IRQ_MUIC)
447
448#define LED_IRQ_FLED2_OPEN		BIT(0)
449#define LED_IRQ_FLED2_SHORT		BIT(1)
450#define LED_IRQ_FLED1_OPEN		BIT(2)
451#define LED_IRQ_FLED1_SHORT		BIT(3)
452#define LED_IRQ_MAX_FLASH		BIT(4)
453
454#define TOPSYS_IRQ_T120C_INT		BIT(0)
455#define TOPSYS_IRQ_T140C_INT		BIT(1)
456#define TOPSYS_IRQ_LOWSYS_INT		BIT(3)
457
458#define CHG_IRQ_BYP_I			BIT(0)
459#define CHG_IRQ_THM_I			BIT(2)
460#define CHG_IRQ_BAT_I			BIT(3)
461#define CHG_IRQ_CHG_I			BIT(4)
462#define CHG_IRQ_CHGIN_I			BIT(6)
463
464#define MUIC_IRQ_INT1_ADC		BIT(0)
465#define MUIC_IRQ_INT1_ADC_LOW		BIT(1)
466#define MUIC_IRQ_INT1_ADC_ERR		BIT(2)
467#define MUIC_IRQ_INT1_ADC1K		BIT(3)
468
469#define MUIC_IRQ_INT2_CHGTYP		BIT(0)
470#define MUIC_IRQ_INT2_CHGDETREUN	BIT(1)
471#define MUIC_IRQ_INT2_DCDTMR		BIT(2)
472#define MUIC_IRQ_INT2_DXOVP		BIT(3)
473#define MUIC_IRQ_INT2_VBVOLT		BIT(4)
474#define MUIC_IRQ_INT2_VIDRM		BIT(5)
475
476#define MUIC_IRQ_INT3_EOC		BIT(0)
477#define MUIC_IRQ_INT3_CGMBC		BIT(1)
478#define MUIC_IRQ_INT3_OVP		BIT(2)
479#define MUIC_IRQ_INT3_MBCCHG_ERR	BIT(3)
480#define MUIC_IRQ_INT3_CHG_ENABLED	BIT(4)
481#define MUIC_IRQ_INT3_BAT_DET		BIT(5)
482
483enum max77693_irq {
484	/* PMIC - FLASH */
485	MAX77693_LED_IRQ_FLED2_OPEN,
486	MAX77693_LED_IRQ_FLED2_SHORT,
487	MAX77693_LED_IRQ_FLED1_OPEN,
488	MAX77693_LED_IRQ_FLED1_SHORT,
489	MAX77693_LED_IRQ_MAX_FLASH,
490
491	/* PMIC - TOPSYS */
492	MAX77693_TOPSYS_IRQ_T120C_INT,
493	MAX77693_TOPSYS_IRQ_T140C_INT,
494	MAX77693_TOPSYS_IRQ_LOWSYS_INT,
495
496	/* PMIC - Charger */
497	MAX77693_CHG_IRQ_BYP_I,
498	MAX77693_CHG_IRQ_THM_I,
499	MAX77693_CHG_IRQ_BAT_I,
500	MAX77693_CHG_IRQ_CHG_I,
501	MAX77693_CHG_IRQ_CHGIN_I,
502
503	MAX77693_IRQ_NR,
504};
505
506enum max77693_irq_muic {
507	/* MUIC INT1 */
508	MAX77693_MUIC_IRQ_INT1_ADC,
509	MAX77693_MUIC_IRQ_INT1_ADC_LOW,
510	MAX77693_MUIC_IRQ_INT1_ADC_ERR,
511	MAX77693_MUIC_IRQ_INT1_ADC1K,
512
513	/* MUIC INT2 */
514	MAX77693_MUIC_IRQ_INT2_CHGTYP,
515	MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
516	MAX77693_MUIC_IRQ_INT2_DCDTMR,
517	MAX77693_MUIC_IRQ_INT2_DXOVP,
518	MAX77693_MUIC_IRQ_INT2_VBVOLT,
519	MAX77693_MUIC_IRQ_INT2_VIDRM,
520
521	/* MUIC INT3 */
522	MAX77693_MUIC_IRQ_INT3_EOC,
523	MAX77693_MUIC_IRQ_INT3_CGMBC,
524	MAX77693_MUIC_IRQ_INT3_OVP,
525	MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
526	MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
527	MAX77693_MUIC_IRQ_INT3_BAT_DET,
528
529	MAX77693_MUIC_IRQ_NR,
530};
531
532#endif /*  __LINUX_MFD_MAX77693_PRIV_H */
533