1/*
2 *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3 *  JZ4740 Watchdog driver
4 *
5 *  This program is free software; you can redistribute it and/or modify it
6 *  under  the terms of the GNU General  Public License as published by the
7 *  Free Software Foundation;  either version 2 of the License, or (at your
8 *  option) any later version.
9 *
10 *  You should have received a copy of the GNU General Public License along
11 *  with this program; if not, write to the Free Software Foundation, Inc.,
12 *  675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/watchdog.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/device.h>
24#include <linux/clk.h>
25#include <linux/slab.h>
26#include <linux/err.h>
27#include <linux/of.h>
28
29#include <asm/mach-jz4740/timer.h>
30
31#define JZ_REG_WDT_TIMER_DATA     0x0
32#define JZ_REG_WDT_COUNTER_ENABLE 0x4
33#define JZ_REG_WDT_TIMER_COUNTER  0x8
34#define JZ_REG_WDT_TIMER_CONTROL  0xC
35
36#define JZ_WDT_CLOCK_PCLK 0x1
37#define JZ_WDT_CLOCK_RTC  0x2
38#define JZ_WDT_CLOCK_EXT  0x4
39
40#define JZ_WDT_CLOCK_DIV_SHIFT   3
41
42#define JZ_WDT_CLOCK_DIV_1    (0 << JZ_WDT_CLOCK_DIV_SHIFT)
43#define JZ_WDT_CLOCK_DIV_4    (1 << JZ_WDT_CLOCK_DIV_SHIFT)
44#define JZ_WDT_CLOCK_DIV_16   (2 << JZ_WDT_CLOCK_DIV_SHIFT)
45#define JZ_WDT_CLOCK_DIV_64   (3 << JZ_WDT_CLOCK_DIV_SHIFT)
46#define JZ_WDT_CLOCK_DIV_256  (4 << JZ_WDT_CLOCK_DIV_SHIFT)
47#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
48
49#define DEFAULT_HEARTBEAT 5
50#define MAX_HEARTBEAT     2048
51
52static bool nowayout = WATCHDOG_NOWAYOUT;
53module_param(nowayout, bool, 0);
54MODULE_PARM_DESC(nowayout,
55		 "Watchdog cannot be stopped once started (default="
56		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
57
58static unsigned int heartbeat = DEFAULT_HEARTBEAT;
59module_param(heartbeat, uint, 0);
60MODULE_PARM_DESC(heartbeat,
61		"Watchdog heartbeat period in seconds from 1 to "
62		__MODULE_STRING(MAX_HEARTBEAT) ", default "
63		__MODULE_STRING(DEFAULT_HEARTBEAT));
64
65struct jz4740_wdt_drvdata {
66	struct watchdog_device wdt;
67	void __iomem *base;
68	struct clk *rtc_clk;
69};
70
71static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
72{
73	struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
74
75	writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
76	return 0;
77}
78
79static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
80				    unsigned int new_timeout)
81{
82	struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
83	unsigned int rtc_clk_rate;
84	unsigned int timeout_value;
85	unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
86
87	rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
88
89	timeout_value = rtc_clk_rate * new_timeout;
90	while (timeout_value > 0xffff) {
91		if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
92			/* Requested timeout too high;
93			* use highest possible value. */
94			timeout_value = 0xffff;
95			break;
96		}
97		timeout_value >>= 2;
98		clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
99	}
100
101	writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
102	writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
103
104	writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
105	writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
106	writew(clock_div | JZ_WDT_CLOCK_RTC,
107		drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
108
109	writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
110
111	wdt_dev->timeout = new_timeout;
112	return 0;
113}
114
115static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
116{
117	jz4740_timer_enable_watchdog();
118	jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
119
120	return 0;
121}
122
123static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
124{
125	struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
126
127	jz4740_timer_disable_watchdog();
128	writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
129
130	return 0;
131}
132
133static const struct watchdog_info jz4740_wdt_info = {
134	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
135	.identity = "jz4740 Watchdog",
136};
137
138static const struct watchdog_ops jz4740_wdt_ops = {
139	.owner = THIS_MODULE,
140	.start = jz4740_wdt_start,
141	.stop = jz4740_wdt_stop,
142	.ping = jz4740_wdt_ping,
143	.set_timeout = jz4740_wdt_set_timeout,
144};
145
146#ifdef CONFIG_OF
147static const struct of_device_id jz4740_wdt_of_matches[] = {
148	{ .compatible = "ingenic,jz4740-watchdog", },
149	{ /* sentinel */ }
150};
151MODULE_DEVICE_TABLE(of, jz4740_wdt_of_matches)
152#endif
153
154static int jz4740_wdt_probe(struct platform_device *pdev)
155{
156	struct jz4740_wdt_drvdata *drvdata;
157	struct watchdog_device *jz4740_wdt;
158	struct resource	*res;
159	int ret;
160
161	drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
162			       GFP_KERNEL);
163	if (!drvdata) {
164		dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
165		return -ENOMEM;
166	}
167
168	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
169		heartbeat = DEFAULT_HEARTBEAT;
170
171	jz4740_wdt = &drvdata->wdt;
172	jz4740_wdt->info = &jz4740_wdt_info;
173	jz4740_wdt->ops = &jz4740_wdt_ops;
174	jz4740_wdt->timeout = heartbeat;
175	jz4740_wdt->min_timeout = 1;
176	jz4740_wdt->max_timeout = MAX_HEARTBEAT;
177	jz4740_wdt->parent = &pdev->dev;
178	watchdog_set_nowayout(jz4740_wdt, nowayout);
179	watchdog_set_drvdata(jz4740_wdt, drvdata);
180
181	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
182	drvdata->base = devm_ioremap_resource(&pdev->dev, res);
183	if (IS_ERR(drvdata->base)) {
184		ret = PTR_ERR(drvdata->base);
185		goto err_out;
186	}
187
188	drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
189	if (IS_ERR(drvdata->rtc_clk)) {
190		dev_err(&pdev->dev, "cannot find RTC clock\n");
191		ret = PTR_ERR(drvdata->rtc_clk);
192		goto err_out;
193	}
194
195	ret = watchdog_register_device(&drvdata->wdt);
196	if (ret < 0)
197		goto err_disable_clk;
198
199	platform_set_drvdata(pdev, drvdata);
200	return 0;
201
202err_disable_clk:
203	clk_put(drvdata->rtc_clk);
204err_out:
205	return ret;
206}
207
208static int jz4740_wdt_remove(struct platform_device *pdev)
209{
210	struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
211
212	jz4740_wdt_stop(&drvdata->wdt);
213	watchdog_unregister_device(&drvdata->wdt);
214	clk_put(drvdata->rtc_clk);
215
216	return 0;
217}
218
219static struct platform_driver jz4740_wdt_driver = {
220	.probe = jz4740_wdt_probe,
221	.remove = jz4740_wdt_remove,
222	.driver = {
223		.name = "jz4740-wdt",
224		.of_match_table = of_match_ptr(jz4740_wdt_of_matches),
225	},
226};
227
228module_platform_driver(jz4740_wdt_driver);
229
230MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
231MODULE_DESCRIPTION("jz4740 Watchdog Driver");
232MODULE_LICENSE("GPL");
233MODULE_ALIAS("platform:jz4740-wdt");
234