1/*
2 * Imagination Technologies PowerDown Controller Watchdog Timer.
3 *
4 * Copyright (c) 2014 Imagination Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
11 *                                                     2012 Henrik Nordstrom
12 *
13 * Notes
14 * -----
15 * The timeout value is rounded to the next power of two clock cycles.
16 * This is configured using the PDC_WDT_CONFIG register, according to this
17 * formula:
18 *
19 *     timeout = 2^(delay + 1) clock cycles
20 *
21 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
22 *
23 * Therefore, the hardware only allows to program watchdog timeouts, expressed
24 * as a power of two number of watchdog clock cycles. The current implementation
25 * guarantees that the actual watchdog timeout will be _at least_ the value
26 * programmed in the imgpdg_wdt driver.
27 *
28 * The following table shows how the user-configured timeout relates
29 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
30 *
31 * input timeout | WD_DELAY | actual timeout
32 * -----------------------------------
33 *      10       |   18     |  13 seconds
34 *      20       |   19     |  26 seconds
35 *      30       |   20     |  52 seconds
36 *      60       |   21     |  104 seconds
37 *
38 * Albeit coarse, this granularity would suffice most watchdog uses.
39 * If the platform allows it, the user should be able to change the watchdog
40 * clock rate and achieve a finer timeout granularity.
41 */
42
43#include <linux/clk.h>
44#include <linux/io.h>
45#include <linux/log2.h>
46#include <linux/module.h>
47#include <linux/platform_device.h>
48#include <linux/reboot.h>
49#include <linux/slab.h>
50#include <linux/watchdog.h>
51
52/* registers */
53#define PDC_WDT_SOFT_RESET		0x00
54#define PDC_WDT_CONFIG			0x04
55  #define PDC_WDT_CONFIG_ENABLE		BIT(31)
56  #define PDC_WDT_CONFIG_DELAY_MASK	0x1f
57
58#define PDC_WDT_TICKLE1			0x08
59#define PDC_WDT_TICKLE1_MAGIC		0xabcd1234
60#define PDC_WDT_TICKLE2			0x0c
61#define PDC_WDT_TICKLE2_MAGIC		0x4321dcba
62
63#define PDC_WDT_TICKLE_STATUS_MASK	0x7
64#define PDC_WDT_TICKLE_STATUS_SHIFT	0
65#define PDC_WDT_TICKLE_STATUS_HRESET	0x0  /* Hard reset */
66#define PDC_WDT_TICKLE_STATUS_TIMEOUT	0x1  /* Timeout */
67#define PDC_WDT_TICKLE_STATUS_TICKLE	0x2  /* Tickled incorrectly */
68#define PDC_WDT_TICKLE_STATUS_SRESET	0x3  /* Soft reset */
69#define PDC_WDT_TICKLE_STATUS_USER	0x4  /* User reset */
70
71/* Timeout values are in seconds */
72#define PDC_WDT_MIN_TIMEOUT		1
73#define PDC_WDT_DEF_TIMEOUT		64
74
75static int heartbeat;
76module_param(heartbeat, int, 0);
77MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds "
78	"(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");
79
80static bool nowayout = WATCHDOG_NOWAYOUT;
81module_param(nowayout, bool, 0);
82MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
83	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
84
85struct pdc_wdt_dev {
86	struct watchdog_device wdt_dev;
87	struct clk *wdt_clk;
88	struct clk *sys_clk;
89	void __iomem *base;
90	struct notifier_block restart_handler;
91};
92
93static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
94{
95	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
96
97	writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
98	writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
99
100	return 0;
101}
102
103static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
104{
105	unsigned int val;
106	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
107
108	val = readl(wdt->base + PDC_WDT_CONFIG);
109	val &= ~PDC_WDT_CONFIG_ENABLE;
110	writel(val, wdt->base + PDC_WDT_CONFIG);
111
112	/* Must tickle to finish the stop */
113	pdc_wdt_keepalive(wdt_dev);
114
115	return 0;
116}
117
118static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt)
119{
120	unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
121	unsigned int val;
122
123	val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
124	val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
125	writel(val, wdt->base + PDC_WDT_CONFIG);
126}
127
128static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
129			       unsigned int new_timeout)
130{
131	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
132
133	wdt->wdt_dev.timeout = new_timeout;
134
135	__pdc_wdt_set_timeout(wdt);
136
137	return 0;
138}
139
140/* Start the watchdog timer (delay should already be set) */
141static int pdc_wdt_start(struct watchdog_device *wdt_dev)
142{
143	unsigned int val;
144	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
145
146	__pdc_wdt_set_timeout(wdt);
147
148	val = readl(wdt->base + PDC_WDT_CONFIG);
149	val |= PDC_WDT_CONFIG_ENABLE;
150	writel(val, wdt->base + PDC_WDT_CONFIG);
151
152	return 0;
153}
154
155static struct watchdog_info pdc_wdt_info = {
156	.identity	= "IMG PDC Watchdog",
157	.options	= WDIOF_SETTIMEOUT |
158			  WDIOF_KEEPALIVEPING |
159			  WDIOF_MAGICCLOSE,
160};
161
162static const struct watchdog_ops pdc_wdt_ops = {
163	.owner		= THIS_MODULE,
164	.start		= pdc_wdt_start,
165	.stop		= pdc_wdt_stop,
166	.ping		= pdc_wdt_keepalive,
167	.set_timeout	= pdc_wdt_set_timeout,
168};
169
170static int pdc_wdt_restart(struct notifier_block *this, unsigned long mode,
171			   void *cmd)
172{
173	struct pdc_wdt_dev *wdt = container_of(this, struct pdc_wdt_dev,
174					       restart_handler);
175
176	/* Assert SOFT_RESET */
177	writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);
178
179	return NOTIFY_OK;
180}
181
182static int pdc_wdt_probe(struct platform_device *pdev)
183{
184	u64 div;
185	int ret, val;
186	unsigned long clk_rate;
187	struct resource *res;
188	struct pdc_wdt_dev *pdc_wdt;
189
190	pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL);
191	if (!pdc_wdt)
192		return -ENOMEM;
193
194	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195	pdc_wdt->base = devm_ioremap_resource(&pdev->dev, res);
196	if (IS_ERR(pdc_wdt->base))
197		return PTR_ERR(pdc_wdt->base);
198
199	pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys");
200	if (IS_ERR(pdc_wdt->sys_clk)) {
201		dev_err(&pdev->dev, "failed to get the sys clock\n");
202		return PTR_ERR(pdc_wdt->sys_clk);
203	}
204
205	pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt");
206	if (IS_ERR(pdc_wdt->wdt_clk)) {
207		dev_err(&pdev->dev, "failed to get the wdt clock\n");
208		return PTR_ERR(pdc_wdt->wdt_clk);
209	}
210
211	ret = clk_prepare_enable(pdc_wdt->sys_clk);
212	if (ret) {
213		dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
214		return ret;
215	}
216
217	ret = clk_prepare_enable(pdc_wdt->wdt_clk);
218	if (ret) {
219		dev_err(&pdev->dev, "could not prepare or enable wdt clock\n");
220		goto disable_sys_clk;
221	}
222
223	/* We use the clock rate to calculate the max timeout */
224	clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
225	if (clk_rate == 0) {
226		dev_err(&pdev->dev, "failed to get clock rate\n");
227		ret = -EINVAL;
228		goto disable_wdt_clk;
229	}
230
231	if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
232		dev_err(&pdev->dev, "invalid clock rate\n");
233		ret = -EINVAL;
234		goto disable_wdt_clk;
235	}
236
237	if (order_base_2(clk_rate) == 0)
238		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
239	else
240		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;
241
242	pdc_wdt->wdt_dev.info = &pdc_wdt_info;
243	pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;
244
245	div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1);
246	do_div(div, clk_rate);
247	pdc_wdt->wdt_dev.max_timeout = div;
248	pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;
249	pdc_wdt->wdt_dev.parent = &pdev->dev;
250	watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);
251
252	watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev);
253
254	pdc_wdt_stop(&pdc_wdt->wdt_dev);
255
256	/* Find what caused the last reset */
257	val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
258	val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
259	switch (val) {
260	case PDC_WDT_TICKLE_STATUS_TICKLE:
261	case PDC_WDT_TICKLE_STATUS_TIMEOUT:
262		pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;
263		dev_info(&pdev->dev,
264			 "watchdog module last reset due to timeout\n");
265		break;
266	case PDC_WDT_TICKLE_STATUS_HRESET:
267		dev_info(&pdev->dev,
268			 "watchdog module last reset due to hard reset\n");
269		break;
270	case PDC_WDT_TICKLE_STATUS_SRESET:
271		dev_info(&pdev->dev,
272			 "watchdog module last reset due to soft reset\n");
273		break;
274	case PDC_WDT_TICKLE_STATUS_USER:
275		dev_info(&pdev->dev,
276			 "watchdog module last reset due to user reset\n");
277		break;
278	default:
279		dev_info(&pdev->dev,
280			 "contains an illegal status code (%08x)\n", val);
281		break;
282	}
283
284	watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
285
286	platform_set_drvdata(pdev, pdc_wdt);
287
288	ret = watchdog_register_device(&pdc_wdt->wdt_dev);
289	if (ret)
290		goto disable_wdt_clk;
291
292	pdc_wdt->restart_handler.notifier_call = pdc_wdt_restart;
293	pdc_wdt->restart_handler.priority = 128;
294	ret = register_restart_handler(&pdc_wdt->restart_handler);
295	if (ret)
296		dev_warn(&pdev->dev, "failed to register restart handler: %d\n",
297			 ret);
298
299	return 0;
300
301disable_wdt_clk:
302	clk_disable_unprepare(pdc_wdt->wdt_clk);
303disable_sys_clk:
304	clk_disable_unprepare(pdc_wdt->sys_clk);
305	return ret;
306}
307
308static void pdc_wdt_shutdown(struct platform_device *pdev)
309{
310	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
311
312	pdc_wdt_stop(&pdc_wdt->wdt_dev);
313}
314
315static int pdc_wdt_remove(struct platform_device *pdev)
316{
317	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
318
319	unregister_restart_handler(&pdc_wdt->restart_handler);
320	pdc_wdt_stop(&pdc_wdt->wdt_dev);
321	watchdog_unregister_device(&pdc_wdt->wdt_dev);
322	clk_disable_unprepare(pdc_wdt->wdt_clk);
323	clk_disable_unprepare(pdc_wdt->sys_clk);
324
325	return 0;
326}
327
328static const struct of_device_id pdc_wdt_match[] = {
329	{ .compatible = "img,pdc-wdt" },
330	{}
331};
332MODULE_DEVICE_TABLE(of, pdc_wdt_match);
333
334static struct platform_driver pdc_wdt_driver = {
335	.driver = {
336		.name = "imgpdc-wdt",
337		.of_match_table	= pdc_wdt_match,
338	},
339	.probe = pdc_wdt_probe,
340	.remove = pdc_wdt_remove,
341	.shutdown = pdc_wdt_shutdown,
342};
343module_platform_driver(pdc_wdt_driver);
344
345MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
346MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
347MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
348MODULE_LICENSE("GPL v2");
349