1/* 2 * SiS 300/540/630[S]/730[S], 3 * SiS 315[E|PRO]/550/[M]65x/[M]661[F|M]X/740/[M]741[GX]/330/[M]76x[GX], 4 * XGI V3XT/V5/V8, Z7 5 * frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3 6 * 7 * Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the named License, 12 * or any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA 22 */ 23 24#ifndef _SIS_H_ 25#define _SIS_H_ 26 27#include <video/sisfb.h> 28 29#include "vgatypes.h" 30#include "vstruct.h" 31 32#define VER_MAJOR 1 33#define VER_MINOR 8 34#define VER_LEVEL 9 35 36#include <linux/spinlock.h> 37 38#ifdef CONFIG_COMPAT 39#define SIS_NEW_CONFIG_COMPAT 40#endif /* CONFIG_COMPAT */ 41 42#undef SISFBDEBUG 43 44#ifdef SISFBDEBUG 45#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args) 46#define TWDEBUG(x) printk(KERN_INFO x "\n"); 47#else 48#define DPRINTK(fmt, args...) 49#define TWDEBUG(x) 50#endif 51 52#define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0) 53 54/* To be included in pci_ids.h */ 55#ifndef PCI_DEVICE_ID_SI_650_VGA 56#define PCI_DEVICE_ID_SI_650_VGA 0x6325 57#endif 58#ifndef PCI_DEVICE_ID_SI_650 59#define PCI_DEVICE_ID_SI_650 0x0650 60#endif 61#ifndef PCI_DEVICE_ID_SI_651 62#define PCI_DEVICE_ID_SI_651 0x0651 63#endif 64#ifndef PCI_DEVICE_ID_SI_740 65#define PCI_DEVICE_ID_SI_740 0x0740 66#endif 67#ifndef PCI_DEVICE_ID_SI_330 68#define PCI_DEVICE_ID_SI_330 0x0330 69#endif 70#ifndef PCI_DEVICE_ID_SI_660_VGA 71#define PCI_DEVICE_ID_SI_660_VGA 0x6330 72#endif 73#ifndef PCI_DEVICE_ID_SI_661 74#define PCI_DEVICE_ID_SI_661 0x0661 75#endif 76#ifndef PCI_DEVICE_ID_SI_741 77#define PCI_DEVICE_ID_SI_741 0x0741 78#endif 79#ifndef PCI_DEVICE_ID_SI_660 80#define PCI_DEVICE_ID_SI_660 0x0660 81#endif 82#ifndef PCI_DEVICE_ID_SI_760 83#define PCI_DEVICE_ID_SI_760 0x0760 84#endif 85#ifndef PCI_DEVICE_ID_SI_761 86#define PCI_DEVICE_ID_SI_761 0x0761 87#endif 88 89#ifndef PCI_VENDOR_ID_XGI 90#define PCI_VENDOR_ID_XGI 0x18ca 91#endif 92 93#ifndef PCI_DEVICE_ID_XGI_20 94#define PCI_DEVICE_ID_XGI_20 0x0020 95#endif 96 97#ifndef PCI_DEVICE_ID_XGI_40 98#define PCI_DEVICE_ID_XGI_40 0x0040 99#endif 100 101/* To be included in fb.h */ 102#ifndef FB_ACCEL_SIS_GLAMOUR_2 103#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */ 104#endif 105#ifndef FB_ACCEL_SIS_XABRE 106#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre"), 76x */ 107#endif 108#ifndef FB_ACCEL_XGI_VOLARI_V 109#define FB_ACCEL_XGI_VOLARI_V 47 /* XGI Volari Vx (V3XT, V5, V8) */ 110#endif 111#ifndef FB_ACCEL_XGI_VOLARI_Z 112#define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI Volari Z7 */ 113#endif 114 115/* ivideo->caps */ 116#define HW_CURSOR_CAP 0x80 117#define TURBO_QUEUE_CAP 0x40 118#define AGP_CMD_QUEUE_CAP 0x20 119#define VM_CMD_QUEUE_CAP 0x10 120#define MMIO_CMD_QUEUE_CAP 0x08 121 122/* For 300 series */ 123#define TURBO_QUEUE_AREA_SIZE (512 * 1024) /* 512K */ 124#define HW_CURSOR_AREA_SIZE_300 4096 /* 4K */ 125 126/* For 315/Xabre series */ 127#define COMMAND_QUEUE_AREA_SIZE (512 * 1024) /* 512K */ 128#define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */ 129#define HW_CURSOR_AREA_SIZE_315 16384 /* 16K */ 130#define COMMAND_QUEUE_THRESHOLD 0x1F 131 132#define SIS_OH_ALLOC_SIZE 4000 133#define SENTINEL 0x7fffffff 134 135#define SEQ_ADR 0x14 136#define SEQ_DATA 0x15 137#define DAC_ADR 0x18 138#define DAC_DATA 0x19 139#define CRTC_ADR 0x24 140#define CRTC_DATA 0x25 141#define DAC2_ADR (0x16-0x30) 142#define DAC2_DATA (0x17-0x30) 143#define VB_PART1_ADR (0x04-0x30) 144#define VB_PART1_DATA (0x05-0x30) 145#define VB_PART2_ADR (0x10-0x30) 146#define VB_PART2_DATA (0x11-0x30) 147#define VB_PART3_ADR (0x12-0x30) 148#define VB_PART3_DATA (0x13-0x30) 149#define VB_PART4_ADR (0x14-0x30) 150#define VB_PART4_DATA (0x15-0x30) 151 152#define SISSR ivideo->SiS_Pr.SiS_P3c4 153#define SISCR ivideo->SiS_Pr.SiS_P3d4 154#define SISDACA ivideo->SiS_Pr.SiS_P3c8 155#define SISDACD ivideo->SiS_Pr.SiS_P3c9 156#define SISPART1 ivideo->SiS_Pr.SiS_Part1Port 157#define SISPART2 ivideo->SiS_Pr.SiS_Part2Port 158#define SISPART3 ivideo->SiS_Pr.SiS_Part3Port 159#define SISPART4 ivideo->SiS_Pr.SiS_Part4Port 160#define SISPART5 ivideo->SiS_Pr.SiS_Part5Port 161#define SISDAC2A SISPART5 162#define SISDAC2D (SISPART5 + 1) 163#define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c) 164#define SISMISCW ivideo->SiS_Pr.SiS_P3c2 165#define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a) 166#define SISPEL ivideo->SiS_Pr.SiS_P3c6 167#define SISVGAENABLE (ivideo->SiS_Pr.RelIO + 0x13) 168#define SISVID (ivideo->SiS_Pr.RelIO + 0x02 - 0x30) 169#define SISCAP (ivideo->SiS_Pr.RelIO + 0x00 - 0x30) 170 171#define IND_SIS_PASSWORD 0x05 /* SRs */ 172#define IND_SIS_COLOR_MODE 0x06 173#define IND_SIS_RAMDAC_CONTROL 0x07 174#define IND_SIS_DRAM_SIZE 0x14 175#define IND_SIS_MODULE_ENABLE 0x1E 176#define IND_SIS_PCI_ADDRESS_SET 0x20 177#define IND_SIS_TURBOQUEUE_ADR 0x26 178#define IND_SIS_TURBOQUEUE_SET 0x27 179#define IND_SIS_POWER_ON_TRAP 0x38 180#define IND_SIS_POWER_ON_TRAP2 0x39 181#define IND_SIS_CMDQUEUE_SET 0x26 182#define IND_SIS_CMDQUEUE_THRESHOLD 0x27 183 184#define IND_SIS_AGP_IO_PAD 0x48 185 186#define SIS_CRT2_WENABLE_300 0x24 /* Part1 */ 187#define SIS_CRT2_WENABLE_315 0x2F 188 189#define SIS_PASSWORD 0x86 /* SR05 */ 190 191#define SIS_INTERLACED_MODE 0x20 /* SR06 */ 192#define SIS_8BPP_COLOR_MODE 0x0 193#define SIS_15BPP_COLOR_MODE 0x1 194#define SIS_16BPP_COLOR_MODE 0x2 195#define SIS_32BPP_COLOR_MODE 0x4 196 197#define SIS_ENABLE_2D 0x40 /* SR1E */ 198 199#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */ 200#define SIS_PCI_ADDR_ENABLE 0x80 201 202#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */ 203#define SIS_VRAM_CMDQUEUE_ENABLE 0x40 204#define SIS_MMIO_CMD_ENABLE 0x20 205#define SIS_CMD_QUEUE_SIZE_512k 0x00 206#define SIS_CMD_QUEUE_SIZE_1M 0x04 207#define SIS_CMD_QUEUE_SIZE_2M 0x08 208#define SIS_CMD_QUEUE_SIZE_4M 0x0C 209#define SIS_CMD_QUEUE_RESET 0x01 210#define SIS_CMD_AUTO_CORR 0x02 211 212#define SIS_CMD_QUEUE_SIZE_Z7_64k 0x00 /* XGI Z7 */ 213#define SIS_CMD_QUEUE_SIZE_Z7_128k 0x04 214 215#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */ 216#define SIS_MODE_SELECT_CRT2 0x02 217#define SIS_VB_OUTPUT_COMPOSITE 0x04 218#define SIS_VB_OUTPUT_SVIDEO 0x08 219#define SIS_VB_OUTPUT_SCART 0x10 220#define SIS_VB_OUTPUT_LCD 0x20 221#define SIS_VB_OUTPUT_CRT2 0x40 222#define SIS_VB_OUTPUT_HIVISION 0x80 223 224#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */ 225#define SIS_DRIVER_MODE 0x40 226 227#define SIS_VB_COMPOSITE 0x01 /* CR32 */ 228#define SIS_VB_SVIDEO 0x02 229#define SIS_VB_SCART 0x04 230#define SIS_VB_LCD 0x08 231#define SIS_VB_CRT2 0x10 232#define SIS_CRT1 0x20 233#define SIS_VB_HIVISION 0x40 234#define SIS_VB_YPBPR 0x80 235#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \ 236 SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR) 237 238#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */ 239#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */ 240#define SIS_EXTERNAL_CHIP_LVDS 0x02 241#define SIS_EXTERNAL_CHIP_TRUMPION 0x03 242#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04 243#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05 244#define SIS310_EXTERNAL_CHIP_LVDS 0x02 245#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03 246 247#define SIS_AGP_2X 0x20 /* CR48 */ 248 249/* vbflags, private entries (others in sisfb.h) */ 250#define VB_CONEXANT 0x00000800 /* 661 series only */ 251#define VB_TRUMPION VB_CONEXANT /* 300 series only */ 252#define VB_302ELV 0x00004000 253#define VB_301 0x00100000 /* Video bridge type */ 254#define VB_301B 0x00200000 255#define VB_302B 0x00400000 256#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ 257#define VB_LVDS 0x01000000 258#define VB_CHRONTEL 0x02000000 259#define VB_301LV 0x04000000 260#define VB_302LV 0x08000000 261#define VB_301C 0x10000000 262 263#define VB_SISBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV) 264#define VB_VIDEOBRIDGE (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT) 265 266/* vbflags2 (static stuff only!) */ 267#define VB2_SISUMC 0x00000001 268#define VB2_301 0x00000002 /* Video bridge type */ 269#define VB2_301B 0x00000004 270#define VB2_301C 0x00000008 271#define VB2_307T 0x00000010 272#define VB2_302B 0x00000800 273#define VB2_301LV 0x00001000 274#define VB2_302LV 0x00002000 275#define VB2_302ELV 0x00004000 276#define VB2_307LV 0x00008000 277#define VB2_30xBDH 0x08000000 /* 30xB DH version (w/o LCD support) */ 278#define VB2_CONEXANT 0x10000000 279#define VB2_TRUMPION 0x20000000 280#define VB2_LVDS 0x40000000 281#define VB2_CHRONTEL 0x80000000 282 283#define VB2_SISLVDSBRIDGE (VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV) 284#define VB2_SISTMDSBRIDGE (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T) 285#define VB2_SISBRIDGE (VB2_SISLVDSBRIDGE | VB2_SISTMDSBRIDGE) 286 287#define VB2_SISTMDSLCDABRIDGE (VB2_301C | VB2_307T) 288#define VB2_SISLCDABRIDGE (VB2_SISTMDSLCDABRIDGE | VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV) 289 290#define VB2_SISHIVISIONBRIDGE (VB2_301 | VB2_301B | VB2_302B) 291#define VB2_SISYPBPRBRIDGE (VB2_301C | VB2_307T | VB2_SISLVDSBRIDGE) 292#define VB2_SISYPBPRARBRIDGE (VB2_301C | VB2_307T | VB2_307LV) 293#define VB2_SISTAP4SCALER (VB2_301C | VB2_307T | VB2_302ELV | VB2_307LV) 294#define VB2_SISTVBRIDGE (VB2_SISHIVISIONBRIDGE | VB2_SISYPBPRBRIDGE) 295 296#define VB2_SISVGA2BRIDGE (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T) 297 298#define VB2_VIDEOBRIDGE (VB2_SISBRIDGE | VB2_LVDS | VB2_CHRONTEL | VB2_CONEXANT) 299 300#define VB2_30xB (VB2_301B | VB2_301C | VB2_302B | VB2_307T) 301#define VB2_30xBLV (VB2_30xB | VB2_SISLVDSBRIDGE) 302#define VB2_30xC (VB2_301C | VB2_307T) 303#define VB2_30xCLV (VB2_301C | VB2_307T | VB2_302ELV| VB2_307LV) 304#define VB2_SISEMIBRIDGE (VB2_302LV | VB2_302ELV | VB2_307LV) 305#define VB2_LCD162MHZBRIDGE (VB2_301C | VB2_307T) 306#define VB2_LCDOVER1280BRIDGE (VB2_301C | VB2_307T | VB2_302LV | VB2_302ELV | VB2_307LV) 307#define VB2_LCDOVER1600BRIDGE (VB2_307T | VB2_307LV) 308#define VB2_RAMDAC202MHZBRIDGE (VB2_301C | VB2_307T) 309 310/* I/O port access functions */ 311 312void SiS_SetReg(SISIOADDRESS, u8, u8); 313void SiS_SetRegByte(SISIOADDRESS, u8); 314void SiS_SetRegShort(SISIOADDRESS, u16); 315void SiS_SetRegLong(SISIOADDRESS, u32); 316void SiS_SetRegANDOR(SISIOADDRESS, u8, u8, u8); 317void SiS_SetRegAND(SISIOADDRESS, u8, u8); 318void SiS_SetRegOR(SISIOADDRESS, u8, u8); 319u8 SiS_GetReg(SISIOADDRESS, u8); 320u8 SiS_GetRegByte(SISIOADDRESS); 321u16 SiS_GetRegShort(SISIOADDRESS); 322u32 SiS_GetRegLong(SISIOADDRESS); 323 324/* MMIO access macros */ 325#define MMIO_IN8(base, offset) readb((base+offset)) 326#define MMIO_IN16(base, offset) readw((base+offset)) 327#define MMIO_IN32(base, offset) readl((base+offset)) 328 329#define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset)) 330#define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset)) 331#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset)) 332 333/* Queue control MMIO registers */ 334#define Q_BASE_ADDR 0x85C0 /* Base address of software queue */ 335#define Q_WRITE_PTR 0x85C4 /* Current write pointer */ 336#define Q_READ_PTR 0x85C8 /* Current read pointer */ 337#define Q_STATUS 0x85CC /* queue status */ 338 339#define MMIO_QUEUE_PHYBASE Q_BASE_ADDR 340#define MMIO_QUEUE_WRITEPORT Q_WRITE_PTR 341#define MMIO_QUEUE_READPORT Q_READ_PTR 342 343#ifndef FB_BLANK_UNBLANK 344#define FB_BLANK_UNBLANK 0 345#endif 346#ifndef FB_BLANK_NORMAL 347#define FB_BLANK_NORMAL 1 348#endif 349#ifndef FB_BLANK_VSYNC_SUSPEND 350#define FB_BLANK_VSYNC_SUSPEND 2 351#endif 352#ifndef FB_BLANK_HSYNC_SUSPEND 353#define FB_BLANK_HSYNC_SUSPEND 3 354#endif 355#ifndef FB_BLANK_POWERDOWN 356#define FB_BLANK_POWERDOWN 4 357#endif 358 359enum _SIS_LCD_TYPE { 360 LCD_INVALID = 0, 361 LCD_800x600, 362 LCD_1024x768, 363 LCD_1280x1024, 364 LCD_1280x960, 365 LCD_640x480, 366 LCD_1600x1200, 367 LCD_1920x1440, 368 LCD_2048x1536, 369 LCD_320x240, /* FSTN */ 370 LCD_1400x1050, 371 LCD_1152x864, 372 LCD_1152x768, 373 LCD_1280x768, 374 LCD_1024x600, 375 LCD_320x240_2, /* DSTN */ 376 LCD_320x240_3, /* DSTN */ 377 LCD_848x480, 378 LCD_1280x800, 379 LCD_1680x1050, 380 LCD_1280x720, 381 LCD_1280x854, 382 LCD_CUSTOM, 383 LCD_UNKNOWN 384}; 385 386enum _SIS_CMDTYPE { 387 MMIO_CMD = 0, 388 AGP_CMD_QUEUE, 389 VM_CMD_QUEUE, 390}; 391 392struct SIS_OH { 393 struct SIS_OH *poh_next; 394 struct SIS_OH *poh_prev; 395 u32 offset; 396 u32 size; 397}; 398 399struct SIS_OHALLOC { 400 struct SIS_OHALLOC *poha_next; 401 struct SIS_OH aoh[1]; 402}; 403 404struct SIS_HEAP { 405 struct SIS_OH oh_free; 406 struct SIS_OH oh_used; 407 struct SIS_OH *poh_freelist; 408 struct SIS_OHALLOC *poha_chain; 409 u32 max_freesize; 410 struct sis_video_info *vinfo; 411}; 412 413/* Our "par" */ 414struct sis_video_info { 415 int cardnumber; 416 struct fb_info *memyselfandi; 417 418 struct SiS_Private SiS_Pr; 419 420 struct sisfb_info sisfbinfo; /* For ioctl SISFB_GET_INFO */ 421 422 struct fb_var_screeninfo default_var; 423 424 struct fb_fix_screeninfo sisfb_fix; 425 u32 pseudo_palette[16]; 426 427 struct sisfb_monitor { 428 u16 hmin; 429 u16 hmax; 430 u16 vmin; 431 u16 vmax; 432 u32 dclockmax; 433 u8 feature; 434 bool datavalid; 435 } sisfb_thismonitor; 436 437 unsigned short chip_id; /* PCI ID of chip */ 438 unsigned short chip_vendor; /* PCI ID of vendor */ 439 char myid[40]; 440 441 struct pci_dev *nbridge; 442 struct pci_dev *lpcdev; 443 444 int mni; /* Mode number index */ 445 446 unsigned long video_size; 447 unsigned long video_base; 448 unsigned long mmio_size; 449 unsigned long mmio_base; 450 unsigned long vga_base; 451 452 unsigned long video_offset; 453 454 unsigned long UMAsize, LFBsize; 455 456 void __iomem *video_vbase; 457 void __iomem *mmio_vbase; 458 459 unsigned char *bios_abase; 460 461 int wc_cookie; 462 463 u32 sisfb_mem; 464 465 u32 sisfb_parm_mem; 466 int sisfb_accel; 467 int sisfb_ypan; 468 int sisfb_max; 469 int sisfb_userom; 470 int sisfb_useoem; 471 int sisfb_mode_idx; 472 int sisfb_parm_rate; 473 int sisfb_crt1off; 474 int sisfb_forcecrt1; 475 int sisfb_crt2type; 476 int sisfb_crt2flags; 477 int sisfb_dstn; 478 int sisfb_fstn; 479 int sisfb_tvplug; 480 int sisfb_tvstd; 481 int sisfb_nocrt2rate; 482 483 u32 heapstart; /* offset */ 484 void __iomem *sisfb_heap_start; /* address */ 485 void __iomem *sisfb_heap_end; /* address */ 486 u32 sisfb_heap_size; 487 int havenoheap; 488 489 struct SIS_HEAP sisfb_heap; /* This card's vram heap */ 490 491 int video_bpp; 492 int video_cmap_len; 493 int video_width; 494 int video_height; 495 unsigned int refresh_rate; 496 497 unsigned int chip; 498 unsigned int chip_real_id; 499 u8 revision_id; 500 int sisvga_enabled; /* PCI device was enabled */ 501 502 int video_linelength; /* real pitch */ 503 int scrnpitchCRT1; /* pitch regarding interlace */ 504 505 u16 DstColor; /* For 2d acceleration */ 506 u32 SiS310_AccelDepth; 507 u32 CommandReg; 508 int cmdqueuelength; /* Current (for accel) */ 509 u32 cmdQueueSize; /* Total size in KB */ 510 511 spinlock_t lockaccel; /* Do not use outside of kernel! */ 512 513 unsigned int pcibus; 514 unsigned int pcislot; 515 unsigned int pcifunc; 516 517 int accel; 518 int engineok; 519 520 u16 subsysvendor; 521 u16 subsysdevice; 522 523 u32 vbflags; /* Replacing deprecated stuff from above */ 524 u32 currentvbflags; 525 u32 vbflags2; 526 527 int lcdxres, lcdyres; 528 int lcddefmodeidx, tvdefmodeidx, defmodeidx; 529 u32 CRT2LCDType; /* defined in "SIS_LCD_TYPE" */ 530 u32 curFSTN, curDSTN; 531 532 int current_bpp; 533 int current_width; 534 int current_height; 535 int current_htotal; 536 int current_vtotal; 537 int current_linelength; 538 __u32 current_pixclock; 539 int current_refresh_rate; 540 541 unsigned int current_base; 542 543 u8 mode_no; 544 u8 rate_idx; 545 int modechanged; 546 unsigned char modeprechange; 547 548 u8 sisfb_lastrates[128]; 549 550 int newrom; 551 int haveXGIROM; 552 int registered; 553 int warncount; 554 555 int sisvga_engine; 556 int hwcursor_size; 557 int CRT2_write_enable; 558 u8 caps; 559 560 u8 detectedpdc; 561 u8 detectedpdca; 562 u8 detectedlcda; 563 564 void __iomem *hwcursor_vbase; 565 566 int chronteltype; 567 int tvxpos, tvypos; 568 u8 p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02; 569 int tvx, tvy; 570 571 u8 sisfblocked; 572 573 struct sisfb_info sisfb_infoblock; 574 575 struct sisfb_cmd sisfb_command; 576 577 u32 sisfb_id; 578 579 u8 sisfb_can_post; 580 u8 sisfb_card_posted; 581 u8 sisfb_was_boot_device; 582 583 struct sis_video_info *next; 584}; 585 586#endif 587