1#ifndef __RIVAFB_H 2#define __RIVAFB_H 3 4#include <linux/fb.h> 5#include <video/vga.h> 6#include <linux/i2c.h> 7#include <linux/i2c-algo-bit.h> 8 9#include "riva_hw.h" 10 11/* GGI compatibility macros */ 12#define NUM_SEQ_REGS 0x05 13#define NUM_CRT_REGS 0x41 14#define NUM_GRC_REGS 0x09 15#define NUM_ATC_REGS 0x15 16 17/* I2C */ 18#define DDC_SCL_READ_MASK (1 << 2) 19#define DDC_SCL_WRITE_MASK (1 << 5) 20#define DDC_SDA_READ_MASK (1 << 3) 21#define DDC_SDA_WRITE_MASK (1 << 4) 22 23/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. 24 * From KGI originally. */ 25struct riva_regs { 26 u8 attr[NUM_ATC_REGS]; 27 u8 crtc[NUM_CRT_REGS]; 28 u8 gra[NUM_GRC_REGS]; 29 u8 seq[NUM_SEQ_REGS]; 30 u8 misc_output; 31 RIVA_HW_STATE ext; 32}; 33 34struct riva_par; 35 36struct riva_i2c_chan { 37 struct riva_par *par; 38 unsigned long ddc_base; 39 struct i2c_adapter adapter; 40 struct i2c_algo_bit_data algo; 41}; 42 43struct riva_par { 44 RIVA_HW_INST riva; /* interface to riva_hw.c */ 45 u32 pseudo_palette[16]; /* default palette */ 46 u32 palette[16]; /* for Riva128 */ 47 u8 __iomem *ctrl_base; /* virtual control register base addr */ 48 unsigned dclk_max; /* max DCLK */ 49 50 struct riva_regs initial_state; /* initial startup video mode */ 51 struct riva_regs current_state; 52#ifdef CONFIG_X86 53 struct vgastate state; 54#endif 55 struct mutex open_lock; 56 unsigned int ref_count; 57 unsigned char *EDID; 58 unsigned int Chipset; 59 int forceCRTC; 60 Bool SecondCRTC; 61 int FlatPanel; 62 struct pci_dev *pdev; 63 int cursor_reset; 64 int wc_cookie; 65 struct riva_i2c_chan chan[3]; 66}; 67 68void riva_common_setup(struct riva_par *); 69unsigned long riva_get_memlen(struct riva_par *); 70unsigned long riva_get_maxdclk(struct riva_par *); 71void riva_delete_i2c_busses(struct riva_par *par); 72void riva_create_i2c_busses(struct riva_par *par); 73int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); 74 75#endif /* __RIVAFB_H */ 76