1/* 2 * Copyright (C) 2009 3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 4 * 5 * Description: 6 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c 7 * driver to function correctly on these systems. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14#include <linux/clk.h> 15#include <linux/delay.h> 16#include <linux/err.h> 17#include <linux/fsl_devices.h> 18#include <linux/platform_device.h> 19#include <linux/io.h> 20 21#include "fsl_usb2_udc.h" 22 23static struct clk *mxc_ahb_clk; 24static struct clk *mxc_per_clk; 25static struct clk *mxc_ipg_clk; 26 27/* workaround ENGcm09152 for i.MX35 */ 28#define MX35_USBPHYCTRL_OFFSET 0x600 29#define USBPHYCTRL_OTGBASE_OFFSET 0x8 30#define USBPHYCTRL_EVDO (1 << 23) 31 32int fsl_udc_clk_init(struct platform_device *pdev) 33{ 34 struct fsl_usb2_platform_data *pdata; 35 unsigned long freq; 36 int ret; 37 38 pdata = dev_get_platdata(&pdev->dev); 39 40 mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 41 if (IS_ERR(mxc_ipg_clk)) { 42 dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n"); 43 return PTR_ERR(mxc_ipg_clk); 44 } 45 46 mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb"); 47 if (IS_ERR(mxc_ahb_clk)) { 48 dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n"); 49 return PTR_ERR(mxc_ahb_clk); 50 } 51 52 mxc_per_clk = devm_clk_get(&pdev->dev, "per"); 53 if (IS_ERR(mxc_per_clk)) { 54 dev_err(&pdev->dev, "clk_get(\"per\") failed\n"); 55 return PTR_ERR(mxc_per_clk); 56 } 57 58 clk_prepare_enable(mxc_ipg_clk); 59 clk_prepare_enable(mxc_ahb_clk); 60 clk_prepare_enable(mxc_per_clk); 61 62 /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ 63 if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) { 64 freq = clk_get_rate(mxc_per_clk); 65 if (pdata->phy_mode != FSL_USB2_PHY_ULPI && 66 (freq < 59999000 || freq > 60001000)) { 67 dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); 68 ret = -EINVAL; 69 goto eclkrate; 70 } 71 } 72 73 return 0; 74 75eclkrate: 76 clk_disable_unprepare(mxc_ipg_clk); 77 clk_disable_unprepare(mxc_ahb_clk); 78 clk_disable_unprepare(mxc_per_clk); 79 mxc_per_clk = NULL; 80 return ret; 81} 82 83int fsl_udc_clk_finalize(struct platform_device *pdev) 84{ 85 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 86 int ret = 0; 87 88 /* workaround ENGcm09152 for i.MX35 */ 89 if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) { 90 unsigned int v; 91 struct resource *res = platform_get_resource 92 (pdev, IORESOURCE_MEM, 0); 93 void __iomem *phy_regs = ioremap(res->start + 94 MX35_USBPHYCTRL_OFFSET, 512); 95 if (!phy_regs) { 96 dev_err(&pdev->dev, "ioremap for phy address fails\n"); 97 ret = -EINVAL; 98 goto ioremap_err; 99 } 100 101 v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET); 102 writel(v | USBPHYCTRL_EVDO, 103 phy_regs + USBPHYCTRL_OTGBASE_OFFSET); 104 105 iounmap(phy_regs); 106 } 107 108 109ioremap_err: 110 /* ULPI transceivers don't need usbpll */ 111 if (pdata->phy_mode == FSL_USB2_PHY_ULPI) { 112 clk_disable_unprepare(mxc_per_clk); 113 mxc_per_clk = NULL; 114 } 115 116 return ret; 117} 118 119void fsl_udc_clk_release(void) 120{ 121 if (mxc_per_clk) 122 clk_disable_unprepare(mxc_per_clk); 123 clk_disable_unprepare(mxc_ahb_clk); 124 clk_disable_unprepare(mxc_ipg_clk); 125} 126