1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved. 7 */ 8 9 10/* 11 * This file contains a module version of the ioc4 serial driver. This 12 * includes all the support functions needed (support functions, etc.) 13 * and the serial driver itself. 14 */ 15#include <linux/errno.h> 16#include <linux/tty.h> 17#include <linux/tty_flip.h> 18#include <linux/serial.h> 19#include <linux/circ_buf.h> 20#include <linux/serial_reg.h> 21#include <linux/module.h> 22#include <linux/pci.h> 23#include <linux/ioc4.h> 24#include <linux/serial_core.h> 25#include <linux/slab.h> 26 27/* 28 * interesting things about the ioc4 29 */ 30 31#define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */ 32#define IOC4_NUM_CARDS 8 /* max cards per partition */ 33 34#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \ 35 (_n == 1) ? (IOC4_SIO_IR_S1) : \ 36 (_n == 2) ? (IOC4_SIO_IR_S2) : \ 37 (IOC4_SIO_IR_S3) 38 39#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \ 40 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \ 41 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \ 42 (IOC4_OTHER_IR_S3_MEMERR) 43 44 45/* 46 * All IOC4 registers are 32 bits wide. 47 */ 48 49/* 50 * PCI Memory Space Map 51 */ 52#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */ 53#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0) 54#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1) 55#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1) 56#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1) 57#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5) 58#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6) 59 60/* Interrupt types */ 61#define IOC4_SIO_INTR_TYPE 0 62#define IOC4_OTHER_INTR_TYPE 1 63#define IOC4_NUM_INTR_TYPES 2 64 65/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */ 66#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */ 67#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */ 68#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */ 69#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */ 70#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */ 71#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */ 72#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */ 73#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */ 74#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */ 75#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */ 76#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */ 77#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */ 78#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */ 79#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */ 80#define IOC4_SIO_IR_S1_INT 0x00004000 /* */ 81#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */ 82#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */ 83#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */ 84#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */ 85#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */ 86#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */ 87#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */ 88#define IOC4_SIO_IR_S2_INT 0x00400000 /* */ 89#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */ 90#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */ 91#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */ 92#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */ 93#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */ 94#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */ 95#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */ 96#define IOC4_SIO_IR_S3_INT 0x40000000 /* */ 97#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */ 98 99/* Per device interrupt masks */ 100#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \ 101 IOC4_SIO_IR_S0_RX_FULL | \ 102 IOC4_SIO_IR_S0_RX_HIGH | \ 103 IOC4_SIO_IR_S0_RX_TIMER | \ 104 IOC4_SIO_IR_S0_DELTA_DCD | \ 105 IOC4_SIO_IR_S0_DELTA_CTS | \ 106 IOC4_SIO_IR_S0_INT | \ 107 IOC4_SIO_IR_S0_TX_EXPLICIT) 108#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \ 109 IOC4_SIO_IR_S1_RX_FULL | \ 110 IOC4_SIO_IR_S1_RX_HIGH | \ 111 IOC4_SIO_IR_S1_RX_TIMER | \ 112 IOC4_SIO_IR_S1_DELTA_DCD | \ 113 IOC4_SIO_IR_S1_DELTA_CTS | \ 114 IOC4_SIO_IR_S1_INT | \ 115 IOC4_SIO_IR_S1_TX_EXPLICIT) 116#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \ 117 IOC4_SIO_IR_S2_RX_FULL | \ 118 IOC4_SIO_IR_S2_RX_HIGH | \ 119 IOC4_SIO_IR_S2_RX_TIMER | \ 120 IOC4_SIO_IR_S2_DELTA_DCD | \ 121 IOC4_SIO_IR_S2_DELTA_CTS | \ 122 IOC4_SIO_IR_S2_INT | \ 123 IOC4_SIO_IR_S2_TX_EXPLICIT) 124#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \ 125 IOC4_SIO_IR_S3_RX_FULL | \ 126 IOC4_SIO_IR_S3_RX_HIGH | \ 127 IOC4_SIO_IR_S3_RX_TIMER | \ 128 IOC4_SIO_IR_S3_DELTA_DCD | \ 129 IOC4_SIO_IR_S3_DELTA_CTS | \ 130 IOC4_SIO_IR_S3_INT | \ 131 IOC4_SIO_IR_S3_TX_EXPLICIT) 132 133/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */ 134#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */ 135#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */ 136#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */ 137#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */ 138#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */ 139#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */ 140#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */ 141#define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */ 142#define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */ 143#define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */ 144 145#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \ 146 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR) 147 148/* Bitmasks for IOC4_SIO_CR */ 149#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */ 150#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000 151#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010 152#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020 153#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030 154#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040 155#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050 156#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060 157#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070 158#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among 159 serial ports (ro) */ 160/* Defs for some of the generic I/O pins */ 161#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0 162 mode sel */ 163#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1 164 mode sel */ 165#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2 166 mode sel */ 167#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3 168 mode sel */ 169 170#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling 171 uart 0 mode select */ 172#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling 173 uart 1 mode select */ 174#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling 175 uart 2 mode select */ 176#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling 177 uart 3 mode select */ 178 179/* Bitmasks for serial RX status byte */ 180#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */ 181#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */ 182#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */ 183#define IOC4_RXSB_BREAK 0x08 /* Break character */ 184#define IOC4_RXSB_CTS 0x10 /* State of CTS */ 185#define IOC4_RXSB_DCD 0x20 /* State of DCD */ 186#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */ 187#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR 188 * & BREAK valid */ 189 190/* Bitmasks for serial TX control byte */ 191#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */ 192#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */ 193#define IOC4_TXCB_VALID 0x40 /* Byte is valid */ 194#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */ 195#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */ 196 197/* Bitmasks for IOC4_SBBR_L */ 198#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ 199 200/* Bitmasks for IOC4_SSCR_<3:0> */ 201#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */ 202#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ 203#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */ 204#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */ 205#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */ 206#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */ 207#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */ 208#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */ 209#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */ 210#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */ 211#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */ 212 213/* All producer/comsumer pointers are the same bitfield */ 214#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */ 215#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */ 216#define IOC4_PROD_CONS_PTR_OFF 3 217 218/* Bitmasks for IOC4_SRCIR_<3:0> */ 219#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */ 220 221/* Bitmasks for IOC4_SHADOW_<3:0> */ 222#define IOC4_SHADOW_DR 0x00000001 /* Data ready */ 223#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */ 224#define IOC4_SHADOW_PE 0x00000004 /* Parity error */ 225#define IOC4_SHADOW_FE 0x00000008 /* Framing error */ 226#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */ 227#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */ 228#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */ 229#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */ 230#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */ 231#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */ 232#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */ 233#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */ 234#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */ 235#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */ 236#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ 237#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ 238#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */ 239 240/* Bitmasks for IOC4_SRTR_<3:0> */ 241#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */ 242#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */ 243#define IOC4_SRTR_CNT_VAL_SHIFT 16 244#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */ 245 246/* Serial port register map used for DMA and PIO serial I/O */ 247struct ioc4_serialregs { 248 uint32_t sscr; 249 uint32_t stpir; 250 uint32_t stcir; 251 uint32_t srpir; 252 uint32_t srcir; 253 uint32_t srtr; 254 uint32_t shadow; 255}; 256 257/* IOC4 UART register map */ 258struct ioc4_uartregs { 259 char i4u_lcr; 260 union { 261 char iir; /* read only */ 262 char fcr; /* write only */ 263 } u3; 264 union { 265 char ier; /* DLAB == 0 */ 266 char dlm; /* DLAB == 1 */ 267 } u2; 268 union { 269 char rbr; /* read only, DLAB == 0 */ 270 char thr; /* write only, DLAB == 0 */ 271 char dll; /* DLAB == 1 */ 272 } u1; 273 char i4u_scr; 274 char i4u_msr; 275 char i4u_lsr; 276 char i4u_mcr; 277}; 278 279/* short names */ 280#define i4u_dll u1.dll 281#define i4u_ier u2.ier 282#define i4u_dlm u2.dlm 283#define i4u_fcr u3.fcr 284 285/* Serial port registers used for DMA serial I/O */ 286struct ioc4_serial { 287 uint32_t sbbr01_l; 288 uint32_t sbbr01_h; 289 uint32_t sbbr23_l; 290 uint32_t sbbr23_h; 291 292 struct ioc4_serialregs port_0; 293 struct ioc4_serialregs port_1; 294 struct ioc4_serialregs port_2; 295 struct ioc4_serialregs port_3; 296 struct ioc4_uartregs uart_0; 297 struct ioc4_uartregs uart_1; 298 struct ioc4_uartregs uart_2; 299 struct ioc4_uartregs uart_3; 300}; 301 302/* UART clock speed */ 303#define IOC4_SER_XIN_CLK_66 66666667 304#define IOC4_SER_XIN_CLK_33 33333333 305 306#define IOC4_W_IES 0 307#define IOC4_W_IEC 1 308 309typedef void ioc4_intr_func_f(void *, uint32_t); 310typedef ioc4_intr_func_f *ioc4_intr_func_t; 311 312static unsigned int Num_of_ioc4_cards; 313 314/* defining this will get you LOTS of great debug info */ 315//#define DEBUG_INTERRUPTS 316#define DPRINT_CONFIG(_x...) ; 317//#define DPRINT_CONFIG(_x...) printk _x 318 319/* number of characters left in xmit buffer before we ask for more */ 320#define WAKEUP_CHARS 256 321 322/* number of characters we want to transmit to the lower level at a time */ 323#define IOC4_MAX_CHARS 256 324#define IOC4_FIFO_CHARS 255 325 326/* Device name we're using */ 327#define DEVICE_NAME_RS232 "ttyIOC" 328#define DEVICE_NAME_RS422 "ttyAIOC" 329#define DEVICE_MAJOR 204 330#define DEVICE_MINOR_RS232 50 331#define DEVICE_MINOR_RS422 84 332 333 334/* register offsets */ 335#define IOC4_SERIAL_OFFSET 0x300 336 337/* flags for next_char_state */ 338#define NCS_BREAK 0x1 339#define NCS_PARITY 0x2 340#define NCS_FRAMING 0x4 341#define NCS_OVERRUN 0x8 342 343/* cause we need SOME parameters ... */ 344#define MIN_BAUD_SUPPORTED 1200 345#define MAX_BAUD_SUPPORTED 115200 346 347/* protocol types supported */ 348#define PROTO_RS232 3 349#define PROTO_RS422 7 350 351/* Notification types */ 352#define N_DATA_READY 0x01 353#define N_OUTPUT_LOWAT 0x02 354#define N_BREAK 0x04 355#define N_PARITY_ERROR 0x08 356#define N_FRAMING_ERROR 0x10 357#define N_OVERRUN_ERROR 0x20 358#define N_DDCD 0x40 359#define N_DCTS 0x80 360 361#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \ 362 N_PARITY_ERROR | N_FRAMING_ERROR | \ 363 N_OVERRUN_ERROR | N_DDCD | N_DCTS) 364 365#define N_ALL_OUTPUT N_OUTPUT_LOWAT 366 367#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR) 368 369#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \ 370 N_PARITY_ERROR | N_FRAMING_ERROR | \ 371 N_OVERRUN_ERROR | N_DDCD | N_DCTS) 372 373#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16)) 374#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div)) 375 376/* Some masks */ 377#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \ 378 | UART_LCR_WLEN7 | UART_LCR_WLEN8) 379#define LCR_MASK_STOP_BITS (UART_LCR_STOP) 380 381#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb) 382#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw) 383 384/* Default to 4k buffers */ 385#ifdef IOC4_1K_BUFFERS 386#define RING_BUF_SIZE 1024 387#define IOC4_BUF_SIZE_BIT 0 388#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K 389#else 390#define RING_BUF_SIZE 4096 391#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE 392#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K 393#endif 394 395#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4) 396 397/* 398 * This is the entry saved by the driver - one per card 399 */ 400 401#define UART_PORT_MIN 0 402#define UART_PORT_RS232 UART_PORT_MIN 403#define UART_PORT_RS422 1 404#define UART_PORT_COUNT 2 /* one for each mode */ 405 406struct ioc4_control { 407 int ic_irq; 408 struct { 409 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */ 410 struct uart_port icp_uart_port[UART_PORT_COUNT]; 411 /* Handy reference material */ 412 struct ioc4_port *icp_port; 413 } ic_port[IOC4_NUM_SERIAL_PORTS]; 414 struct ioc4_soft *ic_soft; 415}; 416 417/* 418 * per-IOC4 data structure 419 */ 420#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t)) 421struct ioc4_soft { 422 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr; 423 struct ioc4_serial __iomem *is_ioc4_serial_addr; 424 425 /* Each interrupt type has an entry in the array */ 426 struct ioc4_intr_type { 427 428 /* 429 * Each in-use entry in this array contains at least 430 * one nonzero bit in sd_bits; no two entries in this 431 * array have overlapping sd_bits values. 432 */ 433 struct ioc4_intr_info { 434 uint32_t sd_bits; 435 ioc4_intr_func_f *sd_intr; 436 void *sd_info; 437 } is_intr_info[MAX_IOC4_INTR_ENTS]; 438 439 /* Number of entries active in the above array */ 440 atomic_t is_num_intrs; 441 } is_intr_type[IOC4_NUM_INTR_TYPES]; 442 443 /* is_ir_lock must be held while 444 * modifying sio_ie values, so 445 * we can be sure that sio_ie is 446 * not changing when we read it 447 * along with sio_ir. 448 */ 449 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */ 450}; 451 452/* Local port info for each IOC4 serial ports */ 453struct ioc4_port { 454 struct uart_port *ip_port; /* current active port ptr */ 455 /* Ptrs for all ports */ 456 struct uart_port *ip_all_ports[UART_PORT_COUNT]; 457 /* Back ptrs for this port */ 458 struct ioc4_control *ip_control; 459 struct pci_dev *ip_pdev; 460 struct ioc4_soft *ip_ioc4_soft; 461 462 /* pci mem addresses */ 463 struct ioc4_misc_regs __iomem *ip_mem; 464 struct ioc4_serial __iomem *ip_serial; 465 struct ioc4_serialregs __iomem *ip_serial_regs; 466 struct ioc4_uartregs __iomem *ip_uart_regs; 467 468 /* Ring buffer page for this port */ 469 dma_addr_t ip_dma_ringbuf; 470 /* vaddr of ring buffer */ 471 struct ring_buffer *ip_cpu_ringbuf; 472 473 /* Rings for this port */ 474 struct ring *ip_inring; 475 struct ring *ip_outring; 476 477 /* Hook to port specific values */ 478 struct hooks *ip_hooks; 479 480 spinlock_t ip_lock; 481 482 /* Various rx/tx parameters */ 483 int ip_baud; 484 int ip_tx_lowat; 485 int ip_rx_timeout; 486 487 /* Copy of notification bits */ 488 int ip_notify; 489 490 /* Shadow copies of various registers so we don't need to PIO 491 * read them constantly 492 */ 493 uint32_t ip_ienb; /* Enabled interrupts */ 494 uint32_t ip_sscr; 495 uint32_t ip_tx_prod; 496 uint32_t ip_rx_cons; 497 int ip_pci_bus_speed; 498 unsigned char ip_flags; 499}; 500 501/* tx low water mark. We need to notify the driver whenever tx is getting 502 * close to empty so it can refill the tx buffer and keep things going. 503 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll 504 * have no trouble getting in more chars in time (I certainly hope so). 505 */ 506#define TX_LOWAT_LATENCY 1000 507#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY) 508#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ) 509 510/* Flags per port */ 511#define INPUT_HIGH 0x01 512#define DCD_ON 0x02 513#define LOWAT_WRITTEN 0x04 514#define READ_ABORTED 0x08 515#define PORT_ACTIVE 0x10 516#define PORT_INACTIVE 0 /* This is the value when "off" */ 517 518 519/* Since each port has different register offsets and bitmasks 520 * for everything, we'll store those that we need in tables so we 521 * don't have to be constantly checking the port we are dealing with. 522 */ 523struct hooks { 524 uint32_t intr_delta_dcd; 525 uint32_t intr_delta_cts; 526 uint32_t intr_tx_mt; 527 uint32_t intr_rx_timer; 528 uint32_t intr_rx_high; 529 uint32_t intr_tx_explicit; 530 uint32_t intr_dma_error; 531 uint32_t intr_clear; 532 uint32_t intr_all; 533 int rs422_select_pin; 534}; 535 536static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = { 537 /* Values for port 0 */ 538 { 539 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS, 540 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER, 541 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT, 542 IOC4_OTHER_IR_S0_MEMERR, 543 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL | 544 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER | 545 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS | 546 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT), 547 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN, 548 }, 549 550 /* Values for port 1 */ 551 { 552 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS, 553 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER, 554 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT, 555 IOC4_OTHER_IR_S1_MEMERR, 556 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL | 557 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER | 558 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS | 559 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT), 560 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN, 561 }, 562 563 /* Values for port 2 */ 564 { 565 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS, 566 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER, 567 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT, 568 IOC4_OTHER_IR_S2_MEMERR, 569 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL | 570 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER | 571 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS | 572 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT), 573 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN, 574 }, 575 576 /* Values for port 3 */ 577 { 578 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS, 579 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER, 580 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT, 581 IOC4_OTHER_IR_S3_MEMERR, 582 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL | 583 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER | 584 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS | 585 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT), 586 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN, 587 } 588}; 589 590/* A ring buffer entry */ 591struct ring_entry { 592 union { 593 struct { 594 uint32_t alldata; 595 uint32_t allsc; 596 } all; 597 struct { 598 char data[4]; /* data bytes */ 599 char sc[4]; /* status/control */ 600 } s; 601 } u; 602}; 603 604/* Test the valid bits in any of the 4 sc chars using "allsc" member */ 605#define RING_ANY_VALID \ 606 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101) 607 608#define ring_sc u.s.sc 609#define ring_data u.s.data 610#define ring_allsc u.all.allsc 611 612/* Number of entries per ring buffer. */ 613#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry)) 614 615/* An individual ring */ 616struct ring { 617 struct ring_entry entries[ENTRIES_PER_RING]; 618}; 619 620/* The whole enchilada */ 621struct ring_buffer { 622 struct ring TX_0_OR_2; 623 struct ring RX_0_OR_2; 624 struct ring TX_1_OR_3; 625 struct ring RX_1_OR_3; 626}; 627 628/* Get a ring from a port struct */ 629#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh) 630 631/* Infinite loop detection. 632 */ 633#define MAXITER 10000000 634 635/* Prototypes */ 636static void receive_chars(struct uart_port *); 637static void handle_intr(void *arg, uint32_t sio_ir); 638 639/* 640 * port_is_active - determines if this port is currently active 641 * @port: ptr to soft struct for this port 642 * @uart_port: uart port to test for 643 */ 644static inline int port_is_active(struct ioc4_port *port, 645 struct uart_port *uart_port) 646{ 647 if (port) { 648 if ((port->ip_flags & PORT_ACTIVE) 649 && (port->ip_port == uart_port)) 650 return 1; 651 } 652 return 0; 653} 654 655 656/** 657 * write_ireg - write the interrupt regs 658 * @ioc4_soft: ptr to soft struct for this port 659 * @val: value to write 660 * @which: which register 661 * @type: which ireg set 662 */ 663static inline void 664write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type) 665{ 666 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr; 667 unsigned long flags; 668 669 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags); 670 671 switch (type) { 672 case IOC4_SIO_INTR_TYPE: 673 switch (which) { 674 case IOC4_W_IES: 675 writel(val, &mem->sio_ies.raw); 676 break; 677 678 case IOC4_W_IEC: 679 writel(val, &mem->sio_iec.raw); 680 break; 681 } 682 break; 683 684 case IOC4_OTHER_INTR_TYPE: 685 switch (which) { 686 case IOC4_W_IES: 687 writel(val, &mem->other_ies.raw); 688 break; 689 690 case IOC4_W_IEC: 691 writel(val, &mem->other_iec.raw); 692 break; 693 } 694 break; 695 696 default: 697 break; 698 } 699 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags); 700} 701 702/** 703 * set_baud - Baud rate setting code 704 * @port: port to set 705 * @baud: baud rate to use 706 */ 707static int set_baud(struct ioc4_port *port, int baud) 708{ 709 int actual_baud; 710 int diff; 711 int lcr; 712 unsigned short divisor; 713 struct ioc4_uartregs __iomem *uart; 714 715 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed); 716 if (!divisor) 717 return 1; 718 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed); 719 720 diff = actual_baud - baud; 721 if (diff < 0) 722 diff = -diff; 723 724 /* If we're within 1%, we've found a match */ 725 if (diff * 100 > actual_baud) 726 return 1; 727 728 uart = port->ip_uart_regs; 729 lcr = readb(&uart->i4u_lcr); 730 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr); 731 writeb((unsigned char)divisor, &uart->i4u_dll); 732 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm); 733 writeb(lcr, &uart->i4u_lcr); 734 return 0; 735} 736 737 738/** 739 * get_ioc4_port - given a uart port, return the control structure 740 * @port: uart port 741 * @set: set this port as current 742 */ 743static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set) 744{ 745 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev); 746 struct ioc4_control *control = idd->idd_serial_data; 747 struct ioc4_port *port; 748 int port_num, port_type; 749 750 if (control) { 751 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; 752 port_num++ ) { 753 port = control->ic_port[port_num].icp_port; 754 if (!port) 755 continue; 756 for (port_type = UART_PORT_MIN; 757 port_type < UART_PORT_COUNT; 758 port_type++) { 759 if (the_port == port->ip_all_ports 760 [port_type]) { 761 /* set local copy */ 762 if (set) { 763 port->ip_port = the_port; 764 } 765 return port; 766 } 767 } 768 } 769 } 770 return NULL; 771} 772 773/* The IOC4 hardware provides no atomic way to determine if interrupts 774 * are pending since two reads are required to do so. The handler must 775 * read the SIO_IR and the SIO_IES, and take the logical and of the 776 * two. When this value is zero, all interrupts have been serviced and 777 * the handler may return. 778 * 779 * This has the unfortunate "hole" that, if some other CPU or 780 * some other thread or some higher level interrupt manages to 781 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may 782 * think we have observed SIO_IR&SIO_IE==0 when in fact this 783 * condition never really occurred. 784 * 785 * To solve this, we use a simple spinlock that must be held 786 * whenever modifying SIO_IE; holding this lock while observing 787 * both SIO_IR and SIO_IE guarantees that we do not falsely 788 * conclude that no enabled interrupts are pending. 789 */ 790 791static inline uint32_t 792pending_intrs(struct ioc4_soft *soft, int type) 793{ 794 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr; 795 unsigned long flag; 796 uint32_t intrs = 0; 797 798 BUG_ON(!((type == IOC4_SIO_INTR_TYPE) 799 || (type == IOC4_OTHER_INTR_TYPE))); 800 801 spin_lock_irqsave(&soft->is_ir_lock, flag); 802 803 switch (type) { 804 case IOC4_SIO_INTR_TYPE: 805 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw); 806 break; 807 808 case IOC4_OTHER_INTR_TYPE: 809 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw); 810 811 /* Don't process any ATA interrupte */ 812 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR); 813 break; 814 815 default: 816 break; 817 } 818 spin_unlock_irqrestore(&soft->is_ir_lock, flag); 819 return intrs; 820} 821 822/** 823 * port_init - Initialize the sio and ioc4 hardware for a given port 824 * called per port from attach... 825 * @port: port to initialize 826 */ 827static int inline port_init(struct ioc4_port *port) 828{ 829 uint32_t sio_cr; 830 struct hooks *hooks = port->ip_hooks; 831 struct ioc4_uartregs __iomem *uart; 832 833 /* Idle the IOC4 serial interface */ 834 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr); 835 836 /* Wait until any pending bus activity for this port has ceased */ 837 do 838 sio_cr = readl(&port->ip_mem->sio_cr.raw); 839 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE)); 840 841 /* Finish reset sequence */ 842 writel(0, &port->ip_serial_regs->sscr); 843 844 /* Once RESET is done, reload cached tx_prod and rx_cons values 845 * and set rings to empty by making prod == cons 846 */ 847 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK; 848 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir); 849 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK; 850 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir); 851 852 /* Disable interrupts for this 16550 */ 853 uart = port->ip_uart_regs; 854 writeb(0, &uart->i4u_lcr); 855 writeb(0, &uart->i4u_ier); 856 857 /* Set the default baud */ 858 set_baud(port, port->ip_baud); 859 860 /* Set line control to 8 bits no parity */ 861 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr); 862 /* UART_LCR_STOP == 1 stop */ 863 864 /* Enable the FIFOs */ 865 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr); 866 /* then reset 16550 FIFOs */ 867 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 868 &uart->i4u_fcr); 869 870 /* Clear modem control register */ 871 writeb(0, &uart->i4u_mcr); 872 873 /* Clear deltas in modem status register */ 874 readb(&uart->i4u_msr); 875 876 /* Only do this once per port pair */ 877 if (port->ip_hooks == &hooks_array[0] 878 || port->ip_hooks == &hooks_array[2]) { 879 unsigned long ring_pci_addr; 880 uint32_t __iomem *sbbr_l; 881 uint32_t __iomem *sbbr_h; 882 883 if (port->ip_hooks == &hooks_array[0]) { 884 sbbr_l = &port->ip_serial->sbbr01_l; 885 sbbr_h = &port->ip_serial->sbbr01_h; 886 } else { 887 sbbr_l = &port->ip_serial->sbbr23_l; 888 sbbr_h = &port->ip_serial->sbbr23_h; 889 } 890 891 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf; 892 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n", 893 __func__, ring_pci_addr)); 894 895 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h); 896 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l); 897 } 898 899 /* Set the receive timeout value to 10 msec */ 900 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr); 901 902 /* Set rx threshold, enable DMA */ 903 /* Set high water mark at 3/4 of full ring */ 904 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4); 905 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 906 907 /* Disable and clear all serial related interrupt bits */ 908 write_ireg(port->ip_ioc4_soft, hooks->intr_clear, 909 IOC4_W_IEC, IOC4_SIO_INTR_TYPE); 910 port->ip_ienb &= ~hooks->intr_clear; 911 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw); 912 return 0; 913} 914 915/** 916 * handle_dma_error_intr - service any pending DMA error interrupts for the 917 * given port - 2nd level called via sd_intr 918 * @arg: handler arg 919 * @other_ir: ioc4regs 920 */ 921static void handle_dma_error_intr(void *arg, uint32_t other_ir) 922{ 923 struct ioc4_port *port = (struct ioc4_port *)arg; 924 struct hooks *hooks = port->ip_hooks; 925 unsigned long flags; 926 927 spin_lock_irqsave(&port->ip_lock, flags); 928 929 /* ACK the interrupt */ 930 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw); 931 932 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) { 933 printk(KERN_ERR 934 "PCI error address is 0x%llx, " 935 "master is serial port %c %s\n", 936 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h) 937 << 32) 938 | readl(&port->ip_mem->pci_err_addr_l.raw)) 939 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' + 940 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) & 941 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1), 942 (readl(&port->ip_mem->pci_err_addr_l.raw) 943 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK) 944 ? "RX" : "TX"); 945 946 if (readl(&port->ip_mem->pci_err_addr_l.raw) 947 & IOC4_PCI_ERR_ADDR_MUL_ERR) { 948 printk(KERN_ERR 949 "Multiple errors occurred\n"); 950 } 951 } 952 spin_unlock_irqrestore(&port->ip_lock, flags); 953 954 /* Re-enable DMA error interrupts */ 955 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES, 956 IOC4_OTHER_INTR_TYPE); 957} 958 959/** 960 * intr_connect - interrupt connect function 961 * @soft: soft struct for this card 962 * @type: interrupt type 963 * @intrbits: bit pattern to set 964 * @intr: handler function 965 * @info: handler arg 966 */ 967static void 968intr_connect(struct ioc4_soft *soft, int type, 969 uint32_t intrbits, ioc4_intr_func_f * intr, void *info) 970{ 971 int i; 972 struct ioc4_intr_info *intr_ptr; 973 974 BUG_ON(!((type == IOC4_SIO_INTR_TYPE) 975 || (type == IOC4_OTHER_INTR_TYPE))); 976 977 i = atomic_inc_return(&soft-> is_intr_type[type].is_num_intrs) - 1; 978 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0))); 979 980 /* Save off the lower level interrupt handler */ 981 intr_ptr = &soft->is_intr_type[type].is_intr_info[i]; 982 intr_ptr->sd_bits = intrbits; 983 intr_ptr->sd_intr = intr; 984 intr_ptr->sd_info = info; 985} 986 987/** 988 * ioc4_intr - Top level IOC4 interrupt handler. 989 * @irq: irq value 990 * @arg: handler arg 991 */ 992 993static irqreturn_t ioc4_intr(int irq, void *arg) 994{ 995 struct ioc4_soft *soft; 996 uint32_t this_ir, this_mir; 997 int xx, num_intrs = 0; 998 int intr_type; 999 int handled = 0; 1000 struct ioc4_intr_info *intr_info; 1001 1002 soft = arg; 1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) { 1004 num_intrs = (int)atomic_read( 1005 &soft->is_intr_type[intr_type].is_num_intrs); 1006 1007 this_mir = this_ir = pending_intrs(soft, intr_type); 1008 1009 /* Farm out the interrupt to the various drivers depending on 1010 * which interrupt bits are set. 1011 */ 1012 for (xx = 0; xx < num_intrs; xx++) { 1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx]; 1014 this_mir = this_ir & intr_info->sd_bits; 1015 if (this_mir) { 1016 /* Disable owned interrupts, call handler */ 1017 handled++; 1018 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC, 1019 intr_type); 1020 intr_info->sd_intr(intr_info->sd_info, this_mir); 1021 this_ir &= ~this_mir; 1022 } 1023 } 1024 } 1025#ifdef DEBUG_INTERRUPTS 1026 { 1027 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr; 1028 unsigned long flag; 1029 1030 spin_lock_irqsave(&soft->is_ir_lock, flag); 1031 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x " 1032 "other_ir 0x%x other_ies 0x%x mask 0x%x\n", 1033 __func__, __LINE__, 1034 (void *)mem, readl(&mem->sio_ir.raw), 1035 readl(&mem->sio_ies.raw), 1036 readl(&mem->other_ir.raw), 1037 readl(&mem->other_ies.raw), 1038 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR); 1039 spin_unlock_irqrestore(&soft->is_ir_lock, flag); 1040 } 1041#endif 1042 return handled ? IRQ_HANDLED : IRQ_NONE; 1043} 1044 1045/** 1046 * ioc4_attach_local - Device initialization. 1047 * Called at *_attach() time for each 1048 * IOC4 with serial ports in the system. 1049 * @idd: Master module data for this IOC4 1050 */ 1051static int inline ioc4_attach_local(struct ioc4_driver_data *idd) 1052{ 1053 struct ioc4_port *port; 1054 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS]; 1055 int port_number; 1056 uint16_t ioc4_revid_min = 62; 1057 uint16_t ioc4_revid; 1058 struct pci_dev *pdev = idd->idd_pdev; 1059 struct ioc4_control* control = idd->idd_serial_data; 1060 struct ioc4_soft *soft = control->ic_soft; 1061 void __iomem *ioc4_misc = idd->idd_misc_regs; 1062 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr; 1063 1064 /* IOC4 firmware must be at least rev 62 */ 1065 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid); 1066 1067 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid); 1068 if (ioc4_revid < ioc4_revid_min) { 1069 printk(KERN_WARNING 1070 "IOC4 serial not supported on firmware rev %d, " 1071 "please upgrade to rev %d or higher\n", 1072 ioc4_revid, ioc4_revid_min); 1073 return -EPERM; 1074 } 1075 BUG_ON(ioc4_misc == NULL); 1076 BUG_ON(ioc4_serial == NULL); 1077 1078 /* Create port structures for each port */ 1079 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS; 1080 port_number++) { 1081 port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL); 1082 if (!port) { 1083 printk(KERN_WARNING 1084 "IOC4 serial memory not available for port\n"); 1085 return -ENOMEM; 1086 } 1087 spin_lock_init(&port->ip_lock); 1088 1089 /* we need to remember the previous ones, to point back to 1090 * them farther down - setting up the ring buffers. 1091 */ 1092 ports[port_number] = port; 1093 1094 /* Allocate buffers and jumpstart the hardware. */ 1095 control->ic_port[port_number].icp_port = port; 1096 port->ip_ioc4_soft = soft; 1097 port->ip_pdev = pdev; 1098 port->ip_ienb = 0; 1099 /* Use baud rate calculations based on detected PCI 1100 * bus speed. Simply test whether the PCI clock is 1101 * running closer to 66MHz or 33MHz. 1102 */ 1103 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) { 1104 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66; 1105 } else { 1106 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33; 1107 } 1108 port->ip_baud = 9600; 1109 port->ip_control = control; 1110 port->ip_mem = ioc4_misc; 1111 port->ip_serial = ioc4_serial; 1112 1113 /* point to the right hook */ 1114 port->ip_hooks = &hooks_array[port_number]; 1115 1116 /* Get direct hooks to the serial regs and uart regs 1117 * for this port 1118 */ 1119 switch (port_number) { 1120 case 0: 1121 port->ip_serial_regs = &(port->ip_serial->port_0); 1122 port->ip_uart_regs = &(port->ip_serial->uart_0); 1123 break; 1124 case 1: 1125 port->ip_serial_regs = &(port->ip_serial->port_1); 1126 port->ip_uart_regs = &(port->ip_serial->uart_1); 1127 break; 1128 case 2: 1129 port->ip_serial_regs = &(port->ip_serial->port_2); 1130 port->ip_uart_regs = &(port->ip_serial->uart_2); 1131 break; 1132 default: 1133 case 3: 1134 port->ip_serial_regs = &(port->ip_serial->port_3); 1135 port->ip_uart_regs = &(port->ip_serial->uart_3); 1136 break; 1137 } 1138 1139 /* ring buffers are 1 to a pair of ports */ 1140 if (port_number && (port_number & 1)) { 1141 /* odd use the evens buffer */ 1142 port->ip_dma_ringbuf = 1143 ports[port_number - 1]->ip_dma_ringbuf; 1144 port->ip_cpu_ringbuf = 1145 ports[port_number - 1]->ip_cpu_ringbuf; 1146 port->ip_inring = RING(port, RX_1_OR_3); 1147 port->ip_outring = RING(port, TX_1_OR_3); 1148 1149 } else { 1150 if (port->ip_dma_ringbuf == 0) { 1151 port->ip_cpu_ringbuf = pci_alloc_consistent 1152 (pdev, TOTAL_RING_BUF_SIZE, 1153 &port->ip_dma_ringbuf); 1154 1155 } 1156 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) & 1157 (TOTAL_RING_BUF_SIZE - 1)) == 0)); 1158 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p " 1159 "ip_dma_ringbuf 0x%p\n", 1160 __func__, 1161 (void *)port->ip_cpu_ringbuf, 1162 (void *)port->ip_dma_ringbuf)); 1163 port->ip_inring = RING(port, RX_0_OR_2); 1164 port->ip_outring = RING(port, TX_0_OR_2); 1165 } 1166 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p", 1167 __func__, 1168 port_number, (void *)port, (void *)control)); 1169 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n", 1170 (void *)port->ip_serial_regs, 1171 (void *)port->ip_uart_regs)); 1172 1173 /* Initialize the hardware for IOC4 */ 1174 port_init(port); 1175 1176 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p " 1177 "outring 0x%p\n", 1178 __func__, 1179 port_number, (void *)port, 1180 (void *)port->ip_inring, 1181 (void *)port->ip_outring)); 1182 1183 /* Attach interrupt handlers */ 1184 intr_connect(soft, IOC4_SIO_INTR_TYPE, 1185 GET_SIO_IR(port_number), 1186 handle_intr, port); 1187 1188 intr_connect(soft, IOC4_OTHER_INTR_TYPE, 1189 GET_OTHER_IR(port_number), 1190 handle_dma_error_intr, port); 1191 } 1192 return 0; 1193} 1194 1195/** 1196 * enable_intrs - enable interrupts 1197 * @port: port to enable 1198 * @mask: mask to use 1199 */ 1200static void enable_intrs(struct ioc4_port *port, uint32_t mask) 1201{ 1202 struct hooks *hooks = port->ip_hooks; 1203 1204 if ((port->ip_ienb & mask) != mask) { 1205 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES, 1206 IOC4_SIO_INTR_TYPE); 1207 port->ip_ienb |= mask; 1208 } 1209 1210 if (port->ip_ienb) 1211 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, 1212 IOC4_W_IES, IOC4_OTHER_INTR_TYPE); 1213} 1214 1215/** 1216 * local_open - local open a port 1217 * @port: port to open 1218 */ 1219static inline int local_open(struct ioc4_port *port) 1220{ 1221 int spiniter = 0; 1222 1223 port->ip_flags = PORT_ACTIVE; 1224 1225 /* Pause the DMA interface if necessary */ 1226 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1227 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE, 1228 &port->ip_serial_regs->sscr); 1229 while((readl(&port->ip_serial_regs-> sscr) 1230 & IOC4_SSCR_PAUSE_STATE) == 0) { 1231 spiniter++; 1232 if (spiniter > MAXITER) { 1233 port->ip_flags = PORT_INACTIVE; 1234 return -1; 1235 } 1236 } 1237 } 1238 1239 /* Reset the input fifo. If the uart received chars while the port 1240 * was closed and DMA is not enabled, the uart may have a bunch of 1241 * chars hanging around in its rx fifo which will not be discarded 1242 * by rclr in the upper layer. We must get rid of them here. 1243 */ 1244 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR, 1245 &port->ip_uart_regs->i4u_fcr); 1246 1247 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr); 1248 /* UART_LCR_STOP == 1 stop */ 1249 1250 /* Re-enable DMA, set default threshold to intr whenever there is 1251 * data available. 1252 */ 1253 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD; 1254 port->ip_sscr |= 1; /* default threshold */ 1255 1256 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE 1257 * flag if it was set above 1258 */ 1259 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1260 port->ip_tx_lowat = 1; 1261 return 0; 1262} 1263 1264/** 1265 * set_rx_timeout - Set rx timeout and threshold values. 1266 * @port: port to use 1267 * @timeout: timeout value in ticks 1268 */ 1269static inline int set_rx_timeout(struct ioc4_port *port, int timeout) 1270{ 1271 int threshold; 1272 1273 port->ip_rx_timeout = timeout; 1274 1275 /* Timeout is in ticks. Let's figure out how many chars we 1276 * can receive at the current baud rate in that interval 1277 * and set the rx threshold to that amount. There are 4 chars 1278 * per ring entry, so we'll divide the number of chars that will 1279 * arrive in timeout by 4. 1280 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100. 1281 */ 1282 threshold = timeout * port->ip_baud / 4000; 1283 if (threshold == 0) 1284 threshold = 1; /* otherwise we'll intr all the time! */ 1285 1286 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD) 1287 return 1; 1288 1289 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD; 1290 port->ip_sscr |= threshold; 1291 1292 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1293 1294 /* Now set the rx timeout to the given value 1295 * again timeout * IOC4_SRTR_HZ / HZ 1296 */ 1297 timeout = timeout * IOC4_SRTR_HZ / 100; 1298 if (timeout > IOC4_SRTR_CNT) 1299 timeout = IOC4_SRTR_CNT; 1300 1301 writel(timeout, &port->ip_serial_regs->srtr); 1302 return 0; 1303} 1304 1305/** 1306 * config_port - config the hardware 1307 * @port: port to config 1308 * @baud: baud rate for the port 1309 * @byte_size: data size 1310 * @stop_bits: number of stop bits 1311 * @parenb: parity enable ? 1312 * @parodd: odd parity ? 1313 */ 1314static inline int 1315config_port(struct ioc4_port *port, 1316 int baud, int byte_size, int stop_bits, int parenb, int parodd) 1317{ 1318 char lcr, sizebits; 1319 int spiniter = 0; 1320 1321 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n", 1322 __func__, baud, byte_size, stop_bits, parenb, parodd)); 1323 1324 if (set_baud(port, baud)) 1325 return 1; 1326 1327 switch (byte_size) { 1328 case 5: 1329 sizebits = UART_LCR_WLEN5; 1330 break; 1331 case 6: 1332 sizebits = UART_LCR_WLEN6; 1333 break; 1334 case 7: 1335 sizebits = UART_LCR_WLEN7; 1336 break; 1337 case 8: 1338 sizebits = UART_LCR_WLEN8; 1339 break; 1340 default: 1341 return 1; 1342 } 1343 1344 /* Pause the DMA interface if necessary */ 1345 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1346 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE, 1347 &port->ip_serial_regs->sscr); 1348 while((readl(&port->ip_serial_regs->sscr) 1349 & IOC4_SSCR_PAUSE_STATE) == 0) { 1350 spiniter++; 1351 if (spiniter > MAXITER) 1352 return -1; 1353 } 1354 } 1355 1356 /* Clear relevant fields in lcr */ 1357 lcr = readb(&port->ip_uart_regs->i4u_lcr); 1358 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR | 1359 UART_LCR_PARITY | LCR_MASK_STOP_BITS); 1360 1361 /* Set byte size in lcr */ 1362 lcr |= sizebits; 1363 1364 /* Set parity */ 1365 if (parenb) { 1366 lcr |= UART_LCR_PARITY; 1367 if (!parodd) 1368 lcr |= UART_LCR_EPAR; 1369 } 1370 1371 /* Set stop bits */ 1372 if (stop_bits) 1373 lcr |= UART_LCR_STOP /* 2 stop bits */ ; 1374 1375 writeb(lcr, &port->ip_uart_regs->i4u_lcr); 1376 1377 /* Re-enable the DMA interface if necessary */ 1378 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1379 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1380 } 1381 port->ip_baud = baud; 1382 1383 /* When we get within this number of ring entries of filling the 1384 * entire ring on tx, place an EXPLICIT intr to generate a lowat 1385 * notification when output has drained. 1386 */ 1387 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4; 1388 if (port->ip_tx_lowat == 0) 1389 port->ip_tx_lowat = 1; 1390 1391 set_rx_timeout(port, 2); 1392 1393 return 0; 1394} 1395 1396/** 1397 * do_write - Write bytes to the port. Returns the number of bytes 1398 * actually written. Called from transmit_chars 1399 * @port: port to use 1400 * @buf: the stuff to write 1401 * @len: how many bytes in 'buf' 1402 */ 1403static inline int do_write(struct ioc4_port *port, char *buf, int len) 1404{ 1405 int prod_ptr, cons_ptr, total = 0; 1406 struct ring *outring; 1407 struct ring_entry *entry; 1408 struct hooks *hooks = port->ip_hooks; 1409 1410 BUG_ON(!(len >= 0)); 1411 1412 prod_ptr = port->ip_tx_prod; 1413 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK; 1414 outring = port->ip_outring; 1415 1416 /* Maintain a 1-entry red-zone. The ring buffer is full when 1417 * (cons - prod) % ring_size is 1. Rather than do this subtraction 1418 * in the body of the loop, I'll do it now. 1419 */ 1420 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK; 1421 1422 /* Stuff the bytes into the output */ 1423 while ((prod_ptr != cons_ptr) && (len > 0)) { 1424 int xx; 1425 1426 /* Get 4 bytes (one ring entry) at a time */ 1427 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr); 1428 1429 /* Invalidate all entries */ 1430 entry->ring_allsc = 0; 1431 1432 /* Copy in some bytes */ 1433 for (xx = 0; (xx < 4) && (len > 0); xx++) { 1434 entry->ring_data[xx] = *buf++; 1435 entry->ring_sc[xx] = IOC4_TXCB_VALID; 1436 len--; 1437 total++; 1438 } 1439 1440 /* If we are within some small threshold of filling up the 1441 * entire ring buffer, we must place an EXPLICIT intr here 1442 * to generate a lowat interrupt in case we subsequently 1443 * really do fill up the ring and the caller goes to sleep. 1444 * No need to place more than one though. 1445 */ 1446 if (!(port->ip_flags & LOWAT_WRITTEN) && 1447 ((cons_ptr - prod_ptr) & PROD_CONS_MASK) 1448 <= port->ip_tx_lowat 1449 * (int)sizeof(struct ring_entry)) { 1450 port->ip_flags |= LOWAT_WRITTEN; 1451 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE; 1452 } 1453 1454 /* Go on to next entry */ 1455 prod_ptr += sizeof(struct ring_entry); 1456 prod_ptr &= PROD_CONS_MASK; 1457 } 1458 1459 /* If we sent something, start DMA if necessary */ 1460 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) { 1461 port->ip_sscr |= IOC4_SSCR_DMA_EN; 1462 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1463 } 1464 1465 /* Store the new producer pointer. If tx is disabled, we stuff the 1466 * data into the ring buffer, but we don't actually start tx. 1467 */ 1468 if (!uart_tx_stopped(port->ip_port)) { 1469 writel(prod_ptr, &port->ip_serial_regs->stpir); 1470 1471 /* If we are now transmitting, enable tx_mt interrupt so we 1472 * can disable DMA if necessary when the tx finishes. 1473 */ 1474 if (total > 0) 1475 enable_intrs(port, hooks->intr_tx_mt); 1476 } 1477 port->ip_tx_prod = prod_ptr; 1478 return total; 1479} 1480 1481/** 1482 * disable_intrs - disable interrupts 1483 * @port: port to enable 1484 * @mask: mask to use 1485 */ 1486static void disable_intrs(struct ioc4_port *port, uint32_t mask) 1487{ 1488 struct hooks *hooks = port->ip_hooks; 1489 1490 if (port->ip_ienb & mask) { 1491 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC, 1492 IOC4_SIO_INTR_TYPE); 1493 port->ip_ienb &= ~mask; 1494 } 1495 1496 if (!port->ip_ienb) 1497 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, 1498 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE); 1499} 1500 1501/** 1502 * set_notification - Modify event notification 1503 * @port: port to use 1504 * @mask: events mask 1505 * @set_on: set ? 1506 */ 1507static int set_notification(struct ioc4_port *port, int mask, int set_on) 1508{ 1509 struct hooks *hooks = port->ip_hooks; 1510 uint32_t intrbits, sscrbits; 1511 1512 BUG_ON(!mask); 1513 1514 intrbits = sscrbits = 0; 1515 1516 if (mask & N_DATA_READY) 1517 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high); 1518 if (mask & N_OUTPUT_LOWAT) 1519 intrbits |= hooks->intr_tx_explicit; 1520 if (mask & N_DDCD) { 1521 intrbits |= hooks->intr_delta_dcd; 1522 sscrbits |= IOC4_SSCR_RX_RING_DCD; 1523 } 1524 if (mask & N_DCTS) 1525 intrbits |= hooks->intr_delta_cts; 1526 1527 if (set_on) { 1528 enable_intrs(port, intrbits); 1529 port->ip_notify |= mask; 1530 port->ip_sscr |= sscrbits; 1531 } else { 1532 disable_intrs(port, intrbits); 1533 port->ip_notify &= ~mask; 1534 port->ip_sscr &= ~sscrbits; 1535 } 1536 1537 /* We require DMA if either DATA_READY or DDCD notification is 1538 * currently requested. If neither of these is requested and 1539 * there is currently no tx in progress, DMA may be disabled. 1540 */ 1541 if (port->ip_notify & (N_DATA_READY | N_DDCD)) 1542 port->ip_sscr |= IOC4_SSCR_DMA_EN; 1543 else if (!(port->ip_ienb & hooks->intr_tx_mt)) 1544 port->ip_sscr &= ~IOC4_SSCR_DMA_EN; 1545 1546 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1547 return 0; 1548} 1549 1550/** 1551 * set_mcr - set the master control reg 1552 * @the_port: port to use 1553 * @mask1: mcr mask 1554 * @mask2: shadow mask 1555 */ 1556static inline int set_mcr(struct uart_port *the_port, 1557 int mask1, int mask2) 1558{ 1559 struct ioc4_port *port = get_ioc4_port(the_port, 0); 1560 uint32_t shadow; 1561 int spiniter = 0; 1562 char mcr; 1563 1564 if (!port) 1565 return -1; 1566 1567 /* Pause the DMA interface if necessary */ 1568 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1569 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE, 1570 &port->ip_serial_regs->sscr); 1571 while ((readl(&port->ip_serial_regs->sscr) 1572 & IOC4_SSCR_PAUSE_STATE) == 0) { 1573 spiniter++; 1574 if (spiniter > MAXITER) 1575 return -1; 1576 } 1577 } 1578 shadow = readl(&port->ip_serial_regs->shadow); 1579 mcr = (shadow & 0xff000000) >> 24; 1580 1581 /* Set new value */ 1582 mcr |= mask1; 1583 shadow |= mask2; 1584 1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr); 1586 writel(shadow, &port->ip_serial_regs->shadow); 1587 1588 /* Re-enable the DMA interface if necessary */ 1589 if (port->ip_sscr & IOC4_SSCR_DMA_EN) { 1590 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1591 } 1592 return 0; 1593} 1594 1595/** 1596 * ioc4_set_proto - set the protocol for the port 1597 * @port: port to use 1598 * @proto: protocol to use 1599 */ 1600static int ioc4_set_proto(struct ioc4_port *port, int proto) 1601{ 1602 struct hooks *hooks = port->ip_hooks; 1603 1604 switch (proto) { 1605 case PROTO_RS232: 1606 /* Clear the appropriate GIO pin */ 1607 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw)); 1608 break; 1609 1610 case PROTO_RS422: 1611 /* Set the appropriate GIO pin */ 1612 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw)); 1613 break; 1614 1615 default: 1616 return 1; 1617 } 1618 return 0; 1619} 1620 1621/** 1622 * transmit_chars - upper level write, called with ip_lock 1623 * @the_port: port to write 1624 */ 1625static void transmit_chars(struct uart_port *the_port) 1626{ 1627 int xmit_count, tail, head; 1628 int result; 1629 char *start; 1630 struct tty_struct *tty; 1631 struct ioc4_port *port = get_ioc4_port(the_port, 0); 1632 struct uart_state *state; 1633 1634 if (!the_port) 1635 return; 1636 if (!port) 1637 return; 1638 1639 state = the_port->state; 1640 tty = state->port.tty; 1641 1642 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) { 1643 /* Nothing to do or hw stopped */ 1644 set_notification(port, N_ALL_OUTPUT, 0); 1645 return; 1646 } 1647 1648 head = state->xmit.head; 1649 tail = state->xmit.tail; 1650 start = (char *)&state->xmit.buf[tail]; 1651 1652 /* write out all the data or until the end of the buffer */ 1653 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail); 1654 if (xmit_count > 0) { 1655 result = do_write(port, start, xmit_count); 1656 if (result > 0) { 1657 /* booking */ 1658 xmit_count -= result; 1659 the_port->icount.tx += result; 1660 /* advance the pointers */ 1661 tail += result; 1662 tail &= UART_XMIT_SIZE - 1; 1663 state->xmit.tail = tail; 1664 start = (char *)&state->xmit.buf[tail]; 1665 } 1666 } 1667 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS) 1668 uart_write_wakeup(the_port); 1669 1670 if (uart_circ_empty(&state->xmit)) { 1671 set_notification(port, N_OUTPUT_LOWAT, 0); 1672 } else { 1673 set_notification(port, N_OUTPUT_LOWAT, 1); 1674 } 1675} 1676 1677/** 1678 * ioc4_change_speed - change the speed of the port 1679 * @the_port: port to change 1680 * @new_termios: new termios settings 1681 * @old_termios: old termios settings 1682 */ 1683static void 1684ioc4_change_speed(struct uart_port *the_port, 1685 struct ktermios *new_termios, struct ktermios *old_termios) 1686{ 1687 struct ioc4_port *port = get_ioc4_port(the_port, 0); 1688 int baud, bits; 1689 unsigned cflag, iflag; 1690 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8; 1691 struct uart_state *state = the_port->state; 1692 1693 cflag = new_termios->c_cflag; 1694 iflag = new_termios->c_iflag; 1695 1696 switch (cflag & CSIZE) { 1697 case CS5: 1698 new_data = 5; 1699 bits = 7; 1700 break; 1701 case CS6: 1702 new_data = 6; 1703 bits = 8; 1704 break; 1705 case CS7: 1706 new_data = 7; 1707 bits = 9; 1708 break; 1709 case CS8: 1710 new_data = 8; 1711 bits = 10; 1712 break; 1713 default: 1714 /* cuz we always need a default ... */ 1715 new_data = 5; 1716 bits = 7; 1717 break; 1718 } 1719 if (cflag & CSTOPB) { 1720 bits++; 1721 new_stop = 1; 1722 } 1723 if (cflag & PARENB) { 1724 bits++; 1725 new_parity_enable = 1; 1726 if (cflag & PARODD) 1727 new_parity = 1; 1728 } 1729 baud = uart_get_baud_rate(the_port, new_termios, old_termios, 1730 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED); 1731 DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud)); 1732 1733 /* default is 9600 */ 1734 if (!baud) 1735 baud = 9600; 1736 1737 if (!the_port->fifosize) 1738 the_port->fifosize = IOC4_FIFO_CHARS; 1739 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10)); 1740 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */ 1741 1742 the_port->ignore_status_mask = N_ALL_INPUT; 1743 1744 state->port.low_latency = 1; 1745 1746 if (iflag & IGNPAR) 1747 the_port->ignore_status_mask &= ~(N_PARITY_ERROR 1748 | N_FRAMING_ERROR); 1749 if (iflag & IGNBRK) { 1750 the_port->ignore_status_mask &= ~N_BREAK; 1751 if (iflag & IGNPAR) 1752 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR; 1753 } 1754 if (!(cflag & CREAD)) { 1755 /* ignore everything */ 1756 the_port->ignore_status_mask &= ~N_DATA_READY; 1757 } 1758 1759 if (cflag & CRTSCTS) { 1760 port->ip_sscr |= IOC4_SSCR_HFC_EN; 1761 } 1762 else { 1763 port->ip_sscr &= ~IOC4_SSCR_HFC_EN; 1764 } 1765 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 1766 1767 /* Set the configuration and proper notification call */ 1768 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o " 1769 "config_port(baud %d data %d stop %d p enable %d parity %d)," 1770 " notification 0x%x\n", 1771 __func__, (void *)port, cflag, baud, new_data, new_stop, 1772 new_parity_enable, new_parity, the_port->ignore_status_mask)); 1773 1774 if ((config_port(port, baud, /* baud */ 1775 new_data, /* byte size */ 1776 new_stop, /* stop bits */ 1777 new_parity_enable, /* set parity */ 1778 new_parity)) >= 0) { /* parity 1==odd */ 1779 set_notification(port, the_port->ignore_status_mask, 1); 1780 } 1781} 1782 1783/** 1784 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors 1785 * @the_port: Port to operate on 1786 */ 1787static inline int ic4_startup_local(struct uart_port *the_port) 1788{ 1789 struct ioc4_port *port; 1790 struct uart_state *state; 1791 1792 if (!the_port) 1793 return -1; 1794 1795 port = get_ioc4_port(the_port, 0); 1796 if (!port) 1797 return -1; 1798 1799 state = the_port->state; 1800 1801 local_open(port); 1802 1803 /* set the protocol - mapbase has the port type */ 1804 ioc4_set_proto(port, the_port->mapbase); 1805 1806 /* set the speed of the serial port */ 1807 ioc4_change_speed(the_port, &state->port.tty->termios, 1808 (struct ktermios *)0); 1809 1810 return 0; 1811} 1812 1813/* 1814 * ioc4_cb_output_lowat - called when the output low water mark is hit 1815 * @the_port: port to output 1816 */ 1817static void ioc4_cb_output_lowat(struct uart_port *the_port) 1818{ 1819 unsigned long pflags; 1820 1821 /* ip_lock is set on the call here */ 1822 if (the_port) { 1823 spin_lock_irqsave(&the_port->lock, pflags); 1824 transmit_chars(the_port); 1825 spin_unlock_irqrestore(&the_port->lock, pflags); 1826 } 1827} 1828 1829/** 1830 * handle_intr - service any interrupts for the given port - 2nd level 1831 * called via sd_intr 1832 * @arg: handler arg 1833 * @sio_ir: ioc4regs 1834 */ 1835static void handle_intr(void *arg, uint32_t sio_ir) 1836{ 1837 struct ioc4_port *port = (struct ioc4_port *)arg; 1838 struct hooks *hooks = port->ip_hooks; 1839 unsigned int rx_high_rd_aborted = 0; 1840 unsigned long flags; 1841 struct uart_port *the_port; 1842 int loop_counter; 1843 1844 /* Possible race condition here: The tx_mt interrupt bit may be 1845 * cleared without the intervention of the interrupt handler, 1846 * e.g. by a write. If the top level interrupt handler reads a 1847 * tx_mt, then some other processor does a write, starting up 1848 * output, then we come in here, see the tx_mt and stop DMA, the 1849 * output started by the other processor will hang. Thus we can 1850 * only rely on tx_mt being legitimate if it is read while the 1851 * port lock is held. Therefore this bit must be ignored in the 1852 * passed in interrupt mask which was read by the top level 1853 * interrupt handler since the port lock was not held at the time 1854 * it was read. We can only rely on this bit being accurate if it 1855 * is read while the port lock is held. So we'll clear it for now, 1856 * and reload it later once we have the port lock. 1857 */ 1858 sio_ir &= ~(hooks->intr_tx_mt); 1859 1860 spin_lock_irqsave(&port->ip_lock, flags); 1861 1862 loop_counter = MAXITER; /* to avoid hangs */ 1863 1864 do { 1865 uint32_t shadow; 1866 1867 if ( loop_counter-- <= 0 ) { 1868 printk(KERN_WARNING "IOC4 serial: " 1869 "possible hang condition/" 1870 "port stuck on interrupt.\n"); 1871 break; 1872 } 1873 1874 /* Handle a DCD change */ 1875 if (sio_ir & hooks->intr_delta_dcd) { 1876 /* ACK the interrupt */ 1877 writel(hooks->intr_delta_dcd, 1878 &port->ip_mem->sio_ir.raw); 1879 1880 shadow = readl(&port->ip_serial_regs->shadow); 1881 1882 if ((port->ip_notify & N_DDCD) 1883 && (shadow & IOC4_SHADOW_DCD) 1884 && (port->ip_port)) { 1885 the_port = port->ip_port; 1886 the_port->icount.dcd = 1; 1887 wake_up_interruptible 1888 (&the_port->state->port.delta_msr_wait); 1889 } else if ((port->ip_notify & N_DDCD) 1890 && !(shadow & IOC4_SHADOW_DCD)) { 1891 /* Flag delta DCD/no DCD */ 1892 port->ip_flags |= DCD_ON; 1893 } 1894 } 1895 1896 /* Handle a CTS change */ 1897 if (sio_ir & hooks->intr_delta_cts) { 1898 /* ACK the interrupt */ 1899 writel(hooks->intr_delta_cts, 1900 &port->ip_mem->sio_ir.raw); 1901 1902 shadow = readl(&port->ip_serial_regs->shadow); 1903 1904 if ((port->ip_notify & N_DCTS) 1905 && (port->ip_port)) { 1906 the_port = port->ip_port; 1907 the_port->icount.cts = 1908 (shadow & IOC4_SHADOW_CTS) ? 1 : 0; 1909 wake_up_interruptible 1910 (&the_port->state->port.delta_msr_wait); 1911 } 1912 } 1913 1914 /* rx timeout interrupt. Must be some data available. Put this 1915 * before the check for rx_high since servicing this condition 1916 * may cause that condition to clear. 1917 */ 1918 if (sio_ir & hooks->intr_rx_timer) { 1919 /* ACK the interrupt */ 1920 writel(hooks->intr_rx_timer, 1921 &port->ip_mem->sio_ir.raw); 1922 1923 if ((port->ip_notify & N_DATA_READY) 1924 && (port->ip_port)) { 1925 /* ip_lock is set on call here */ 1926 receive_chars(port->ip_port); 1927 } 1928 } 1929 1930 /* rx high interrupt. Must be after rx_timer. */ 1931 else if (sio_ir & hooks->intr_rx_high) { 1932 /* Data available, notify upper layer */ 1933 if ((port->ip_notify & N_DATA_READY) 1934 && port->ip_port) { 1935 /* ip_lock is set on call here */ 1936 receive_chars(port->ip_port); 1937 } 1938 1939 /* We can't ACK this interrupt. If receive_chars didn't 1940 * cause the condition to clear, we'll have to disable 1941 * the interrupt until the data is drained. 1942 * If the read was aborted, don't disable the interrupt 1943 * as this may cause us to hang indefinitely. An 1944 * aborted read generally means that this interrupt 1945 * hasn't been delivered to the cpu yet anyway, even 1946 * though we see it as asserted when we read the sio_ir. 1947 */ 1948 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) { 1949 if ((port->ip_flags & READ_ABORTED) == 0) { 1950 port->ip_ienb &= ~hooks->intr_rx_high; 1951 port->ip_flags |= INPUT_HIGH; 1952 } else { 1953 rx_high_rd_aborted++; 1954 } 1955 } 1956 } 1957 1958 /* We got a low water interrupt: notify upper layer to 1959 * send more data. Must come before tx_mt since servicing 1960 * this condition may cause that condition to clear. 1961 */ 1962 if (sio_ir & hooks->intr_tx_explicit) { 1963 port->ip_flags &= ~LOWAT_WRITTEN; 1964 1965 /* ACK the interrupt */ 1966 writel(hooks->intr_tx_explicit, 1967 &port->ip_mem->sio_ir.raw); 1968 1969 if (port->ip_notify & N_OUTPUT_LOWAT) 1970 ioc4_cb_output_lowat(port->ip_port); 1971 } 1972 1973 /* Handle tx_mt. Must come after tx_explicit. */ 1974 else if (sio_ir & hooks->intr_tx_mt) { 1975 /* If we are expecting a lowat notification 1976 * and we get to this point it probably means that for 1977 * some reason the tx_explicit didn't work as expected 1978 * (that can legitimately happen if the output buffer is 1979 * filled up in just the right way). 1980 * So send the notification now. 1981 */ 1982 if (port->ip_notify & N_OUTPUT_LOWAT) { 1983 ioc4_cb_output_lowat(port->ip_port); 1984 1985 /* We need to reload the sio_ir since the lowat 1986 * call may have caused another write to occur, 1987 * clearing the tx_mt condition. 1988 */ 1989 sio_ir = PENDING(port); 1990 } 1991 1992 /* If the tx_mt condition still persists even after the 1993 * lowat call, we've got some work to do. 1994 */ 1995 if (sio_ir & hooks->intr_tx_mt) { 1996 1997 /* If we are not currently expecting DMA input, 1998 * and the transmitter has just gone idle, 1999 * there is no longer any reason for DMA, so 2000 * disable it. 2001 */ 2002 if (!(port->ip_notify 2003 & (N_DATA_READY | N_DDCD))) { 2004 BUG_ON(!(port->ip_sscr 2005 & IOC4_SSCR_DMA_EN)); 2006 port->ip_sscr &= ~IOC4_SSCR_DMA_EN; 2007 writel(port->ip_sscr, 2008 &port->ip_serial_regs->sscr); 2009 } 2010 2011 /* Prevent infinite tx_mt interrupt */ 2012 port->ip_ienb &= ~hooks->intr_tx_mt; 2013 } 2014 } 2015 sio_ir = PENDING(port); 2016 2017 /* if the read was aborted and only hooks->intr_rx_high, 2018 * clear hooks->intr_rx_high, so we do not loop forever. 2019 */ 2020 2021 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) { 2022 sio_ir &= ~hooks->intr_rx_high; 2023 } 2024 } while (sio_ir & hooks->intr_all); 2025 2026 spin_unlock_irqrestore(&port->ip_lock, flags); 2027 2028 /* Re-enable interrupts before returning from interrupt handler. 2029 * Getting interrupted here is okay. It'll just v() our semaphore, and 2030 * we'll come through the loop again. 2031 */ 2032 2033 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES, 2034 IOC4_SIO_INTR_TYPE); 2035} 2036 2037/* 2038 * ioc4_cb_post_ncs - called for some basic errors 2039 * @port: port to use 2040 * @ncs: event 2041 */ 2042static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs) 2043{ 2044 struct uart_icount *icount; 2045 2046 icount = &the_port->icount; 2047 2048 if (ncs & NCS_BREAK) 2049 icount->brk++; 2050 if (ncs & NCS_FRAMING) 2051 icount->frame++; 2052 if (ncs & NCS_OVERRUN) 2053 icount->overrun++; 2054 if (ncs & NCS_PARITY) 2055 icount->parity++; 2056} 2057 2058/** 2059 * do_read - Read in bytes from the port. Return the number of bytes 2060 * actually read. 2061 * @the_port: port to use 2062 * @buf: place to put the stuff we read 2063 * @len: how big 'buf' is 2064 */ 2065 2066static inline int do_read(struct uart_port *the_port, unsigned char *buf, 2067 int len) 2068{ 2069 int prod_ptr, cons_ptr, total; 2070 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2071 struct ring *inring; 2072 struct ring_entry *entry; 2073 struct hooks *hooks; 2074 int byte_num; 2075 char *sc; 2076 int loop_counter; 2077 2078 BUG_ON(!(len >= 0)); 2079 BUG_ON(!port); 2080 hooks = port->ip_hooks; 2081 2082 /* There is a nasty timing issue in the IOC4. When the rx_timer 2083 * expires or the rx_high condition arises, we take an interrupt. 2084 * At some point while servicing the interrupt, we read bytes from 2085 * the ring buffer and re-arm the rx_timer. However the rx_timer is 2086 * not started until the first byte is received *after* it is armed, 2087 * and any bytes pending in the rx construction buffers are not drained 2088 * to memory until either there are 4 bytes available or the rx_timer 2089 * expires. This leads to a potential situation where data is left 2090 * in the construction buffers forever - 1 to 3 bytes were received 2091 * after the interrupt was generated but before the rx_timer was 2092 * re-armed. At that point as long as no subsequent bytes are received 2093 * the timer will never be started and the bytes will remain in the 2094 * construction buffer forever. The solution is to execute a DRAIN 2095 * command after rearming the timer. This way any bytes received before 2096 * the DRAIN will be drained to memory, and any bytes received after 2097 * the DRAIN will start the TIMER and be drained when it expires. 2098 * Luckily, this only needs to be done when the DMA buffer is empty 2099 * since there is no requirement that this function return all 2100 * available data as long as it returns some. 2101 */ 2102 /* Re-arm the timer */ 2103 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir); 2104 2105 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK; 2106 cons_ptr = port->ip_rx_cons; 2107 2108 if (prod_ptr == cons_ptr) { 2109 int reset_dma = 0; 2110 2111 /* Input buffer appears empty, do a flush. */ 2112 2113 /* DMA must be enabled for this to work. */ 2114 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) { 2115 port->ip_sscr |= IOC4_SSCR_DMA_EN; 2116 reset_dma = 1; 2117 } 2118 2119 /* Potential race condition: we must reload the srpir after 2120 * issuing the drain command, otherwise we could think the rx 2121 * buffer is empty, then take a very long interrupt, and when 2122 * we come back it's full and we wait forever for the drain to 2123 * complete. 2124 */ 2125 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN, 2126 &port->ip_serial_regs->sscr); 2127 prod_ptr = readl(&port->ip_serial_regs->srpir) 2128 & PROD_CONS_MASK; 2129 2130 /* We must not wait for the DRAIN to complete unless there are 2131 * at least 8 bytes (2 ring entries) available to receive the 2132 * data otherwise the DRAIN will never complete and we'll 2133 * deadlock here. 2134 * In fact, to make things easier, I'll just ignore the flush if 2135 * there is any data at all now available. 2136 */ 2137 if (prod_ptr == cons_ptr) { 2138 loop_counter = 0; 2139 while (readl(&port->ip_serial_regs->sscr) & 2140 IOC4_SSCR_RX_DRAIN) { 2141 loop_counter++; 2142 if (loop_counter > MAXITER) 2143 return -1; 2144 } 2145 2146 /* SIGH. We have to reload the prod_ptr *again* since 2147 * the drain may have caused it to change 2148 */ 2149 prod_ptr = readl(&port->ip_serial_regs->srpir) 2150 & PROD_CONS_MASK; 2151 } 2152 if (reset_dma) { 2153 port->ip_sscr &= ~IOC4_SSCR_DMA_EN; 2154 writel(port->ip_sscr, &port->ip_serial_regs->sscr); 2155 } 2156 } 2157 inring = port->ip_inring; 2158 port->ip_flags &= ~READ_ABORTED; 2159 2160 total = 0; 2161 loop_counter = 0xfffff; /* to avoid hangs */ 2162 2163 /* Grab bytes from the hardware */ 2164 while ((prod_ptr != cons_ptr) && (len > 0)) { 2165 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr); 2166 2167 if ( loop_counter-- <= 0 ) { 2168 printk(KERN_WARNING "IOC4 serial: " 2169 "possible hang condition/" 2170 "port stuck on read.\n"); 2171 break; 2172 } 2173 2174 /* According to the producer pointer, this ring entry 2175 * must contain some data. But if the PIO happened faster 2176 * than the DMA, the data may not be available yet, so let's 2177 * wait until it arrives. 2178 */ 2179 if ((entry->ring_allsc & RING_ANY_VALID) == 0) { 2180 /* Indicate the read is aborted so we don't disable 2181 * the interrupt thinking that the consumer is 2182 * congested. 2183 */ 2184 port->ip_flags |= READ_ABORTED; 2185 len = 0; 2186 break; 2187 } 2188 2189 /* Load the bytes/status out of the ring entry */ 2190 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) { 2191 sc = &(entry->ring_sc[byte_num]); 2192 2193 /* Check for change in modem state or overrun */ 2194 if ((*sc & IOC4_RXSB_MODEM_VALID) 2195 && (port->ip_notify & N_DDCD)) { 2196 /* Notify upper layer if DCD dropped */ 2197 2198 if ((port->ip_flags & DCD_ON) 2199 && !(*sc & IOC4_RXSB_DCD)) { 2200 2201 /* If we have already copied some data, 2202 * return it. We'll pick up the carrier 2203 * drop on the next pass. That way we 2204 * don't throw away the data that has 2205 * already been copied back to 2206 * the caller's buffer. 2207 */ 2208 if (total > 0) { 2209 len = 0; 2210 break; 2211 } 2212 port->ip_flags &= ~DCD_ON; 2213 2214 /* Turn off this notification so the 2215 * carrier drop protocol won't see it 2216 * again when it does a read. 2217 */ 2218 *sc &= ~IOC4_RXSB_MODEM_VALID; 2219 2220 /* To keep things consistent, we need 2221 * to update the consumer pointer so 2222 * the next reader won't come in and 2223 * try to read the same ring entries 2224 * again. This must be done here before 2225 * the dcd change. 2226 */ 2227 2228 if ((entry->ring_allsc & RING_ANY_VALID) 2229 == 0) { 2230 cons_ptr += (int)sizeof 2231 (struct ring_entry); 2232 cons_ptr &= PROD_CONS_MASK; 2233 } 2234 writel(cons_ptr, 2235 &port->ip_serial_regs->srcir); 2236 port->ip_rx_cons = cons_ptr; 2237 2238 /* Notify upper layer of carrier drop */ 2239 if ((port->ip_notify & N_DDCD) 2240 && port->ip_port) { 2241 the_port->icount.dcd = 0; 2242 wake_up_interruptible 2243 (&the_port->state-> 2244 port.delta_msr_wait); 2245 } 2246 2247 /* If we had any data to return, we 2248 * would have returned it above. 2249 */ 2250 return 0; 2251 } 2252 } 2253 if (*sc & IOC4_RXSB_MODEM_VALID) { 2254 /* Notify that an input overrun occurred */ 2255 if ((*sc & IOC4_RXSB_OVERRUN) 2256 && (port->ip_notify & N_OVERRUN_ERROR)) { 2257 ioc4_cb_post_ncs(the_port, NCS_OVERRUN); 2258 } 2259 /* Don't look at this byte again */ 2260 *sc &= ~IOC4_RXSB_MODEM_VALID; 2261 } 2262 2263 /* Check for valid data or RX errors */ 2264 if ((*sc & IOC4_RXSB_DATA_VALID) && 2265 ((*sc & (IOC4_RXSB_PAR_ERR 2266 | IOC4_RXSB_FRAME_ERR 2267 | IOC4_RXSB_BREAK)) 2268 && (port->ip_notify & (N_PARITY_ERROR 2269 | N_FRAMING_ERROR 2270 | N_BREAK)))) { 2271 /* There is an error condition on the next byte. 2272 * If we have already transferred some bytes, 2273 * we'll stop here. Otherwise if this is the 2274 * first byte to be read, we'll just transfer 2275 * it alone after notifying the 2276 * upper layer of its status. 2277 */ 2278 if (total > 0) { 2279 len = 0; 2280 break; 2281 } else { 2282 if ((*sc & IOC4_RXSB_PAR_ERR) && 2283 (port->ip_notify & N_PARITY_ERROR)) { 2284 ioc4_cb_post_ncs(the_port, 2285 NCS_PARITY); 2286 } 2287 if ((*sc & IOC4_RXSB_FRAME_ERR) && 2288 (port->ip_notify & N_FRAMING_ERROR)){ 2289 ioc4_cb_post_ncs(the_port, 2290 NCS_FRAMING); 2291 } 2292 if ((*sc & IOC4_RXSB_BREAK) 2293 && (port->ip_notify & N_BREAK)) { 2294 ioc4_cb_post_ncs 2295 (the_port, 2296 NCS_BREAK); 2297 } 2298 len = 1; 2299 } 2300 } 2301 if (*sc & IOC4_RXSB_DATA_VALID) { 2302 *sc &= ~IOC4_RXSB_DATA_VALID; 2303 *buf = entry->ring_data[byte_num]; 2304 buf++; 2305 len--; 2306 total++; 2307 } 2308 } 2309 2310 /* If we used up this entry entirely, go on to the next one, 2311 * otherwise we must have run out of buffer space, so 2312 * leave the consumer pointer here for the next read in case 2313 * there are still unread bytes in this entry. 2314 */ 2315 if ((entry->ring_allsc & RING_ANY_VALID) == 0) { 2316 cons_ptr += (int)sizeof(struct ring_entry); 2317 cons_ptr &= PROD_CONS_MASK; 2318 } 2319 } 2320 2321 /* Update consumer pointer and re-arm rx timer interrupt */ 2322 writel(cons_ptr, &port->ip_serial_regs->srcir); 2323 port->ip_rx_cons = cons_ptr; 2324 2325 /* If we have now dipped below the rx high water mark and we have 2326 * rx_high interrupt turned off, we can now turn it back on again. 2327 */ 2328 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr) 2329 & PROD_CONS_MASK) < ((port->ip_sscr & 2330 IOC4_SSCR_RX_THRESHOLD) 2331 << IOC4_PROD_CONS_PTR_OFF))) { 2332 port->ip_flags &= ~INPUT_HIGH; 2333 enable_intrs(port, hooks->intr_rx_high); 2334 } 2335 return total; 2336} 2337 2338/** 2339 * receive_chars - upper level read. Called with ip_lock. 2340 * @the_port: port to read from 2341 */ 2342static void receive_chars(struct uart_port *the_port) 2343{ 2344 unsigned char ch[IOC4_MAX_CHARS]; 2345 int read_count, request_count = IOC4_MAX_CHARS; 2346 struct uart_icount *icount; 2347 struct uart_state *state = the_port->state; 2348 unsigned long pflags; 2349 2350 /* Make sure all the pointers are "good" ones */ 2351 if (!state) 2352 return; 2353 2354 spin_lock_irqsave(&the_port->lock, pflags); 2355 2356 request_count = tty_buffer_request_room(&state->port, IOC4_MAX_CHARS); 2357 2358 if (request_count > 0) { 2359 icount = &the_port->icount; 2360 read_count = do_read(the_port, ch, request_count); 2361 if (read_count > 0) { 2362 tty_insert_flip_string(&state->port, ch, read_count); 2363 icount->rx += read_count; 2364 } 2365 } 2366 2367 spin_unlock_irqrestore(&the_port->lock, pflags); 2368 2369 tty_flip_buffer_push(&state->port); 2370} 2371 2372/** 2373 * ic4_type - What type of console are we? 2374 * @port: Port to operate with (we ignore since we only have one port) 2375 * 2376 */ 2377static const char *ic4_type(struct uart_port *the_port) 2378{ 2379 if (the_port->mapbase == PROTO_RS232) 2380 return "SGI IOC4 Serial [rs232]"; 2381 else 2382 return "SGI IOC4 Serial [rs422]"; 2383} 2384 2385/** 2386 * ic4_tx_empty - Is the transmitter empty? 2387 * @port: Port to operate on 2388 * 2389 */ 2390static unsigned int ic4_tx_empty(struct uart_port *the_port) 2391{ 2392 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2393 unsigned int ret = 0; 2394 2395 if (port_is_active(port, the_port)) { 2396 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT) 2397 ret = TIOCSER_TEMT; 2398 } 2399 return ret; 2400} 2401 2402/** 2403 * ic4_stop_tx - stop the transmitter 2404 * @port: Port to operate on 2405 * 2406 */ 2407static void ic4_stop_tx(struct uart_port *the_port) 2408{ 2409 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2410 2411 if (port_is_active(port, the_port)) 2412 set_notification(port, N_OUTPUT_LOWAT, 0); 2413} 2414 2415/** 2416 * null_void_function - 2417 * @port: Port to operate on 2418 * 2419 */ 2420static void null_void_function(struct uart_port *the_port) 2421{ 2422} 2423 2424/** 2425 * ic4_shutdown - shut down the port - free irq and disable 2426 * @port: Port to shut down 2427 * 2428 */ 2429static void ic4_shutdown(struct uart_port *the_port) 2430{ 2431 unsigned long port_flags; 2432 struct ioc4_port *port; 2433 struct uart_state *state; 2434 2435 port = get_ioc4_port(the_port, 0); 2436 if (!port) 2437 return; 2438 2439 state = the_port->state; 2440 port->ip_port = NULL; 2441 2442 wake_up_interruptible(&state->port.delta_msr_wait); 2443 2444 if (state->port.tty) 2445 set_bit(TTY_IO_ERROR, &state->port.tty->flags); 2446 2447 spin_lock_irqsave(&the_port->lock, port_flags); 2448 set_notification(port, N_ALL, 0); 2449 port->ip_flags = PORT_INACTIVE; 2450 spin_unlock_irqrestore(&the_port->lock, port_flags); 2451} 2452 2453/** 2454 * ic4_set_mctrl - set control lines (dtr, rts, etc) 2455 * @port: Port to operate on 2456 * @mctrl: Lines to set/unset 2457 * 2458 */ 2459static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl) 2460{ 2461 unsigned char mcr = 0; 2462 struct ioc4_port *port; 2463 2464 port = get_ioc4_port(the_port, 0); 2465 if (!port_is_active(port, the_port)) 2466 return; 2467 2468 if (mctrl & TIOCM_RTS) 2469 mcr |= UART_MCR_RTS; 2470 if (mctrl & TIOCM_DTR) 2471 mcr |= UART_MCR_DTR; 2472 if (mctrl & TIOCM_OUT1) 2473 mcr |= UART_MCR_OUT1; 2474 if (mctrl & TIOCM_OUT2) 2475 mcr |= UART_MCR_OUT2; 2476 if (mctrl & TIOCM_LOOP) 2477 mcr |= UART_MCR_LOOP; 2478 2479 set_mcr(the_port, mcr, IOC4_SHADOW_DTR); 2480} 2481 2482/** 2483 * ic4_get_mctrl - get control line info 2484 * @port: port to operate on 2485 * 2486 */ 2487static unsigned int ic4_get_mctrl(struct uart_port *the_port) 2488{ 2489 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2490 uint32_t shadow; 2491 unsigned int ret = 0; 2492 2493 if (!port_is_active(port, the_port)) 2494 return 0; 2495 2496 shadow = readl(&port->ip_serial_regs->shadow); 2497 if (shadow & IOC4_SHADOW_DCD) 2498 ret |= TIOCM_CAR; 2499 if (shadow & IOC4_SHADOW_DR) 2500 ret |= TIOCM_DSR; 2501 if (shadow & IOC4_SHADOW_CTS) 2502 ret |= TIOCM_CTS; 2503 return ret; 2504} 2505 2506/** 2507 * ic4_start_tx - Start transmitter, flush any output 2508 * @port: Port to operate on 2509 * 2510 */ 2511static void ic4_start_tx(struct uart_port *the_port) 2512{ 2513 struct ioc4_port *port = get_ioc4_port(the_port, 0); 2514 2515 if (port_is_active(port, the_port)) { 2516 set_notification(port, N_OUTPUT_LOWAT, 1); 2517 enable_intrs(port, port->ip_hooks->intr_tx_mt); 2518 } 2519} 2520 2521/** 2522 * ic4_break_ctl - handle breaks 2523 * @port: Port to operate on 2524 * @break_state: Break state 2525 * 2526 */ 2527static void ic4_break_ctl(struct uart_port *the_port, int break_state) 2528{ 2529} 2530 2531/** 2532 * ic4_startup - Start up the serial port 2533 * @port: Port to operate on 2534 * 2535 */ 2536static int ic4_startup(struct uart_port *the_port) 2537{ 2538 int retval; 2539 struct ioc4_port *port; 2540 struct ioc4_control *control; 2541 struct uart_state *state; 2542 unsigned long port_flags; 2543 2544 if (!the_port) 2545 return -ENODEV; 2546 port = get_ioc4_port(the_port, 1); 2547 if (!port) 2548 return -ENODEV; 2549 state = the_port->state; 2550 2551 control = port->ip_control; 2552 if (!control) { 2553 port->ip_port = NULL; 2554 return -ENODEV; 2555 } 2556 2557 /* Start up the serial port */ 2558 spin_lock_irqsave(&the_port->lock, port_flags); 2559 retval = ic4_startup_local(the_port); 2560 spin_unlock_irqrestore(&the_port->lock, port_flags); 2561 return retval; 2562} 2563 2564/** 2565 * ic4_set_termios - set termios stuff 2566 * @port: port to operate on 2567 * @termios: New settings 2568 * @termios: Old 2569 * 2570 */ 2571static void 2572ic4_set_termios(struct uart_port *the_port, 2573 struct ktermios *termios, struct ktermios *old_termios) 2574{ 2575 unsigned long port_flags; 2576 2577 spin_lock_irqsave(&the_port->lock, port_flags); 2578 ioc4_change_speed(the_port, termios, old_termios); 2579 spin_unlock_irqrestore(&the_port->lock, port_flags); 2580} 2581 2582/** 2583 * ic4_request_port - allocate resources for port - no op.... 2584 * @port: port to operate on 2585 * 2586 */ 2587static int ic4_request_port(struct uart_port *port) 2588{ 2589 return 0; 2590} 2591 2592/* Associate the uart functions above - given to serial core */ 2593 2594static struct uart_ops ioc4_ops = { 2595 .tx_empty = ic4_tx_empty, 2596 .set_mctrl = ic4_set_mctrl, 2597 .get_mctrl = ic4_get_mctrl, 2598 .stop_tx = ic4_stop_tx, 2599 .start_tx = ic4_start_tx, 2600 .stop_rx = null_void_function, 2601 .break_ctl = ic4_break_ctl, 2602 .startup = ic4_startup, 2603 .shutdown = ic4_shutdown, 2604 .set_termios = ic4_set_termios, 2605 .type = ic4_type, 2606 .release_port = null_void_function, 2607 .request_port = ic4_request_port, 2608}; 2609 2610/* 2611 * Boot-time initialization code 2612 */ 2613 2614static struct uart_driver ioc4_uart_rs232 = { 2615 .owner = THIS_MODULE, 2616 .driver_name = "ioc4_serial_rs232", 2617 .dev_name = DEVICE_NAME_RS232, 2618 .major = DEVICE_MAJOR, 2619 .minor = DEVICE_MINOR_RS232, 2620 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS, 2621}; 2622 2623static struct uart_driver ioc4_uart_rs422 = { 2624 .owner = THIS_MODULE, 2625 .driver_name = "ioc4_serial_rs422", 2626 .dev_name = DEVICE_NAME_RS422, 2627 .major = DEVICE_MAJOR, 2628 .minor = DEVICE_MINOR_RS422, 2629 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS, 2630}; 2631 2632 2633/** 2634 * ioc4_serial_remove_one - detach function 2635 * 2636 * @idd: IOC4 master module data for this IOC4 2637 */ 2638 2639static int ioc4_serial_remove_one(struct ioc4_driver_data *idd) 2640{ 2641 int port_num, port_type; 2642 struct ioc4_control *control; 2643 struct uart_port *the_port; 2644 struct ioc4_port *port; 2645 struct ioc4_soft *soft; 2646 2647 /* If serial driver did not attach, don't try to detach */ 2648 control = idd->idd_serial_data; 2649 if (!control) 2650 return 0; 2651 2652 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) { 2653 for (port_type = UART_PORT_MIN; 2654 port_type < UART_PORT_COUNT; 2655 port_type++) { 2656 the_port = &control->ic_port[port_num].icp_uart_port 2657 [port_type]; 2658 if (the_port) { 2659 switch (port_type) { 2660 case UART_PORT_RS422: 2661 uart_remove_one_port(&ioc4_uart_rs422, 2662 the_port); 2663 break; 2664 default: 2665 case UART_PORT_RS232: 2666 uart_remove_one_port(&ioc4_uart_rs232, 2667 the_port); 2668 break; 2669 } 2670 } 2671 } 2672 port = control->ic_port[port_num].icp_port; 2673 /* we allocate in pairs */ 2674 if (!(port_num & 1) && port) { 2675 pci_free_consistent(port->ip_pdev, 2676 TOTAL_RING_BUF_SIZE, 2677 port->ip_cpu_ringbuf, 2678 port->ip_dma_ringbuf); 2679 kfree(port); 2680 } 2681 } 2682 soft = control->ic_soft; 2683 if (soft) { 2684 free_irq(control->ic_irq, soft); 2685 if (soft->is_ioc4_serial_addr) { 2686 iounmap(soft->is_ioc4_serial_addr); 2687 release_mem_region((unsigned long) 2688 soft->is_ioc4_serial_addr, 2689 sizeof(struct ioc4_serial)); 2690 } 2691 kfree(soft); 2692 } 2693 kfree(control); 2694 idd->idd_serial_data = NULL; 2695 2696 return 0; 2697} 2698 2699 2700/** 2701 * ioc4_serial_core_attach_rs232 - register with serial core 2702 * This is done during pci probing 2703 * @pdev: handle for this card 2704 */ 2705static inline int 2706ioc4_serial_core_attach(struct pci_dev *pdev, int port_type) 2707{ 2708 struct ioc4_port *port; 2709 struct uart_port *the_port; 2710 struct ioc4_driver_data *idd = pci_get_drvdata(pdev); 2711 struct ioc4_control *control = idd->idd_serial_data; 2712 int port_num; 2713 int port_type_idx; 2714 struct uart_driver *u_driver; 2715 2716 2717 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n", 2718 __func__, pdev, (void *)control)); 2719 2720 if (!control) 2721 return -ENODEV; 2722 2723 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232 2724 : UART_PORT_RS422; 2725 2726 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232 2727 : &ioc4_uart_rs422; 2728 2729 /* once around for each port on this card */ 2730 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) { 2731 the_port = &control->ic_port[port_num].icp_uart_port 2732 [port_type_idx]; 2733 port = control->ic_port[port_num].icp_port; 2734 port->ip_all_ports[port_type_idx] = the_port; 2735 2736 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n", 2737 __func__, (void *)the_port, 2738 (void *)port, 2739 port_type == PROTO_RS232 ? "rs232" : "rs422")); 2740 2741 /* membase, iobase and mapbase just need to be non-0 */ 2742 the_port->membase = (unsigned char __iomem *)1; 2743 the_port->iobase = (pdev->bus->number << 16) | port_num; 2744 the_port->line = (Num_of_ioc4_cards << 2) | port_num; 2745 the_port->mapbase = port_type; 2746 the_port->type = PORT_16550A; 2747 the_port->fifosize = IOC4_FIFO_CHARS; 2748 the_port->ops = &ioc4_ops; 2749 the_port->irq = control->ic_irq; 2750 the_port->dev = &pdev->dev; 2751 spin_lock_init(&the_port->lock); 2752 if (uart_add_one_port(u_driver, the_port) < 0) { 2753 printk(KERN_WARNING 2754 "%s: unable to add port %d bus %d\n", 2755 __func__, the_port->line, pdev->bus->number); 2756 } else { 2757 DPRINT_CONFIG( 2758 ("IOC4 serial port %d irq = %d, bus %d\n", 2759 the_port->line, the_port->irq, pdev->bus->number)); 2760 } 2761 } 2762 return 0; 2763} 2764 2765/** 2766 * ioc4_serial_attach_one - register attach function 2767 * called per card found from IOC4 master module. 2768 * @idd: Master module data for this IOC4 2769 */ 2770static int 2771ioc4_serial_attach_one(struct ioc4_driver_data *idd) 2772{ 2773 unsigned long tmp_addr1; 2774 struct ioc4_serial __iomem *serial; 2775 struct ioc4_soft *soft; 2776 struct ioc4_control *control; 2777 int ret = 0; 2778 2779 2780 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev, 2781 idd->idd_pci_id)); 2782 2783 /* PCI-RT does not bring out serial connections. 2784 * Do not attach to this particular IOC4. 2785 */ 2786 if (idd->idd_variant == IOC4_VARIANT_PCI_RT) 2787 return 0; 2788 2789 /* request serial registers */ 2790 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET; 2791 2792 if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial), 2793 "sioc4_uart")) { 2794 printk(KERN_WARNING 2795 "ioc4 (%p): unable to get request region for " 2796 "uart space\n", (void *)idd->idd_pdev); 2797 ret = -ENODEV; 2798 goto out1; 2799 } 2800 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial)); 2801 if (!serial) { 2802 printk(KERN_WARNING 2803 "ioc4 (%p) : unable to remap ioc4 serial register\n", 2804 (void *)idd->idd_pdev); 2805 ret = -ENODEV; 2806 goto out2; 2807 } 2808 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n", 2809 __func__, (void *)idd->idd_misc_regs, 2810 (void *)serial)); 2811 2812 /* Get memory for the new card */ 2813 control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL); 2814 2815 if (!control) { 2816 printk(KERN_WARNING "ioc4_attach_one" 2817 ": unable to get memory for the IOC4\n"); 2818 ret = -ENOMEM; 2819 goto out2; 2820 } 2821 idd->idd_serial_data = control; 2822 2823 /* Allocate the soft structure */ 2824 soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL); 2825 if (!soft) { 2826 printk(KERN_WARNING 2827 "ioc4 (%p): unable to get memory for the soft struct\n", 2828 (void *)idd->idd_pdev); 2829 ret = -ENOMEM; 2830 goto out3; 2831 } 2832 2833 spin_lock_init(&soft->is_ir_lock); 2834 soft->is_ioc4_misc_addr = idd->idd_misc_regs; 2835 soft->is_ioc4_serial_addr = serial; 2836 2837 /* Init the IOC4 */ 2838 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT, 2839 &idd->idd_misc_regs->sio_cr.raw); 2840 2841 /* Enable serial port mode select generic PIO pins as outputs */ 2842 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL 2843 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL, 2844 &idd->idd_misc_regs->gpcr_s.raw); 2845 2846 /* Clear and disable all serial interrupts */ 2847 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE); 2848 writel(~0, &idd->idd_misc_regs->sio_ir.raw); 2849 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC, 2850 IOC4_OTHER_INTR_TYPE); 2851 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw); 2852 control->ic_soft = soft; 2853 2854 /* Hook up interrupt handler */ 2855 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED, 2856 "sgi-ioc4serial", soft)) { 2857 control->ic_irq = idd->idd_pdev->irq; 2858 } else { 2859 printk(KERN_WARNING 2860 "%s : request_irq fails for IRQ 0x%x\n ", 2861 __func__, idd->idd_pdev->irq); 2862 } 2863 ret = ioc4_attach_local(idd); 2864 if (ret) 2865 goto out4; 2866 2867 /* register port with the serial core - 1 rs232, 1 rs422 */ 2868 2869 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232); 2870 if (ret) 2871 goto out4; 2872 2873 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422); 2874 if (ret) 2875 goto out5; 2876 2877 Num_of_ioc4_cards++; 2878 2879 return ret; 2880 2881 /* error exits that give back resources */ 2882out5: 2883 ioc4_serial_remove_one(idd); 2884 return ret; 2885out4: 2886 kfree(soft); 2887out3: 2888 kfree(control); 2889out2: 2890 if (serial) 2891 iounmap(serial); 2892 release_mem_region(tmp_addr1, sizeof(struct ioc4_serial)); 2893out1: 2894 2895 return ret; 2896} 2897 2898 2899static struct ioc4_submodule ioc4_serial_submodule = { 2900 .is_name = "IOC4_serial", 2901 .is_owner = THIS_MODULE, 2902 .is_probe = ioc4_serial_attach_one, 2903 .is_remove = ioc4_serial_remove_one, 2904}; 2905 2906/** 2907 * ioc4_serial_init - module init 2908 */ 2909static int __init ioc4_serial_init(void) 2910{ 2911 int ret; 2912 2913 /* register with serial core */ 2914 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) { 2915 printk(KERN_WARNING 2916 "%s: Couldn't register rs232 IOC4 serial driver\n", 2917 __func__); 2918 goto out; 2919 } 2920 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) { 2921 printk(KERN_WARNING 2922 "%s: Couldn't register rs422 IOC4 serial driver\n", 2923 __func__); 2924 goto out_uart_rs232; 2925 } 2926 2927 /* register with IOC4 main module */ 2928 ret = ioc4_register_submodule(&ioc4_serial_submodule); 2929 if (ret) 2930 goto out_uart_rs422; 2931 return 0; 2932 2933out_uart_rs422: 2934 uart_unregister_driver(&ioc4_uart_rs422); 2935out_uart_rs232: 2936 uart_unregister_driver(&ioc4_uart_rs232); 2937out: 2938 return ret; 2939} 2940 2941static void __exit ioc4_serial_exit(void) 2942{ 2943 ioc4_unregister_submodule(&ioc4_serial_submodule); 2944 uart_unregister_driver(&ioc4_uart_rs232); 2945 uart_unregister_driver(&ioc4_uart_rs422); 2946} 2947 2948late_initcall(ioc4_serial_init); /* Call only after tty init is done */ 2949module_exit(ioc4_serial_exit); 2950 2951MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>"); 2952MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card"); 2953MODULE_LICENSE("GPL"); 2954