1/* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12#undef DEBUG 13#include <linux/module.h> 14#include <linux/pci.h> 15#include <linux/string.h> 16#include <linux/kernel.h> 17#include <linux/slab.h> 18#include <linux/delay.h> 19#include <linux/tty.h> 20#include <linux/serial_reg.h> 21#include <linux/serial_core.h> 22#include <linux/8250_pci.h> 23#include <linux/bitops.h> 24#include <linux/rational.h> 25 26#include <asm/byteorder.h> 27#include <asm/io.h> 28 29#include <linux/dmaengine.h> 30#include <linux/platform_data/dma-dw.h> 31 32#include "8250.h" 33 34/* 35 * init function returns: 36 * > 0 - number of ports 37 * = 0 - use board->num_ports 38 * < 0 - error 39 */ 40struct pci_serial_quirk { 41 u32 vendor; 42 u32 device; 43 u32 subvendor; 44 u32 subdevice; 45 int (*probe)(struct pci_dev *dev); 46 int (*init)(struct pci_dev *dev); 47 int (*setup)(struct serial_private *, 48 const struct pciserial_board *, 49 struct uart_8250_port *, int); 50 void (*exit)(struct pci_dev *dev); 51}; 52 53#define PCI_NUM_BAR_RESOURCES 6 54 55struct serial_private { 56 struct pci_dev *dev; 57 unsigned int nr; 58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 59 struct pci_serial_quirk *quirk; 60 int line[0]; 61}; 62 63static int pci_default_setup(struct serial_private*, 64 const struct pciserial_board*, struct uart_8250_port *, int); 65 66static void moan_device(const char *str, struct pci_dev *dev) 67{ 68 dev_err(&dev->dev, 69 "%s: %s\n" 70 "Please send the output of lspci -vv, this\n" 71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 72 "manufacturer and name of serial board or\n" 73 "modem board to <linux-serial@vger.kernel.org>.\n", 74 pci_name(dev), str, dev->vendor, dev->device, 75 dev->subsystem_vendor, dev->subsystem_device); 76} 77 78static int 79setup_port(struct serial_private *priv, struct uart_8250_port *port, 80 int bar, int offset, int regshift) 81{ 82 struct pci_dev *dev = priv->dev; 83 84 if (bar >= PCI_NUM_BAR_RESOURCES) 85 return -EINVAL; 86 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 88 if (!priv->remapped_bar[bar]) 89 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); 90 if (!priv->remapped_bar[bar]) 91 return -ENOMEM; 92 93 port->port.iotype = UPIO_MEM; 94 port->port.iobase = 0; 95 port->port.mapbase = pci_resource_start(dev, bar) + offset; 96 port->port.membase = priv->remapped_bar[bar] + offset; 97 port->port.regshift = regshift; 98 } else { 99 port->port.iotype = UPIO_PORT; 100 port->port.iobase = pci_resource_start(dev, bar) + offset; 101 port->port.mapbase = 0; 102 port->port.membase = NULL; 103 port->port.regshift = 0; 104 } 105 return 0; 106} 107 108/* 109 * ADDI-DATA GmbH communication cards <info@addi-data.com> 110 */ 111static int addidata_apci7800_setup(struct serial_private *priv, 112 const struct pciserial_board *board, 113 struct uart_8250_port *port, int idx) 114{ 115 unsigned int bar = 0, offset = board->first_offset; 116 bar = FL_GET_BASE(board->flags); 117 118 if (idx < 2) { 119 offset += idx * board->uart_offset; 120 } else if ((idx >= 2) && (idx < 4)) { 121 bar += 1; 122 offset += ((idx - 2) * board->uart_offset); 123 } else if ((idx >= 4) && (idx < 6)) { 124 bar += 2; 125 offset += ((idx - 4) * board->uart_offset); 126 } else if (idx >= 6) { 127 bar += 3; 128 offset += ((idx - 6) * board->uart_offset); 129 } 130 131 return setup_port(priv, port, bar, offset, board->reg_shift); 132} 133 134/* 135 * AFAVLAB uses a different mixture of BARs and offsets 136 * Not that ugly ;) -- HW 137 */ 138static int 139afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 140 struct uart_8250_port *port, int idx) 141{ 142 unsigned int bar, offset = board->first_offset; 143 144 bar = FL_GET_BASE(board->flags); 145 if (idx < 4) 146 bar += idx; 147 else { 148 bar = 4; 149 offset += (idx - 4) * board->uart_offset; 150 } 151 152 return setup_port(priv, port, bar, offset, board->reg_shift); 153} 154 155/* 156 * HP's Remote Management Console. The Diva chip came in several 157 * different versions. N-class, L2000 and A500 have two Diva chips, each 158 * with 3 UARTs (the third UART on the second chip is unused). Superdome 159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 160 * one Diva chip, but it has been expanded to 5 UARTs. 161 */ 162static int pci_hp_diva_init(struct pci_dev *dev) 163{ 164 int rc = 0; 165 166 switch (dev->subsystem_device) { 167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 170 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 171 rc = 3; 172 break; 173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 174 rc = 2; 175 break; 176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 177 rc = 4; 178 break; 179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 181 rc = 1; 182 break; 183 } 184 185 return rc; 186} 187 188/* 189 * HP's Diva chip puts the 4th/5th serial port further out, and 190 * some serial ports are supposed to be hidden on certain models. 191 */ 192static int 193pci_hp_diva_setup(struct serial_private *priv, 194 const struct pciserial_board *board, 195 struct uart_8250_port *port, int idx) 196{ 197 unsigned int offset = board->first_offset; 198 unsigned int bar = FL_GET_BASE(board->flags); 199 200 switch (priv->dev->subsystem_device) { 201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 202 if (idx == 3) 203 idx++; 204 break; 205 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 206 if (idx > 0) 207 idx++; 208 if (idx > 2) 209 idx++; 210 break; 211 } 212 if (idx > 2) 213 offset = 0x18; 214 215 offset += idx * board->uart_offset; 216 217 return setup_port(priv, port, bar, offset, board->reg_shift); 218} 219 220/* 221 * Added for EKF Intel i960 serial boards 222 */ 223static int pci_inteli960ni_init(struct pci_dev *dev) 224{ 225 u32 oldval; 226 227 if (!(dev->subsystem_device & 0x1000)) 228 return -ENODEV; 229 230 /* is firmware started? */ 231 pci_read_config_dword(dev, 0x44, &oldval); 232 if (oldval == 0x00001000L) { /* RESET value */ 233 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 234 return -ENODEV; 235 } 236 return 0; 237} 238 239/* 240 * Some PCI serial cards using the PLX 9050 PCI interface chip require 241 * that the card interrupt be explicitly enabled or disabled. This 242 * seems to be mainly needed on card using the PLX which also use I/O 243 * mapped memory. 244 */ 245static int pci_plx9050_init(struct pci_dev *dev) 246{ 247 u8 irq_config; 248 void __iomem *p; 249 250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 251 moan_device("no memory in bar 0", dev); 252 return 0; 253 } 254 255 irq_config = 0x41; 256 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 258 irq_config = 0x43; 259 260 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 262 /* 263 * As the megawolf cards have the int pins active 264 * high, and have 2 UART chips, both ints must be 265 * enabled on the 9050. Also, the UARTS are set in 266 * 16450 mode by default, so we have to enable the 267 * 16C950 'enhanced' mode so that we can use the 268 * deep FIFOs 269 */ 270 irq_config = 0x5b; 271 /* 272 * enable/disable interrupts 273 */ 274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 275 if (p == NULL) 276 return -ENOMEM; 277 writel(irq_config, p + 0x4c); 278 279 /* 280 * Read the register back to ensure that it took effect. 281 */ 282 readl(p + 0x4c); 283 iounmap(p); 284 285 return 0; 286} 287 288static void pci_plx9050_exit(struct pci_dev *dev) 289{ 290 u8 __iomem *p; 291 292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 293 return; 294 295 /* 296 * disable interrupts 297 */ 298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 299 if (p != NULL) { 300 writel(0, p + 0x4c); 301 302 /* 303 * Read the register back to ensure that it took effect. 304 */ 305 readl(p + 0x4c); 306 iounmap(p); 307 } 308} 309 310#define NI8420_INT_ENABLE_REG 0x38 311#define NI8420_INT_ENABLE_BIT 0x2000 312 313static void pci_ni8420_exit(struct pci_dev *dev) 314{ 315 void __iomem *p; 316 unsigned int bar = 0; 317 318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 319 moan_device("no memory in bar", dev); 320 return; 321 } 322 323 p = pci_ioremap_bar(dev, bar); 324 if (p == NULL) 325 return; 326 327 /* Disable the CPU Interrupt */ 328 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 329 p + NI8420_INT_ENABLE_REG); 330 iounmap(p); 331} 332 333 334/* MITE registers */ 335#define MITE_IOWBSR1 0xc4 336#define MITE_IOWCR1 0xf4 337#define MITE_LCIMR1 0x08 338#define MITE_LCIMR2 0x10 339 340#define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 341 342static void pci_ni8430_exit(struct pci_dev *dev) 343{ 344 void __iomem *p; 345 unsigned int bar = 0; 346 347 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 348 moan_device("no memory in bar", dev); 349 return; 350 } 351 352 p = pci_ioremap_bar(dev, bar); 353 if (p == NULL) 354 return; 355 356 /* Disable the CPU Interrupt */ 357 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 358 iounmap(p); 359} 360 361/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 362static int 363sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 364 struct uart_8250_port *port, int idx) 365{ 366 unsigned int bar, offset = board->first_offset; 367 368 bar = 0; 369 370 if (idx < 4) { 371 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 372 offset += idx * board->uart_offset; 373 } else if (idx < 8) { 374 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 375 offset += idx * board->uart_offset + 0xC00; 376 } else /* we have only 8 ports on PMC-OCTALPRO */ 377 return 1; 378 379 return setup_port(priv, port, bar, offset, board->reg_shift); 380} 381 382/* 383* This does initialization for PMC OCTALPRO cards: 384* maps the device memory, resets the UARTs (needed, bc 385* if the module is removed and inserted again, the card 386* is in the sleep mode) and enables global interrupt. 387*/ 388 389/* global control register offset for SBS PMC-OctalPro */ 390#define OCT_REG_CR_OFF 0x500 391 392static int sbs_init(struct pci_dev *dev) 393{ 394 u8 __iomem *p; 395 396 p = pci_ioremap_bar(dev, 0); 397 398 if (p == NULL) 399 return -ENOMEM; 400 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 401 writeb(0x10, p + OCT_REG_CR_OFF); 402 udelay(50); 403 writeb(0x0, p + OCT_REG_CR_OFF); 404 405 /* Set bit-2 (INTENABLE) of Control Register */ 406 writeb(0x4, p + OCT_REG_CR_OFF); 407 iounmap(p); 408 409 return 0; 410} 411 412/* 413 * Disables the global interrupt of PMC-OctalPro 414 */ 415 416static void sbs_exit(struct pci_dev *dev) 417{ 418 u8 __iomem *p; 419 420 p = pci_ioremap_bar(dev, 0); 421 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 422 if (p != NULL) 423 writeb(0, p + OCT_REG_CR_OFF); 424 iounmap(p); 425} 426 427/* 428 * SIIG serial cards have an PCI interface chip which also controls 429 * the UART clocking frequency. Each UART can be clocked independently 430 * (except cards equipped with 4 UARTs) and initial clocking settings 431 * are stored in the EEPROM chip. It can cause problems because this 432 * version of serial driver doesn't support differently clocked UART's 433 * on single PCI card. To prevent this, initialization functions set 434 * high frequency clocking for all UART's on given card. It is safe (I 435 * hope) because it doesn't touch EEPROM settings to prevent conflicts 436 * with other OSes (like M$ DOS). 437 * 438 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 439 * 440 * There is two family of SIIG serial cards with different PCI 441 * interface chip and different configuration methods: 442 * - 10x cards have control registers in IO and/or memory space; 443 * - 20x cards have control registers in standard PCI configuration space. 444 * 445 * Note: all 10x cards have PCI device ids 0x10.. 446 * all 20x cards have PCI device ids 0x20.. 447 * 448 * There are also Quartet Serial cards which use Oxford Semiconductor 449 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 450 * 451 * Note: some SIIG cards are probed by the parport_serial object. 452 */ 453 454#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 455#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 456 457static int pci_siig10x_init(struct pci_dev *dev) 458{ 459 u16 data; 460 void __iomem *p; 461 462 switch (dev->device & 0xfff8) { 463 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 464 data = 0xffdf; 465 break; 466 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 467 data = 0xf7ff; 468 break; 469 default: /* 1S1P, 4S */ 470 data = 0xfffb; 471 break; 472 } 473 474 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 475 if (p == NULL) 476 return -ENOMEM; 477 478 writew(readw(p + 0x28) & data, p + 0x28); 479 readw(p + 0x28); 480 iounmap(p); 481 return 0; 482} 483 484#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 485#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 486 487static int pci_siig20x_init(struct pci_dev *dev) 488{ 489 u8 data; 490 491 /* Change clock frequency for the first UART. */ 492 pci_read_config_byte(dev, 0x6f, &data); 493 pci_write_config_byte(dev, 0x6f, data & 0xef); 494 495 /* If this card has 2 UART, we have to do the same with second UART. */ 496 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 497 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 498 pci_read_config_byte(dev, 0x73, &data); 499 pci_write_config_byte(dev, 0x73, data & 0xef); 500 } 501 return 0; 502} 503 504static int pci_siig_init(struct pci_dev *dev) 505{ 506 unsigned int type = dev->device & 0xff00; 507 508 if (type == 0x1000) 509 return pci_siig10x_init(dev); 510 else if (type == 0x2000) 511 return pci_siig20x_init(dev); 512 513 moan_device("Unknown SIIG card", dev); 514 return -ENODEV; 515} 516 517static int pci_siig_setup(struct serial_private *priv, 518 const struct pciserial_board *board, 519 struct uart_8250_port *port, int idx) 520{ 521 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 522 523 if (idx > 3) { 524 bar = 4; 525 offset = (idx - 4) * 8; 526 } 527 528 return setup_port(priv, port, bar, offset, 0); 529} 530 531/* 532 * Timedia has an explosion of boards, and to avoid the PCI table from 533 * growing *huge*, we use this function to collapse some 70 entries 534 * in the PCI table into one, for sanity's and compactness's sake. 535 */ 536static const unsigned short timedia_single_port[] = { 537 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 538}; 539 540static const unsigned short timedia_dual_port[] = { 541 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 542 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 543 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 544 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 545 0xD079, 0 546}; 547 548static const unsigned short timedia_quad_port[] = { 549 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 550 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 551 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 552 0xB157, 0 553}; 554 555static const unsigned short timedia_eight_port[] = { 556 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 557 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 558}; 559 560static const struct timedia_struct { 561 int num; 562 const unsigned short *ids; 563} timedia_data[] = { 564 { 1, timedia_single_port }, 565 { 2, timedia_dual_port }, 566 { 4, timedia_quad_port }, 567 { 8, timedia_eight_port } 568}; 569 570/* 571 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 572 * listing them individually, this driver merely grabs them all with 573 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 574 * and should be left free to be claimed by parport_serial instead. 575 */ 576static int pci_timedia_probe(struct pci_dev *dev) 577{ 578 /* 579 * Check the third digit of the subdevice ID 580 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 581 */ 582 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 583 dev_info(&dev->dev, 584 "ignoring Timedia subdevice %04x for parport_serial\n", 585 dev->subsystem_device); 586 return -ENODEV; 587 } 588 589 return 0; 590} 591 592static int pci_timedia_init(struct pci_dev *dev) 593{ 594 const unsigned short *ids; 595 int i, j; 596 597 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 598 ids = timedia_data[i].ids; 599 for (j = 0; ids[j]; j++) 600 if (dev->subsystem_device == ids[j]) 601 return timedia_data[i].num; 602 } 603 return 0; 604} 605 606/* 607 * Timedia/SUNIX uses a mixture of BARs and offsets 608 * Ugh, this is ugly as all hell --- TYT 609 */ 610static int 611pci_timedia_setup(struct serial_private *priv, 612 const struct pciserial_board *board, 613 struct uart_8250_port *port, int idx) 614{ 615 unsigned int bar = 0, offset = board->first_offset; 616 617 switch (idx) { 618 case 0: 619 bar = 0; 620 break; 621 case 1: 622 offset = board->uart_offset; 623 bar = 0; 624 break; 625 case 2: 626 bar = 1; 627 break; 628 case 3: 629 offset = board->uart_offset; 630 /* FALLTHROUGH */ 631 case 4: /* BAR 2 */ 632 case 5: /* BAR 3 */ 633 case 6: /* BAR 4 */ 634 case 7: /* BAR 5 */ 635 bar = idx - 2; 636 } 637 638 return setup_port(priv, port, bar, offset, board->reg_shift); 639} 640 641/* 642 * Some Titan cards are also a little weird 643 */ 644static int 645titan_400l_800l_setup(struct serial_private *priv, 646 const struct pciserial_board *board, 647 struct uart_8250_port *port, int idx) 648{ 649 unsigned int bar, offset = board->first_offset; 650 651 switch (idx) { 652 case 0: 653 bar = 1; 654 break; 655 case 1: 656 bar = 2; 657 break; 658 default: 659 bar = 4; 660 offset = (idx - 2) * board->uart_offset; 661 } 662 663 return setup_port(priv, port, bar, offset, board->reg_shift); 664} 665 666static int pci_xircom_init(struct pci_dev *dev) 667{ 668 msleep(100); 669 return 0; 670} 671 672static int pci_ni8420_init(struct pci_dev *dev) 673{ 674 void __iomem *p; 675 unsigned int bar = 0; 676 677 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 678 moan_device("no memory in bar", dev); 679 return 0; 680 } 681 682 p = pci_ioremap_bar(dev, bar); 683 if (p == NULL) 684 return -ENOMEM; 685 686 /* Enable CPU Interrupt */ 687 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 688 p + NI8420_INT_ENABLE_REG); 689 690 iounmap(p); 691 return 0; 692} 693 694#define MITE_IOWBSR1_WSIZE 0xa 695#define MITE_IOWBSR1_WIN_OFFSET 0x800 696#define MITE_IOWBSR1_WENAB (1 << 7) 697#define MITE_LCIMR1_IO_IE_0 (1 << 24) 698#define MITE_LCIMR2_SET_CPU_IE (1 << 31) 699#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 700 701static int pci_ni8430_init(struct pci_dev *dev) 702{ 703 void __iomem *p; 704 struct pci_bus_region region; 705 u32 device_window; 706 unsigned int bar = 0; 707 708 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 709 moan_device("no memory in bar", dev); 710 return 0; 711 } 712 713 p = pci_ioremap_bar(dev, bar); 714 if (p == NULL) 715 return -ENOMEM; 716 717 /* 718 * Set device window address and size in BAR0, while acknowledging that 719 * the resource structure may contain a translated address that differs 720 * from the address the device responds to. 721 */ 722 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 723 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 724 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 725 writel(device_window, p + MITE_IOWBSR1); 726 727 /* Set window access to go to RAMSEL IO address space */ 728 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 729 p + MITE_IOWCR1); 730 731 /* Enable IO Bus Interrupt 0 */ 732 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 733 734 /* Enable CPU Interrupt */ 735 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 736 737 iounmap(p); 738 return 0; 739} 740 741/* UART Port Control Register */ 742#define NI8430_PORTCON 0x0f 743#define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 744 745static int 746pci_ni8430_setup(struct serial_private *priv, 747 const struct pciserial_board *board, 748 struct uart_8250_port *port, int idx) 749{ 750 struct pci_dev *dev = priv->dev; 751 void __iomem *p; 752 unsigned int bar, offset = board->first_offset; 753 754 if (idx >= board->num_ports) 755 return 1; 756 757 bar = FL_GET_BASE(board->flags); 758 offset += idx * board->uart_offset; 759 760 p = pci_ioremap_bar(dev, bar); 761 if (!p) 762 return -ENOMEM; 763 764 /* enable the transceiver */ 765 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 766 p + offset + NI8430_PORTCON); 767 768 iounmap(p); 769 770 return setup_port(priv, port, bar, offset, board->reg_shift); 771} 772 773static int pci_netmos_9900_setup(struct serial_private *priv, 774 const struct pciserial_board *board, 775 struct uart_8250_port *port, int idx) 776{ 777 unsigned int bar; 778 779 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 780 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 781 /* netmos apparently orders BARs by datasheet layout, so serial 782 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 783 */ 784 bar = 3 * idx; 785 786 return setup_port(priv, port, bar, 0, board->reg_shift); 787 } else { 788 return pci_default_setup(priv, board, port, idx); 789 } 790} 791 792/* the 99xx series comes with a range of device IDs and a variety 793 * of capabilities: 794 * 795 * 9900 has varying capabilities and can cascade to sub-controllers 796 * (cascading should be purely internal) 797 * 9904 is hardwired with 4 serial ports 798 * 9912 and 9922 are hardwired with 2 serial ports 799 */ 800static int pci_netmos_9900_numports(struct pci_dev *dev) 801{ 802 unsigned int c = dev->class; 803 unsigned int pi; 804 unsigned short sub_serports; 805 806 pi = (c & 0xff); 807 808 if (pi == 2) { 809 return 1; 810 } else if ((pi == 0) && 811 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 812 /* two possibilities: 0x30ps encodes number of parallel and 813 * serial ports, or 0x1000 indicates *something*. This is not 814 * immediately obvious, since the 2s1p+4s configuration seems 815 * to offer all functionality on functions 0..2, while still 816 * advertising the same function 3 as the 4s+2s1p config. 817 */ 818 sub_serports = dev->subsystem_device & 0xf; 819 if (sub_serports > 0) { 820 return sub_serports; 821 } else { 822 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 823 return 0; 824 } 825 } 826 827 moan_device("unknown NetMos/Mostech program interface", dev); 828 return 0; 829} 830 831static int pci_netmos_init(struct pci_dev *dev) 832{ 833 /* subdevice 0x00PS means <P> parallel, <S> serial */ 834 unsigned int num_serial = dev->subsystem_device & 0xf; 835 836 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 837 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 838 return 0; 839 840 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 841 dev->subsystem_device == 0x0299) 842 return 0; 843 844 switch (dev->device) { /* FALLTHROUGH on all */ 845 case PCI_DEVICE_ID_NETMOS_9904: 846 case PCI_DEVICE_ID_NETMOS_9912: 847 case PCI_DEVICE_ID_NETMOS_9922: 848 case PCI_DEVICE_ID_NETMOS_9900: 849 num_serial = pci_netmos_9900_numports(dev); 850 break; 851 852 default: 853 if (num_serial == 0 ) { 854 moan_device("unknown NetMos/Mostech device", dev); 855 } 856 } 857 858 if (num_serial == 0) 859 return -ENODEV; 860 861 return num_serial; 862} 863 864/* 865 * These chips are available with optionally one parallel port and up to 866 * two serial ports. Unfortunately they all have the same product id. 867 * 868 * Basic configuration is done over a region of 32 I/O ports. The base 869 * ioport is called INTA or INTC, depending on docs/other drivers. 870 * 871 * The region of the 32 I/O ports is configured in POSIO0R... 872 */ 873 874/* registers */ 875#define ITE_887x_MISCR 0x9c 876#define ITE_887x_INTCBAR 0x78 877#define ITE_887x_UARTBAR 0x7c 878#define ITE_887x_PS0BAR 0x10 879#define ITE_887x_POSIO0 0x60 880 881/* I/O space size */ 882#define ITE_887x_IOSIZE 32 883/* I/O space size (bits 26-24; 8 bytes = 011b) */ 884#define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 885/* I/O space size (bits 26-24; 32 bytes = 101b) */ 886#define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 887/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 888#define ITE_887x_POSIO_SPEED (3 << 29) 889/* enable IO_Space bit */ 890#define ITE_887x_POSIO_ENABLE (1 << 31) 891 892static int pci_ite887x_init(struct pci_dev *dev) 893{ 894 /* inta_addr are the configuration addresses of the ITE */ 895 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 896 0x200, 0x280, 0 }; 897 int ret, i, type; 898 struct resource *iobase = NULL; 899 u32 miscr, uartbar, ioport; 900 901 /* search for the base-ioport */ 902 i = 0; 903 while (inta_addr[i] && iobase == NULL) { 904 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 905 "ite887x"); 906 if (iobase != NULL) { 907 /* write POSIO0R - speed | size | ioport */ 908 pci_write_config_dword(dev, ITE_887x_POSIO0, 909 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 910 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 911 /* write INTCBAR - ioport */ 912 pci_write_config_dword(dev, ITE_887x_INTCBAR, 913 inta_addr[i]); 914 ret = inb(inta_addr[i]); 915 if (ret != 0xff) { 916 /* ioport connected */ 917 break; 918 } 919 release_region(iobase->start, ITE_887x_IOSIZE); 920 iobase = NULL; 921 } 922 i++; 923 } 924 925 if (!inta_addr[i]) { 926 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 927 return -ENODEV; 928 } 929 930 /* start of undocumented type checking (see parport_pc.c) */ 931 type = inb(iobase->start + 0x18) & 0x0f; 932 933 switch (type) { 934 case 0x2: /* ITE8871 (1P) */ 935 case 0xa: /* ITE8875 (1P) */ 936 ret = 0; 937 break; 938 case 0xe: /* ITE8872 (2S1P) */ 939 ret = 2; 940 break; 941 case 0x6: /* ITE8873 (1S) */ 942 ret = 1; 943 break; 944 case 0x8: /* ITE8874 (2S) */ 945 ret = 2; 946 break; 947 default: 948 moan_device("Unknown ITE887x", dev); 949 ret = -ENODEV; 950 } 951 952 /* configure all serial ports */ 953 for (i = 0; i < ret; i++) { 954 /* read the I/O port from the device */ 955 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 956 &ioport); 957 ioport &= 0x0000FF00; /* the actual base address */ 958 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 959 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 960 ITE_887x_POSIO_IOSIZE_8 | ioport); 961 962 /* write the ioport to the UARTBAR */ 963 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 964 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 965 uartbar |= (ioport << (16 * i)); /* set the ioport */ 966 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 967 968 /* get current config */ 969 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 970 /* disable interrupts (UARTx_Routing[3:0]) */ 971 miscr &= ~(0xf << (12 - 4 * i)); 972 /* activate the UART (UARTx_En) */ 973 miscr |= 1 << (23 - i); 974 /* write new config with activated UART */ 975 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 976 } 977 978 if (ret <= 0) { 979 /* the device has no UARTs if we get here */ 980 release_region(iobase->start, ITE_887x_IOSIZE); 981 } 982 983 return ret; 984} 985 986static void pci_ite887x_exit(struct pci_dev *dev) 987{ 988 u32 ioport; 989 /* the ioport is bit 0-15 in POSIO0R */ 990 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 991 ioport &= 0xffff; 992 release_region(ioport, ITE_887x_IOSIZE); 993} 994 995/* 996 * EndRun Technologies. 997 * Determine the number of ports available on the device. 998 */ 999#define PCI_VENDOR_ID_ENDRUN 0x7401 1000#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1001 1002static int pci_endrun_init(struct pci_dev *dev) 1003{ 1004 u8 __iomem *p; 1005 unsigned long deviceID; 1006 unsigned int number_uarts = 0; 1007 1008 /* EndRun device is all 0xexxx */ 1009 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1010 (dev->device & 0xf000) != 0xe000) 1011 return 0; 1012 1013 p = pci_iomap(dev, 0, 5); 1014 if (p == NULL) 1015 return -ENOMEM; 1016 1017 deviceID = ioread32(p); 1018 /* EndRun device */ 1019 if (deviceID == 0x07000200) { 1020 number_uarts = ioread8(p + 4); 1021 dev_dbg(&dev->dev, 1022 "%d ports detected on EndRun PCI Express device\n", 1023 number_uarts); 1024 } 1025 pci_iounmap(dev, p); 1026 return number_uarts; 1027} 1028 1029/* 1030 * Oxford Semiconductor Inc. 1031 * Check that device is part of the Tornado range of devices, then determine 1032 * the number of ports available on the device. 1033 */ 1034static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1035{ 1036 u8 __iomem *p; 1037 unsigned long deviceID; 1038 unsigned int number_uarts = 0; 1039 1040 /* OxSemi Tornado devices are all 0xCxxx */ 1041 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1042 (dev->device & 0xF000) != 0xC000) 1043 return 0; 1044 1045 p = pci_iomap(dev, 0, 5); 1046 if (p == NULL) 1047 return -ENOMEM; 1048 1049 deviceID = ioread32(p); 1050 /* Tornado device */ 1051 if (deviceID == 0x07000200) { 1052 number_uarts = ioread8(p + 4); 1053 dev_dbg(&dev->dev, 1054 "%d ports detected on Oxford PCI Express device\n", 1055 number_uarts); 1056 } 1057 pci_iounmap(dev, p); 1058 return number_uarts; 1059} 1060 1061static int pci_asix_setup(struct serial_private *priv, 1062 const struct pciserial_board *board, 1063 struct uart_8250_port *port, int idx) 1064{ 1065 port->bugs |= UART_BUG_PARITY; 1066 return pci_default_setup(priv, board, port, idx); 1067} 1068 1069/* Quatech devices have their own extra interface features */ 1070 1071struct quatech_feature { 1072 u16 devid; 1073 bool amcc; 1074}; 1075 1076#define QPCR_TEST_FOR1 0x3F 1077#define QPCR_TEST_GET1 0x00 1078#define QPCR_TEST_FOR2 0x40 1079#define QPCR_TEST_GET2 0x40 1080#define QPCR_TEST_FOR3 0x80 1081#define QPCR_TEST_GET3 0x40 1082#define QPCR_TEST_FOR4 0xC0 1083#define QPCR_TEST_GET4 0x80 1084 1085#define QOPR_CLOCK_X1 0x0000 1086#define QOPR_CLOCK_X2 0x0001 1087#define QOPR_CLOCK_X4 0x0002 1088#define QOPR_CLOCK_X8 0x0003 1089#define QOPR_CLOCK_RATE_MASK 0x0003 1090 1091 1092static struct quatech_feature quatech_cards[] = { 1093 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1096 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1097 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1098 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1099 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1100 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1102 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1104 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1105 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1106 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1107 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1108 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1111 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1112 { 0, } 1113}; 1114 1115static int pci_quatech_amcc(u16 devid) 1116{ 1117 struct quatech_feature *qf = &quatech_cards[0]; 1118 while (qf->devid) { 1119 if (qf->devid == devid) 1120 return qf->amcc; 1121 qf++; 1122 } 1123 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1124 return 0; 1125}; 1126 1127static int pci_quatech_rqopr(struct uart_8250_port *port) 1128{ 1129 unsigned long base = port->port.iobase; 1130 u8 LCR, val; 1131 1132 LCR = inb(base + UART_LCR); 1133 outb(0xBF, base + UART_LCR); 1134 val = inb(base + UART_SCR); 1135 outb(LCR, base + UART_LCR); 1136 return val; 1137} 1138 1139static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1140{ 1141 unsigned long base = port->port.iobase; 1142 u8 LCR, val; 1143 1144 LCR = inb(base + UART_LCR); 1145 outb(0xBF, base + UART_LCR); 1146 val = inb(base + UART_SCR); 1147 outb(qopr, base + UART_SCR); 1148 outb(LCR, base + UART_LCR); 1149} 1150 1151static int pci_quatech_rqmcr(struct uart_8250_port *port) 1152{ 1153 unsigned long base = port->port.iobase; 1154 u8 LCR, val, qmcr; 1155 1156 LCR = inb(base + UART_LCR); 1157 outb(0xBF, base + UART_LCR); 1158 val = inb(base + UART_SCR); 1159 outb(val | 0x10, base + UART_SCR); 1160 qmcr = inb(base + UART_MCR); 1161 outb(val, base + UART_SCR); 1162 outb(LCR, base + UART_LCR); 1163 1164 return qmcr; 1165} 1166 1167static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1168{ 1169 unsigned long base = port->port.iobase; 1170 u8 LCR, val; 1171 1172 LCR = inb(base + UART_LCR); 1173 outb(0xBF, base + UART_LCR); 1174 val = inb(base + UART_SCR); 1175 outb(val | 0x10, base + UART_SCR); 1176 outb(qmcr, base + UART_MCR); 1177 outb(val, base + UART_SCR); 1178 outb(LCR, base + UART_LCR); 1179} 1180 1181static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1182{ 1183 unsigned long base = port->port.iobase; 1184 u8 LCR, val; 1185 1186 LCR = inb(base + UART_LCR); 1187 outb(0xBF, base + UART_LCR); 1188 val = inb(base + UART_SCR); 1189 if (val & 0x20) { 1190 outb(0x80, UART_LCR); 1191 if (!(inb(UART_SCR) & 0x20)) { 1192 outb(LCR, base + UART_LCR); 1193 return 1; 1194 } 1195 } 1196 return 0; 1197} 1198 1199static int pci_quatech_test(struct uart_8250_port *port) 1200{ 1201 u8 reg; 1202 u8 qopr = pci_quatech_rqopr(port); 1203 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1204 reg = pci_quatech_rqopr(port) & 0xC0; 1205 if (reg != QPCR_TEST_GET1) 1206 return -EINVAL; 1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1208 reg = pci_quatech_rqopr(port) & 0xC0; 1209 if (reg != QPCR_TEST_GET2) 1210 return -EINVAL; 1211 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1212 reg = pci_quatech_rqopr(port) & 0xC0; 1213 if (reg != QPCR_TEST_GET3) 1214 return -EINVAL; 1215 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1216 reg = pci_quatech_rqopr(port) & 0xC0; 1217 if (reg != QPCR_TEST_GET4) 1218 return -EINVAL; 1219 1220 pci_quatech_wqopr(port, qopr); 1221 return 0; 1222} 1223 1224static int pci_quatech_clock(struct uart_8250_port *port) 1225{ 1226 u8 qopr, reg, set; 1227 unsigned long clock; 1228 1229 if (pci_quatech_test(port) < 0) 1230 return 1843200; 1231 1232 qopr = pci_quatech_rqopr(port); 1233 1234 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1235 reg = pci_quatech_rqopr(port); 1236 if (reg & QOPR_CLOCK_X8) { 1237 clock = 1843200; 1238 goto out; 1239 } 1240 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1241 reg = pci_quatech_rqopr(port); 1242 if (!(reg & QOPR_CLOCK_X8)) { 1243 clock = 1843200; 1244 goto out; 1245 } 1246 reg &= QOPR_CLOCK_X8; 1247 if (reg == QOPR_CLOCK_X2) { 1248 clock = 3685400; 1249 set = QOPR_CLOCK_X2; 1250 } else if (reg == QOPR_CLOCK_X4) { 1251 clock = 7372800; 1252 set = QOPR_CLOCK_X4; 1253 } else if (reg == QOPR_CLOCK_X8) { 1254 clock = 14745600; 1255 set = QOPR_CLOCK_X8; 1256 } else { 1257 clock = 1843200; 1258 set = QOPR_CLOCK_X1; 1259 } 1260 qopr &= ~QOPR_CLOCK_RATE_MASK; 1261 qopr |= set; 1262 1263out: 1264 pci_quatech_wqopr(port, qopr); 1265 return clock; 1266} 1267 1268static int pci_quatech_rs422(struct uart_8250_port *port) 1269{ 1270 u8 qmcr; 1271 int rs422 = 0; 1272 1273 if (!pci_quatech_has_qmcr(port)) 1274 return 0; 1275 qmcr = pci_quatech_rqmcr(port); 1276 pci_quatech_wqmcr(port, 0xFF); 1277 if (pci_quatech_rqmcr(port)) 1278 rs422 = 1; 1279 pci_quatech_wqmcr(port, qmcr); 1280 return rs422; 1281} 1282 1283static int pci_quatech_init(struct pci_dev *dev) 1284{ 1285 if (pci_quatech_amcc(dev->device)) { 1286 unsigned long base = pci_resource_start(dev, 0); 1287 if (base) { 1288 u32 tmp; 1289 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1290 tmp = inl(base + 0x3c); 1291 outl(tmp | 0x01000000, base + 0x3c); 1292 outl(tmp &= ~0x01000000, base + 0x3c); 1293 } 1294 } 1295 return 0; 1296} 1297 1298static int pci_quatech_setup(struct serial_private *priv, 1299 const struct pciserial_board *board, 1300 struct uart_8250_port *port, int idx) 1301{ 1302 /* Needed by pci_quatech calls below */ 1303 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1304 /* Set up the clocking */ 1305 port->port.uartclk = pci_quatech_clock(port); 1306 /* For now just warn about RS422 */ 1307 if (pci_quatech_rs422(port)) 1308 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1309 return pci_default_setup(priv, board, port, idx); 1310} 1311 1312static void pci_quatech_exit(struct pci_dev *dev) 1313{ 1314} 1315 1316static int pci_default_setup(struct serial_private *priv, 1317 const struct pciserial_board *board, 1318 struct uart_8250_port *port, int idx) 1319{ 1320 unsigned int bar, offset = board->first_offset, maxnr; 1321 1322 bar = FL_GET_BASE(board->flags); 1323 if (board->flags & FL_BASE_BARS) 1324 bar += idx; 1325 else 1326 offset += idx * board->uart_offset; 1327 1328 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1329 (board->reg_shift + 3); 1330 1331 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1332 return 1; 1333 1334 return setup_port(priv, port, bar, offset, board->reg_shift); 1335} 1336 1337static int pci_pericom_setup(struct serial_private *priv, 1338 const struct pciserial_board *board, 1339 struct uart_8250_port *port, int idx) 1340{ 1341 unsigned int bar, offset = board->first_offset, maxnr; 1342 1343 bar = FL_GET_BASE(board->flags); 1344 if (board->flags & FL_BASE_BARS) 1345 bar += idx; 1346 else 1347 offset += idx * board->uart_offset; 1348 1349 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1350 (board->reg_shift + 3); 1351 1352 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1353 return 1; 1354 1355 port->port.uartclk = 14745600; 1356 1357 return setup_port(priv, port, bar, offset, board->reg_shift); 1358} 1359 1360static int 1361ce4100_serial_setup(struct serial_private *priv, 1362 const struct pciserial_board *board, 1363 struct uart_8250_port *port, int idx) 1364{ 1365 int ret; 1366 1367 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1368 port->port.iotype = UPIO_MEM32; 1369 port->port.type = PORT_XSCALE; 1370 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1371 port->port.regshift = 2; 1372 1373 return ret; 1374} 1375 1376#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1377#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1378 1379#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a 1380#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c 1381 1382#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3 1383#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4 1384 1385#define BYT_PRV_CLK 0x800 1386#define BYT_PRV_CLK_EN (1 << 0) 1387#define BYT_PRV_CLK_M_VAL_SHIFT 1 1388#define BYT_PRV_CLK_N_VAL_SHIFT 16 1389#define BYT_PRV_CLK_UPDATE (1 << 31) 1390 1391#define BYT_TX_OVF_INT 0x820 1392#define BYT_TX_OVF_INT_MASK (1 << 1) 1393 1394static void 1395byt_set_termios(struct uart_port *p, struct ktermios *termios, 1396 struct ktermios *old) 1397{ 1398 unsigned int baud = tty_termios_baud_rate(termios); 1399 unsigned long fref = 100000000, fuart = baud * 16; 1400 unsigned long w = BIT(15) - 1; 1401 unsigned long m, n; 1402 u32 reg; 1403 1404 /* Gracefully handle the B0 case: fall back to B9600 */ 1405 fuart = fuart ? fuart : 9600 * 16; 1406 1407 /* Get Fuart closer to Fref */ 1408 fuart *= rounddown_pow_of_two(fref / fuart); 1409 1410 /* 1411 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1412 * dividers must be adjusted. 1413 * 1414 * uartclk = (m / n) * 100 MHz, where m <= n 1415 */ 1416 rational_best_approximation(fuart, fref, w, w, &m, &n); 1417 p->uartclk = fuart; 1418 1419 /* Reset the clock */ 1420 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1421 writel(reg, p->membase + BYT_PRV_CLK); 1422 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1423 writel(reg, p->membase + BYT_PRV_CLK); 1424 1425 p->status &= ~UPSTAT_AUTOCTS; 1426 if (termios->c_cflag & CRTSCTS) 1427 p->status |= UPSTAT_AUTOCTS; 1428 1429 serial8250_do_set_termios(p, termios, old); 1430} 1431 1432static bool byt_dma_filter(struct dma_chan *chan, void *param) 1433{ 1434 struct dw_dma_slave *dws = param; 1435 1436 if (dws->dma_dev != chan->device->dev) 1437 return false; 1438 1439 chan->private = dws; 1440 return true; 1441} 1442 1443static int 1444byt_serial_setup(struct serial_private *priv, 1445 const struct pciserial_board *board, 1446 struct uart_8250_port *port, int idx) 1447{ 1448 struct pci_dev *pdev = priv->dev; 1449 struct device *dev = port->port.dev; 1450 struct uart_8250_dma *dma; 1451 struct dw_dma_slave *tx_param, *rx_param; 1452 struct pci_dev *dma_dev; 1453 int ret; 1454 1455 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1456 if (!dma) 1457 return -ENOMEM; 1458 1459 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1460 if (!tx_param) 1461 return -ENOMEM; 1462 1463 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1464 if (!rx_param) 1465 return -ENOMEM; 1466 1467 switch (pdev->device) { 1468 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1469 case PCI_DEVICE_ID_INTEL_BSW_UART1: 1470 case PCI_DEVICE_ID_INTEL_BDW_UART1: 1471 rx_param->src_id = 3; 1472 tx_param->dst_id = 2; 1473 break; 1474 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1475 case PCI_DEVICE_ID_INTEL_BSW_UART2: 1476 case PCI_DEVICE_ID_INTEL_BDW_UART2: 1477 rx_param->src_id = 5; 1478 tx_param->dst_id = 4; 1479 break; 1480 default: 1481 return -EINVAL; 1482 } 1483 1484 rx_param->src_master = 1; 1485 rx_param->dst_master = 0; 1486 1487 dma->rxconf.src_maxburst = 16; 1488 1489 tx_param->src_master = 1; 1490 tx_param->dst_master = 0; 1491 1492 dma->txconf.dst_maxburst = 16; 1493 1494 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 1495 rx_param->dma_dev = &dma_dev->dev; 1496 tx_param->dma_dev = &dma_dev->dev; 1497 1498 dma->fn = byt_dma_filter; 1499 dma->rx_param = rx_param; 1500 dma->tx_param = tx_param; 1501 1502 ret = pci_default_setup(priv, board, port, idx); 1503 port->port.iotype = UPIO_MEM; 1504 port->port.type = PORT_16550A; 1505 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1506 port->port.set_termios = byt_set_termios; 1507 port->port.fifosize = 64; 1508 port->tx_loadsz = 64; 1509 port->dma = dma; 1510 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1511 1512 /* Disable Tx counter interrupts */ 1513 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1514 1515 return ret; 1516} 1517 1518static int 1519pci_omegapci_setup(struct serial_private *priv, 1520 const struct pciserial_board *board, 1521 struct uart_8250_port *port, int idx) 1522{ 1523 return setup_port(priv, port, 2, idx * 8, 0); 1524} 1525 1526static int 1527pci_brcm_trumanage_setup(struct serial_private *priv, 1528 const struct pciserial_board *board, 1529 struct uart_8250_port *port, int idx) 1530{ 1531 int ret = pci_default_setup(priv, board, port, idx); 1532 1533 port->port.type = PORT_BRCM_TRUMANAGE; 1534 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1535 return ret; 1536} 1537 1538/* RTS will control by MCR if this bit is 0 */ 1539#define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1540/* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1541#define FINTEK_RTS_INVERT BIT(5) 1542 1543/* We should do proper H/W transceiver setting before change to RS485 mode */ 1544static int pci_fintek_rs485_config(struct uart_port *port, 1545 struct serial_rs485 *rs485) 1546{ 1547 u8 setting; 1548 u8 *index = (u8 *) port->private_data; 1549 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev, 1550 dev); 1551 1552 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1553 1554 if (!rs485) 1555 rs485 = &port->rs485; 1556 else if (rs485->flags & SER_RS485_ENABLED) 1557 memset(rs485->padding, 0, sizeof(rs485->padding)); 1558 else 1559 memset(rs485, 0, sizeof(*rs485)); 1560 1561 /* F81504/508/512 not support RTS delay before or after send */ 1562 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1563 1564 if (rs485->flags & SER_RS485_ENABLED) { 1565 /* Enable RTS H/W control mode */ 1566 setting |= FINTEK_RTS_CONTROL_BY_HW; 1567 1568 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1569 /* RTS driving high on TX */ 1570 setting &= ~FINTEK_RTS_INVERT; 1571 } else { 1572 /* RTS driving low on TX */ 1573 setting |= FINTEK_RTS_INVERT; 1574 } 1575 1576 rs485->delay_rts_after_send = 0; 1577 rs485->delay_rts_before_send = 0; 1578 } else { 1579 /* Disable RTS H/W control mode */ 1580 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1581 } 1582 1583 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1584 1585 if (rs485 != &port->rs485) 1586 port->rs485 = *rs485; 1587 1588 return 0; 1589} 1590 1591static int pci_fintek_setup(struct serial_private *priv, 1592 const struct pciserial_board *board, 1593 struct uart_8250_port *port, int idx) 1594{ 1595 struct pci_dev *pdev = priv->dev; 1596 u8 *data; 1597 u8 config_base; 1598 u16 iobase; 1599 1600 config_base = 0x40 + 0x08 * idx; 1601 1602 /* Get the io address from configuration space */ 1603 pci_read_config_word(pdev, config_base + 4, &iobase); 1604 1605 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1606 1607 port->port.iotype = UPIO_PORT; 1608 port->port.iobase = iobase; 1609 port->port.rs485_config = pci_fintek_rs485_config; 1610 1611 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1612 if (!data) 1613 return -ENOMEM; 1614 1615 /* preserve index in PCI configuration space */ 1616 *data = idx; 1617 port->port.private_data = data; 1618 1619 return 0; 1620} 1621 1622static int pci_fintek_init(struct pci_dev *dev) 1623{ 1624 unsigned long iobase; 1625 u32 max_port, i; 1626 u32 bar_data[3]; 1627 u8 config_base; 1628 struct serial_private *priv = pci_get_drvdata(dev); 1629 struct uart_8250_port *port; 1630 1631 switch (dev->device) { 1632 case 0x1104: /* 4 ports */ 1633 case 0x1108: /* 8 ports */ 1634 max_port = dev->device & 0xff; 1635 break; 1636 case 0x1112: /* 12 ports */ 1637 max_port = 12; 1638 break; 1639 default: 1640 return -EINVAL; 1641 } 1642 1643 /* Get the io address dispatch from the BIOS */ 1644 pci_read_config_dword(dev, 0x24, &bar_data[0]); 1645 pci_read_config_dword(dev, 0x20, &bar_data[1]); 1646 pci_read_config_dword(dev, 0x1c, &bar_data[2]); 1647 1648 for (i = 0; i < max_port; ++i) { 1649 /* UART0 configuration offset start from 0x40 */ 1650 config_base = 0x40 + 0x08 * i; 1651 1652 /* Calculate Real IO Port */ 1653 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1654 1655 /* Enable UART I/O port */ 1656 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1657 1658 /* Select 128-byte FIFO and 8x FIFO threshold */ 1659 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1660 1661 /* LSB UART */ 1662 pci_write_config_byte(dev, config_base + 0x04, 1663 (u8)(iobase & 0xff)); 1664 1665 /* MSB UART */ 1666 pci_write_config_byte(dev, config_base + 0x05, 1667 (u8)((iobase & 0xff00) >> 8)); 1668 1669 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1670 1671 if (priv) { 1672 /* re-apply RS232/485 mode when 1673 * pciserial_resume_ports() 1674 */ 1675 port = serial8250_get_port(priv->line[i]); 1676 pci_fintek_rs485_config(&port->port, NULL); 1677 } else { 1678 /* First init without port data 1679 * force init to RS232 Mode 1680 */ 1681 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1682 } 1683 } 1684 1685 return max_port; 1686} 1687 1688static int skip_tx_en_setup(struct serial_private *priv, 1689 const struct pciserial_board *board, 1690 struct uart_8250_port *port, int idx) 1691{ 1692 port->port.flags |= UPF_NO_TXEN_TEST; 1693 dev_dbg(&priv->dev->dev, 1694 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1695 priv->dev->vendor, priv->dev->device, 1696 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1697 1698 return pci_default_setup(priv, board, port, idx); 1699} 1700 1701static void kt_handle_break(struct uart_port *p) 1702{ 1703 struct uart_8250_port *up = up_to_u8250p(p); 1704 /* 1705 * On receipt of a BI, serial device in Intel ME (Intel 1706 * management engine) needs to have its fifos cleared for sane 1707 * SOL (Serial Over Lan) output. 1708 */ 1709 serial8250_clear_and_reinit_fifos(up); 1710} 1711 1712static unsigned int kt_serial_in(struct uart_port *p, int offset) 1713{ 1714 struct uart_8250_port *up = up_to_u8250p(p); 1715 unsigned int val; 1716 1717 /* 1718 * When the Intel ME (management engine) gets reset its serial 1719 * port registers could return 0 momentarily. Functions like 1720 * serial8250_console_write, read and save the IER, perform 1721 * some operation and then restore it. In order to avoid 1722 * setting IER register inadvertently to 0, if the value read 1723 * is 0, double check with ier value in uart_8250_port and use 1724 * that instead. up->ier should be the same value as what is 1725 * currently configured. 1726 */ 1727 val = inb(p->iobase + offset); 1728 if (offset == UART_IER) { 1729 if (val == 0) 1730 val = up->ier; 1731 } 1732 return val; 1733} 1734 1735static int kt_serial_setup(struct serial_private *priv, 1736 const struct pciserial_board *board, 1737 struct uart_8250_port *port, int idx) 1738{ 1739 port->port.flags |= UPF_BUG_THRE; 1740 port->port.serial_in = kt_serial_in; 1741 port->port.handle_break = kt_handle_break; 1742 return skip_tx_en_setup(priv, board, port, idx); 1743} 1744 1745static int pci_eg20t_init(struct pci_dev *dev) 1746{ 1747#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1748 return -ENODEV; 1749#else 1750 return 0; 1751#endif 1752} 1753 1754#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 1755#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 1756 1757static int 1758pci_xr17c154_setup(struct serial_private *priv, 1759 const struct pciserial_board *board, 1760 struct uart_8250_port *port, int idx) 1761{ 1762 port->port.flags |= UPF_EXAR_EFR; 1763 return pci_default_setup(priv, board, port, idx); 1764} 1765 1766static inline int 1767xr17v35x_has_slave(struct serial_private *priv) 1768{ 1769 const int dev_id = priv->dev->device; 1770 1771 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) || 1772 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358)); 1773} 1774 1775static int 1776pci_xr17v35x_setup(struct serial_private *priv, 1777 const struct pciserial_board *board, 1778 struct uart_8250_port *port, int idx) 1779{ 1780 u8 __iomem *p; 1781 1782 p = pci_ioremap_bar(priv->dev, 0); 1783 if (p == NULL) 1784 return -ENOMEM; 1785 1786 port->port.flags |= UPF_EXAR_EFR; 1787 1788 /* 1789 * Setup the uart clock for the devices on expansion slot to 1790 * half the clock speed of the main chip (which is 125MHz) 1791 */ 1792 if (xr17v35x_has_slave(priv) && idx >= 8) 1793 port->port.uartclk = (7812500 * 16 / 2); 1794 1795 /* 1796 * Setup Multipurpose Input/Output pins. 1797 */ 1798 if (idx == 0) { 1799 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1800 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1801 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1802 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1803 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1804 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1805 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1806 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1807 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1808 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1809 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1810 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1811 } 1812 writeb(0x00, p + UART_EXAR_8XMODE); 1813 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1814 writeb(128, p + UART_EXAR_TXTRG); 1815 writeb(128, p + UART_EXAR_RXTRG); 1816 iounmap(p); 1817 1818 return pci_default_setup(priv, board, port, idx); 1819} 1820 1821#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1822#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1823#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1824#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1825 1826static int 1827pci_fastcom335_setup(struct serial_private *priv, 1828 const struct pciserial_board *board, 1829 struct uart_8250_port *port, int idx) 1830{ 1831 u8 __iomem *p; 1832 1833 p = pci_ioremap_bar(priv->dev, 0); 1834 if (p == NULL) 1835 return -ENOMEM; 1836 1837 port->port.flags |= UPF_EXAR_EFR; 1838 1839 /* 1840 * Setup Multipurpose Input/Output pins. 1841 */ 1842 if (idx == 0) { 1843 switch (priv->dev->device) { 1844 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1845 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1846 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1847 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1848 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1849 break; 1850 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1851 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1852 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1853 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1854 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1855 break; 1856 } 1857 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1858 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1859 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1860 } 1861 writeb(0x00, p + UART_EXAR_8XMODE); 1862 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1863 writeb(32, p + UART_EXAR_TXTRG); 1864 writeb(32, p + UART_EXAR_RXTRG); 1865 iounmap(p); 1866 1867 return pci_default_setup(priv, board, port, idx); 1868} 1869 1870static int 1871pci_wch_ch353_setup(struct serial_private *priv, 1872 const struct pciserial_board *board, 1873 struct uart_8250_port *port, int idx) 1874{ 1875 port->port.flags |= UPF_FIXED_TYPE; 1876 port->port.type = PORT_16550A; 1877 return pci_default_setup(priv, board, port, idx); 1878} 1879 1880static int 1881pci_wch_ch38x_setup(struct serial_private *priv, 1882 const struct pciserial_board *board, 1883 struct uart_8250_port *port, int idx) 1884{ 1885 port->port.flags |= UPF_FIXED_TYPE; 1886 port->port.type = PORT_16850; 1887 return pci_default_setup(priv, board, port, idx); 1888} 1889 1890#define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1891#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1892#define PCI_DEVICE_ID_OCTPRO 0x0001 1893#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1894#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1895#define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1896#define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1897#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1898#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1899#define PCI_VENDOR_ID_ADVANTECH 0x13fe 1900#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1901#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1902#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1903#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1904#define PCI_DEVICE_ID_TITAN_200I 0x8028 1905#define PCI_DEVICE_ID_TITAN_400I 0x8048 1906#define PCI_DEVICE_ID_TITAN_800I 0x8088 1907#define PCI_DEVICE_ID_TITAN_800EH 0xA007 1908#define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1909#define PCI_DEVICE_ID_TITAN_400EH 0xA009 1910#define PCI_DEVICE_ID_TITAN_100E 0xA010 1911#define PCI_DEVICE_ID_TITAN_200E 0xA012 1912#define PCI_DEVICE_ID_TITAN_400E 0xA013 1913#define PCI_DEVICE_ID_TITAN_800E 0xA014 1914#define PCI_DEVICE_ID_TITAN_200EI 0xA016 1915#define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1916#define PCI_DEVICE_ID_TITAN_200V3 0xA306 1917#define PCI_DEVICE_ID_TITAN_400V3 0xA310 1918#define PCI_DEVICE_ID_TITAN_410V3 0xA312 1919#define PCI_DEVICE_ID_TITAN_800V3 0xA314 1920#define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1921#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1922#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1923#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1924#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1925#define PCI_VENDOR_ID_WCH 0x4348 1926#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1927#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1928#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1929#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1930#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1931#define PCI_VENDOR_ID_AGESTAR 0x5372 1932#define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1933#define PCI_VENDOR_ID_ASIX 0x9710 1934#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1935#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1936#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1937#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1938#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1939#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 1940 1941#define PCI_VENDOR_ID_SUNIX 0x1fd4 1942#define PCI_DEVICE_ID_SUNIX_1999 0x1999 1943 1944#define PCIE_VENDOR_ID_WCH 0x1c00 1945#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1946#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1947#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1948 1949#define PCI_VENDOR_ID_PERICOM 0x12D8 1950#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1951#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1952#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1953#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1954 1955/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1956#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1957#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1958 1959/* 1960 * Master list of serial port init/setup/exit quirks. 1961 * This does not describe the general nature of the port. 1962 * (ie, baud base, number and location of ports, etc) 1963 * 1964 * This list is ordered alphabetically by vendor then device. 1965 * Specific entries must come before more generic entries. 1966 */ 1967static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1968 /* 1969 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1970 */ 1971 { 1972 .vendor = PCI_VENDOR_ID_AMCC, 1973 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1974 .subvendor = PCI_ANY_ID, 1975 .subdevice = PCI_ANY_ID, 1976 .setup = addidata_apci7800_setup, 1977 }, 1978 /* 1979 * AFAVLAB cards - these may be called via parport_serial 1980 * It is not clear whether this applies to all products. 1981 */ 1982 { 1983 .vendor = PCI_VENDOR_ID_AFAVLAB, 1984 .device = PCI_ANY_ID, 1985 .subvendor = PCI_ANY_ID, 1986 .subdevice = PCI_ANY_ID, 1987 .setup = afavlab_setup, 1988 }, 1989 /* 1990 * HP Diva 1991 */ 1992 { 1993 .vendor = PCI_VENDOR_ID_HP, 1994 .device = PCI_DEVICE_ID_HP_DIVA, 1995 .subvendor = PCI_ANY_ID, 1996 .subdevice = PCI_ANY_ID, 1997 .init = pci_hp_diva_init, 1998 .setup = pci_hp_diva_setup, 1999 }, 2000 /* 2001 * Intel 2002 */ 2003 { 2004 .vendor = PCI_VENDOR_ID_INTEL, 2005 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2006 .subvendor = 0xe4bf, 2007 .subdevice = PCI_ANY_ID, 2008 .init = pci_inteli960ni_init, 2009 .setup = pci_default_setup, 2010 }, 2011 { 2012 .vendor = PCI_VENDOR_ID_INTEL, 2013 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2014 .subvendor = PCI_ANY_ID, 2015 .subdevice = PCI_ANY_ID, 2016 .setup = skip_tx_en_setup, 2017 }, 2018 { 2019 .vendor = PCI_VENDOR_ID_INTEL, 2020 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2021 .subvendor = PCI_ANY_ID, 2022 .subdevice = PCI_ANY_ID, 2023 .setup = skip_tx_en_setup, 2024 }, 2025 { 2026 .vendor = PCI_VENDOR_ID_INTEL, 2027 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .setup = skip_tx_en_setup, 2031 }, 2032 { 2033 .vendor = PCI_VENDOR_ID_INTEL, 2034 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2035 .subvendor = PCI_ANY_ID, 2036 .subdevice = PCI_ANY_ID, 2037 .setup = ce4100_serial_setup, 2038 }, 2039 { 2040 .vendor = PCI_VENDOR_ID_INTEL, 2041 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2042 .subvendor = PCI_ANY_ID, 2043 .subdevice = PCI_ANY_ID, 2044 .setup = kt_serial_setup, 2045 }, 2046 { 2047 .vendor = PCI_VENDOR_ID_INTEL, 2048 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 2049 .subvendor = PCI_ANY_ID, 2050 .subdevice = PCI_ANY_ID, 2051 .setup = byt_serial_setup, 2052 }, 2053 { 2054 .vendor = PCI_VENDOR_ID_INTEL, 2055 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 2056 .subvendor = PCI_ANY_ID, 2057 .subdevice = PCI_ANY_ID, 2058 .setup = byt_serial_setup, 2059 }, 2060 { 2061 .vendor = PCI_VENDOR_ID_INTEL, 2062 .device = PCI_DEVICE_ID_INTEL_BSW_UART1, 2063 .subvendor = PCI_ANY_ID, 2064 .subdevice = PCI_ANY_ID, 2065 .setup = byt_serial_setup, 2066 }, 2067 { 2068 .vendor = PCI_VENDOR_ID_INTEL, 2069 .device = PCI_DEVICE_ID_INTEL_BSW_UART2, 2070 .subvendor = PCI_ANY_ID, 2071 .subdevice = PCI_ANY_ID, 2072 .setup = byt_serial_setup, 2073 }, 2074 { 2075 .vendor = PCI_VENDOR_ID_INTEL, 2076 .device = PCI_DEVICE_ID_INTEL_BDW_UART1, 2077 .subvendor = PCI_ANY_ID, 2078 .subdevice = PCI_ANY_ID, 2079 .setup = byt_serial_setup, 2080 }, 2081 { 2082 .vendor = PCI_VENDOR_ID_INTEL, 2083 .device = PCI_DEVICE_ID_INTEL_BDW_UART2, 2084 .subvendor = PCI_ANY_ID, 2085 .subdevice = PCI_ANY_ID, 2086 .setup = byt_serial_setup, 2087 }, 2088 /* 2089 * ITE 2090 */ 2091 { 2092 .vendor = PCI_VENDOR_ID_ITE, 2093 .device = PCI_DEVICE_ID_ITE_8872, 2094 .subvendor = PCI_ANY_ID, 2095 .subdevice = PCI_ANY_ID, 2096 .init = pci_ite887x_init, 2097 .setup = pci_default_setup, 2098 .exit = pci_ite887x_exit, 2099 }, 2100 /* 2101 * National Instruments 2102 */ 2103 { 2104 .vendor = PCI_VENDOR_ID_NI, 2105 .device = PCI_DEVICE_ID_NI_PCI23216, 2106 .subvendor = PCI_ANY_ID, 2107 .subdevice = PCI_ANY_ID, 2108 .init = pci_ni8420_init, 2109 .setup = pci_default_setup, 2110 .exit = pci_ni8420_exit, 2111 }, 2112 { 2113 .vendor = PCI_VENDOR_ID_NI, 2114 .device = PCI_DEVICE_ID_NI_PCI2328, 2115 .subvendor = PCI_ANY_ID, 2116 .subdevice = PCI_ANY_ID, 2117 .init = pci_ni8420_init, 2118 .setup = pci_default_setup, 2119 .exit = pci_ni8420_exit, 2120 }, 2121 { 2122 .vendor = PCI_VENDOR_ID_NI, 2123 .device = PCI_DEVICE_ID_NI_PCI2324, 2124 .subvendor = PCI_ANY_ID, 2125 .subdevice = PCI_ANY_ID, 2126 .init = pci_ni8420_init, 2127 .setup = pci_default_setup, 2128 .exit = pci_ni8420_exit, 2129 }, 2130 { 2131 .vendor = PCI_VENDOR_ID_NI, 2132 .device = PCI_DEVICE_ID_NI_PCI2322, 2133 .subvendor = PCI_ANY_ID, 2134 .subdevice = PCI_ANY_ID, 2135 .init = pci_ni8420_init, 2136 .setup = pci_default_setup, 2137 .exit = pci_ni8420_exit, 2138 }, 2139 { 2140 .vendor = PCI_VENDOR_ID_NI, 2141 .device = PCI_DEVICE_ID_NI_PCI2324I, 2142 .subvendor = PCI_ANY_ID, 2143 .subdevice = PCI_ANY_ID, 2144 .init = pci_ni8420_init, 2145 .setup = pci_default_setup, 2146 .exit = pci_ni8420_exit, 2147 }, 2148 { 2149 .vendor = PCI_VENDOR_ID_NI, 2150 .device = PCI_DEVICE_ID_NI_PCI2322I, 2151 .subvendor = PCI_ANY_ID, 2152 .subdevice = PCI_ANY_ID, 2153 .init = pci_ni8420_init, 2154 .setup = pci_default_setup, 2155 .exit = pci_ni8420_exit, 2156 }, 2157 { 2158 .vendor = PCI_VENDOR_ID_NI, 2159 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2160 .subvendor = PCI_ANY_ID, 2161 .subdevice = PCI_ANY_ID, 2162 .init = pci_ni8420_init, 2163 .setup = pci_default_setup, 2164 .exit = pci_ni8420_exit, 2165 }, 2166 { 2167 .vendor = PCI_VENDOR_ID_NI, 2168 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2169 .subvendor = PCI_ANY_ID, 2170 .subdevice = PCI_ANY_ID, 2171 .init = pci_ni8420_init, 2172 .setup = pci_default_setup, 2173 .exit = pci_ni8420_exit, 2174 }, 2175 { 2176 .vendor = PCI_VENDOR_ID_NI, 2177 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2178 .subvendor = PCI_ANY_ID, 2179 .subdevice = PCI_ANY_ID, 2180 .init = pci_ni8420_init, 2181 .setup = pci_default_setup, 2182 .exit = pci_ni8420_exit, 2183 }, 2184 { 2185 .vendor = PCI_VENDOR_ID_NI, 2186 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2187 .subvendor = PCI_ANY_ID, 2188 .subdevice = PCI_ANY_ID, 2189 .init = pci_ni8420_init, 2190 .setup = pci_default_setup, 2191 .exit = pci_ni8420_exit, 2192 }, 2193 { 2194 .vendor = PCI_VENDOR_ID_NI, 2195 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2196 .subvendor = PCI_ANY_ID, 2197 .subdevice = PCI_ANY_ID, 2198 .init = pci_ni8420_init, 2199 .setup = pci_default_setup, 2200 .exit = pci_ni8420_exit, 2201 }, 2202 { 2203 .vendor = PCI_VENDOR_ID_NI, 2204 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2205 .subvendor = PCI_ANY_ID, 2206 .subdevice = PCI_ANY_ID, 2207 .init = pci_ni8420_init, 2208 .setup = pci_default_setup, 2209 .exit = pci_ni8420_exit, 2210 }, 2211 { 2212 .vendor = PCI_VENDOR_ID_NI, 2213 .device = PCI_ANY_ID, 2214 .subvendor = PCI_ANY_ID, 2215 .subdevice = PCI_ANY_ID, 2216 .init = pci_ni8430_init, 2217 .setup = pci_ni8430_setup, 2218 .exit = pci_ni8430_exit, 2219 }, 2220 /* Quatech */ 2221 { 2222 .vendor = PCI_VENDOR_ID_QUATECH, 2223 .device = PCI_ANY_ID, 2224 .subvendor = PCI_ANY_ID, 2225 .subdevice = PCI_ANY_ID, 2226 .init = pci_quatech_init, 2227 .setup = pci_quatech_setup, 2228 .exit = pci_quatech_exit, 2229 }, 2230 /* 2231 * Panacom 2232 */ 2233 { 2234 .vendor = PCI_VENDOR_ID_PANACOM, 2235 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2236 .subvendor = PCI_ANY_ID, 2237 .subdevice = PCI_ANY_ID, 2238 .init = pci_plx9050_init, 2239 .setup = pci_default_setup, 2240 .exit = pci_plx9050_exit, 2241 }, 2242 { 2243 .vendor = PCI_VENDOR_ID_PANACOM, 2244 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2245 .subvendor = PCI_ANY_ID, 2246 .subdevice = PCI_ANY_ID, 2247 .init = pci_plx9050_init, 2248 .setup = pci_default_setup, 2249 .exit = pci_plx9050_exit, 2250 }, 2251 /* 2252 * Pericom 2253 */ 2254 { 2255 .vendor = PCI_VENDOR_ID_PERICOM, 2256 .device = PCI_ANY_ID, 2257 .subvendor = PCI_ANY_ID, 2258 .subdevice = PCI_ANY_ID, 2259 .setup = pci_pericom_setup, 2260 }, 2261 /* 2262 * PLX 2263 */ 2264 { 2265 .vendor = PCI_VENDOR_ID_PLX, 2266 .device = PCI_DEVICE_ID_PLX_9050, 2267 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2268 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2269 .init = pci_plx9050_init, 2270 .setup = pci_default_setup, 2271 .exit = pci_plx9050_exit, 2272 }, 2273 { 2274 .vendor = PCI_VENDOR_ID_PLX, 2275 .device = PCI_DEVICE_ID_PLX_9050, 2276 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2277 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2278 .init = pci_plx9050_init, 2279 .setup = pci_default_setup, 2280 .exit = pci_plx9050_exit, 2281 }, 2282 { 2283 .vendor = PCI_VENDOR_ID_PLX, 2284 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2285 .subvendor = PCI_VENDOR_ID_PLX, 2286 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2287 .init = pci_plx9050_init, 2288 .setup = pci_default_setup, 2289 .exit = pci_plx9050_exit, 2290 }, 2291 /* 2292 * SBS Technologies, Inc., PMC-OCTALPRO 232 2293 */ 2294 { 2295 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2296 .device = PCI_DEVICE_ID_OCTPRO, 2297 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2298 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2299 .init = sbs_init, 2300 .setup = sbs_setup, 2301 .exit = sbs_exit, 2302 }, 2303 /* 2304 * SBS Technologies, Inc., PMC-OCTALPRO 422 2305 */ 2306 { 2307 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2308 .device = PCI_DEVICE_ID_OCTPRO, 2309 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2310 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2311 .init = sbs_init, 2312 .setup = sbs_setup, 2313 .exit = sbs_exit, 2314 }, 2315 /* 2316 * SBS Technologies, Inc., P-Octal 232 2317 */ 2318 { 2319 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2320 .device = PCI_DEVICE_ID_OCTPRO, 2321 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2322 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2323 .init = sbs_init, 2324 .setup = sbs_setup, 2325 .exit = sbs_exit, 2326 }, 2327 /* 2328 * SBS Technologies, Inc., P-Octal 422 2329 */ 2330 { 2331 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2332 .device = PCI_DEVICE_ID_OCTPRO, 2333 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2334 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2335 .init = sbs_init, 2336 .setup = sbs_setup, 2337 .exit = sbs_exit, 2338 }, 2339 /* 2340 * SIIG cards - these may be called via parport_serial 2341 */ 2342 { 2343 .vendor = PCI_VENDOR_ID_SIIG, 2344 .device = PCI_ANY_ID, 2345 .subvendor = PCI_ANY_ID, 2346 .subdevice = PCI_ANY_ID, 2347 .init = pci_siig_init, 2348 .setup = pci_siig_setup, 2349 }, 2350 /* 2351 * Titan cards 2352 */ 2353 { 2354 .vendor = PCI_VENDOR_ID_TITAN, 2355 .device = PCI_DEVICE_ID_TITAN_400L, 2356 .subvendor = PCI_ANY_ID, 2357 .subdevice = PCI_ANY_ID, 2358 .setup = titan_400l_800l_setup, 2359 }, 2360 { 2361 .vendor = PCI_VENDOR_ID_TITAN, 2362 .device = PCI_DEVICE_ID_TITAN_800L, 2363 .subvendor = PCI_ANY_ID, 2364 .subdevice = PCI_ANY_ID, 2365 .setup = titan_400l_800l_setup, 2366 }, 2367 /* 2368 * Timedia cards 2369 */ 2370 { 2371 .vendor = PCI_VENDOR_ID_TIMEDIA, 2372 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2373 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2374 .subdevice = PCI_ANY_ID, 2375 .probe = pci_timedia_probe, 2376 .init = pci_timedia_init, 2377 .setup = pci_timedia_setup, 2378 }, 2379 { 2380 .vendor = PCI_VENDOR_ID_TIMEDIA, 2381 .device = PCI_ANY_ID, 2382 .subvendor = PCI_ANY_ID, 2383 .subdevice = PCI_ANY_ID, 2384 .setup = pci_timedia_setup, 2385 }, 2386 /* 2387 * SUNIX (Timedia) cards 2388 * Do not "probe" for these cards as there is at least one combination 2389 * card that should be handled by parport_pc that doesn't match the 2390 * rule in pci_timedia_probe. 2391 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2392 * There are some boards with part number SER5037AL that report 2393 * subdevice ID 0x0002. 2394 */ 2395 { 2396 .vendor = PCI_VENDOR_ID_SUNIX, 2397 .device = PCI_DEVICE_ID_SUNIX_1999, 2398 .subvendor = PCI_VENDOR_ID_SUNIX, 2399 .subdevice = PCI_ANY_ID, 2400 .init = pci_timedia_init, 2401 .setup = pci_timedia_setup, 2402 }, 2403 /* 2404 * Exar cards 2405 */ 2406 { 2407 .vendor = PCI_VENDOR_ID_EXAR, 2408 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2409 .subvendor = PCI_ANY_ID, 2410 .subdevice = PCI_ANY_ID, 2411 .setup = pci_xr17c154_setup, 2412 }, 2413 { 2414 .vendor = PCI_VENDOR_ID_EXAR, 2415 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2416 .subvendor = PCI_ANY_ID, 2417 .subdevice = PCI_ANY_ID, 2418 .setup = pci_xr17c154_setup, 2419 }, 2420 { 2421 .vendor = PCI_VENDOR_ID_EXAR, 2422 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2423 .subvendor = PCI_ANY_ID, 2424 .subdevice = PCI_ANY_ID, 2425 .setup = pci_xr17c154_setup, 2426 }, 2427 { 2428 .vendor = PCI_VENDOR_ID_EXAR, 2429 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2430 .subvendor = PCI_ANY_ID, 2431 .subdevice = PCI_ANY_ID, 2432 .setup = pci_xr17v35x_setup, 2433 }, 2434 { 2435 .vendor = PCI_VENDOR_ID_EXAR, 2436 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2437 .subvendor = PCI_ANY_ID, 2438 .subdevice = PCI_ANY_ID, 2439 .setup = pci_xr17v35x_setup, 2440 }, 2441 { 2442 .vendor = PCI_VENDOR_ID_EXAR, 2443 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2444 .subvendor = PCI_ANY_ID, 2445 .subdevice = PCI_ANY_ID, 2446 .setup = pci_xr17v35x_setup, 2447 }, 2448 { 2449 .vendor = PCI_VENDOR_ID_EXAR, 2450 .device = PCI_DEVICE_ID_EXAR_XR17V4358, 2451 .subvendor = PCI_ANY_ID, 2452 .subdevice = PCI_ANY_ID, 2453 .setup = pci_xr17v35x_setup, 2454 }, 2455 { 2456 .vendor = PCI_VENDOR_ID_EXAR, 2457 .device = PCI_DEVICE_ID_EXAR_XR17V8358, 2458 .subvendor = PCI_ANY_ID, 2459 .subdevice = PCI_ANY_ID, 2460 .setup = pci_xr17v35x_setup, 2461 }, 2462 /* 2463 * Xircom cards 2464 */ 2465 { 2466 .vendor = PCI_VENDOR_ID_XIRCOM, 2467 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2468 .subvendor = PCI_ANY_ID, 2469 .subdevice = PCI_ANY_ID, 2470 .init = pci_xircom_init, 2471 .setup = pci_default_setup, 2472 }, 2473 /* 2474 * Netmos cards - these may be called via parport_serial 2475 */ 2476 { 2477 .vendor = PCI_VENDOR_ID_NETMOS, 2478 .device = PCI_ANY_ID, 2479 .subvendor = PCI_ANY_ID, 2480 .subdevice = PCI_ANY_ID, 2481 .init = pci_netmos_init, 2482 .setup = pci_netmos_9900_setup, 2483 }, 2484 /* 2485 * EndRun Technologies 2486 */ 2487 { 2488 .vendor = PCI_VENDOR_ID_ENDRUN, 2489 .device = PCI_ANY_ID, 2490 .subvendor = PCI_ANY_ID, 2491 .subdevice = PCI_ANY_ID, 2492 .init = pci_endrun_init, 2493 .setup = pci_default_setup, 2494 }, 2495 /* 2496 * For Oxford Semiconductor Tornado based devices 2497 */ 2498 { 2499 .vendor = PCI_VENDOR_ID_OXSEMI, 2500 .device = PCI_ANY_ID, 2501 .subvendor = PCI_ANY_ID, 2502 .subdevice = PCI_ANY_ID, 2503 .init = pci_oxsemi_tornado_init, 2504 .setup = pci_default_setup, 2505 }, 2506 { 2507 .vendor = PCI_VENDOR_ID_MAINPINE, 2508 .device = PCI_ANY_ID, 2509 .subvendor = PCI_ANY_ID, 2510 .subdevice = PCI_ANY_ID, 2511 .init = pci_oxsemi_tornado_init, 2512 .setup = pci_default_setup, 2513 }, 2514 { 2515 .vendor = PCI_VENDOR_ID_DIGI, 2516 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2517 .subvendor = PCI_SUBVENDOR_ID_IBM, 2518 .subdevice = PCI_ANY_ID, 2519 .init = pci_oxsemi_tornado_init, 2520 .setup = pci_default_setup, 2521 }, 2522 { 2523 .vendor = PCI_VENDOR_ID_INTEL, 2524 .device = 0x8811, 2525 .subvendor = PCI_ANY_ID, 2526 .subdevice = PCI_ANY_ID, 2527 .init = pci_eg20t_init, 2528 .setup = pci_default_setup, 2529 }, 2530 { 2531 .vendor = PCI_VENDOR_ID_INTEL, 2532 .device = 0x8812, 2533 .subvendor = PCI_ANY_ID, 2534 .subdevice = PCI_ANY_ID, 2535 .init = pci_eg20t_init, 2536 .setup = pci_default_setup, 2537 }, 2538 { 2539 .vendor = PCI_VENDOR_ID_INTEL, 2540 .device = 0x8813, 2541 .subvendor = PCI_ANY_ID, 2542 .subdevice = PCI_ANY_ID, 2543 .init = pci_eg20t_init, 2544 .setup = pci_default_setup, 2545 }, 2546 { 2547 .vendor = PCI_VENDOR_ID_INTEL, 2548 .device = 0x8814, 2549 .subvendor = PCI_ANY_ID, 2550 .subdevice = PCI_ANY_ID, 2551 .init = pci_eg20t_init, 2552 .setup = pci_default_setup, 2553 }, 2554 { 2555 .vendor = 0x10DB, 2556 .device = 0x8027, 2557 .subvendor = PCI_ANY_ID, 2558 .subdevice = PCI_ANY_ID, 2559 .init = pci_eg20t_init, 2560 .setup = pci_default_setup, 2561 }, 2562 { 2563 .vendor = 0x10DB, 2564 .device = 0x8028, 2565 .subvendor = PCI_ANY_ID, 2566 .subdevice = PCI_ANY_ID, 2567 .init = pci_eg20t_init, 2568 .setup = pci_default_setup, 2569 }, 2570 { 2571 .vendor = 0x10DB, 2572 .device = 0x8029, 2573 .subvendor = PCI_ANY_ID, 2574 .subdevice = PCI_ANY_ID, 2575 .init = pci_eg20t_init, 2576 .setup = pci_default_setup, 2577 }, 2578 { 2579 .vendor = 0x10DB, 2580 .device = 0x800C, 2581 .subvendor = PCI_ANY_ID, 2582 .subdevice = PCI_ANY_ID, 2583 .init = pci_eg20t_init, 2584 .setup = pci_default_setup, 2585 }, 2586 { 2587 .vendor = 0x10DB, 2588 .device = 0x800D, 2589 .subvendor = PCI_ANY_ID, 2590 .subdevice = PCI_ANY_ID, 2591 .init = pci_eg20t_init, 2592 .setup = pci_default_setup, 2593 }, 2594 /* 2595 * Cronyx Omega PCI (PLX-chip based) 2596 */ 2597 { 2598 .vendor = PCI_VENDOR_ID_PLX, 2599 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2600 .subvendor = PCI_ANY_ID, 2601 .subdevice = PCI_ANY_ID, 2602 .setup = pci_omegapci_setup, 2603 }, 2604 /* WCH CH353 1S1P card (16550 clone) */ 2605 { 2606 .vendor = PCI_VENDOR_ID_WCH, 2607 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2608 .subvendor = PCI_ANY_ID, 2609 .subdevice = PCI_ANY_ID, 2610 .setup = pci_wch_ch353_setup, 2611 }, 2612 /* WCH CH353 2S1P card (16550 clone) */ 2613 { 2614 .vendor = PCI_VENDOR_ID_WCH, 2615 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2616 .subvendor = PCI_ANY_ID, 2617 .subdevice = PCI_ANY_ID, 2618 .setup = pci_wch_ch353_setup, 2619 }, 2620 /* WCH CH353 4S card (16550 clone) */ 2621 { 2622 .vendor = PCI_VENDOR_ID_WCH, 2623 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2624 .subvendor = PCI_ANY_ID, 2625 .subdevice = PCI_ANY_ID, 2626 .setup = pci_wch_ch353_setup, 2627 }, 2628 /* WCH CH353 2S1PF card (16550 clone) */ 2629 { 2630 .vendor = PCI_VENDOR_ID_WCH, 2631 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2632 .subvendor = PCI_ANY_ID, 2633 .subdevice = PCI_ANY_ID, 2634 .setup = pci_wch_ch353_setup, 2635 }, 2636 /* WCH CH352 2S card (16550 clone) */ 2637 { 2638 .vendor = PCI_VENDOR_ID_WCH, 2639 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2640 .subvendor = PCI_ANY_ID, 2641 .subdevice = PCI_ANY_ID, 2642 .setup = pci_wch_ch353_setup, 2643 }, 2644 /* WCH CH382 2S card (16850 clone) */ 2645 { 2646 .vendor = PCIE_VENDOR_ID_WCH, 2647 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2648 .subvendor = PCI_ANY_ID, 2649 .subdevice = PCI_ANY_ID, 2650 .setup = pci_wch_ch38x_setup, 2651 }, 2652 /* WCH CH382 2S1P card (16850 clone) */ 2653 { 2654 .vendor = PCIE_VENDOR_ID_WCH, 2655 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2656 .subvendor = PCI_ANY_ID, 2657 .subdevice = PCI_ANY_ID, 2658 .setup = pci_wch_ch38x_setup, 2659 }, 2660 /* WCH CH384 4S card (16850 clone) */ 2661 { 2662 .vendor = PCIE_VENDOR_ID_WCH, 2663 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2664 .subvendor = PCI_ANY_ID, 2665 .subdevice = PCI_ANY_ID, 2666 .setup = pci_wch_ch38x_setup, 2667 }, 2668 /* 2669 * ASIX devices with FIFO bug 2670 */ 2671 { 2672 .vendor = PCI_VENDOR_ID_ASIX, 2673 .device = PCI_ANY_ID, 2674 .subvendor = PCI_ANY_ID, 2675 .subdevice = PCI_ANY_ID, 2676 .setup = pci_asix_setup, 2677 }, 2678 /* 2679 * Commtech, Inc. Fastcom adapters 2680 * 2681 */ 2682 { 2683 .vendor = PCI_VENDOR_ID_COMMTECH, 2684 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2685 .subvendor = PCI_ANY_ID, 2686 .subdevice = PCI_ANY_ID, 2687 .setup = pci_fastcom335_setup, 2688 }, 2689 { 2690 .vendor = PCI_VENDOR_ID_COMMTECH, 2691 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2692 .subvendor = PCI_ANY_ID, 2693 .subdevice = PCI_ANY_ID, 2694 .setup = pci_fastcom335_setup, 2695 }, 2696 { 2697 .vendor = PCI_VENDOR_ID_COMMTECH, 2698 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2699 .subvendor = PCI_ANY_ID, 2700 .subdevice = PCI_ANY_ID, 2701 .setup = pci_fastcom335_setup, 2702 }, 2703 { 2704 .vendor = PCI_VENDOR_ID_COMMTECH, 2705 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2706 .subvendor = PCI_ANY_ID, 2707 .subdevice = PCI_ANY_ID, 2708 .setup = pci_fastcom335_setup, 2709 }, 2710 { 2711 .vendor = PCI_VENDOR_ID_COMMTECH, 2712 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2713 .subvendor = PCI_ANY_ID, 2714 .subdevice = PCI_ANY_ID, 2715 .setup = pci_xr17v35x_setup, 2716 }, 2717 { 2718 .vendor = PCI_VENDOR_ID_COMMTECH, 2719 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2720 .subvendor = PCI_ANY_ID, 2721 .subdevice = PCI_ANY_ID, 2722 .setup = pci_xr17v35x_setup, 2723 }, 2724 { 2725 .vendor = PCI_VENDOR_ID_COMMTECH, 2726 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2727 .subvendor = PCI_ANY_ID, 2728 .subdevice = PCI_ANY_ID, 2729 .setup = pci_xr17v35x_setup, 2730 }, 2731 /* 2732 * Broadcom TruManage (NetXtreme) 2733 */ 2734 { 2735 .vendor = PCI_VENDOR_ID_BROADCOM, 2736 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2737 .subvendor = PCI_ANY_ID, 2738 .subdevice = PCI_ANY_ID, 2739 .setup = pci_brcm_trumanage_setup, 2740 }, 2741 { 2742 .vendor = 0x1c29, 2743 .device = 0x1104, 2744 .subvendor = PCI_ANY_ID, 2745 .subdevice = PCI_ANY_ID, 2746 .setup = pci_fintek_setup, 2747 .init = pci_fintek_init, 2748 }, 2749 { 2750 .vendor = 0x1c29, 2751 .device = 0x1108, 2752 .subvendor = PCI_ANY_ID, 2753 .subdevice = PCI_ANY_ID, 2754 .setup = pci_fintek_setup, 2755 .init = pci_fintek_init, 2756 }, 2757 { 2758 .vendor = 0x1c29, 2759 .device = 0x1112, 2760 .subvendor = PCI_ANY_ID, 2761 .subdevice = PCI_ANY_ID, 2762 .setup = pci_fintek_setup, 2763 .init = pci_fintek_init, 2764 }, 2765 2766 /* 2767 * Default "match everything" terminator entry 2768 */ 2769 { 2770 .vendor = PCI_ANY_ID, 2771 .device = PCI_ANY_ID, 2772 .subvendor = PCI_ANY_ID, 2773 .subdevice = PCI_ANY_ID, 2774 .setup = pci_default_setup, 2775 } 2776}; 2777 2778static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2779{ 2780 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2781} 2782 2783static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2784{ 2785 struct pci_serial_quirk *quirk; 2786 2787 for (quirk = pci_serial_quirks; ; quirk++) 2788 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2789 quirk_id_matches(quirk->device, dev->device) && 2790 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2791 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2792 break; 2793 return quirk; 2794} 2795 2796static inline int get_pci_irq(struct pci_dev *dev, 2797 const struct pciserial_board *board) 2798{ 2799 if (board->flags & FL_NOIRQ) 2800 return 0; 2801 else 2802 return dev->irq; 2803} 2804 2805/* 2806 * This is the configuration table for all of the PCI serial boards 2807 * which we support. It is directly indexed by the pci_board_num_t enum 2808 * value, which is encoded in the pci_device_id PCI probe table's 2809 * driver_data member. 2810 * 2811 * The makeup of these names are: 2812 * pbn_bn{_bt}_n_baud{_offsetinhex} 2813 * 2814 * bn = PCI BAR number 2815 * bt = Index using PCI BARs 2816 * n = number of serial ports 2817 * baud = baud rate 2818 * offsetinhex = offset for each sequential port (in hex) 2819 * 2820 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2821 * 2822 * Please note: in theory if n = 1, _bt infix should make no difference. 2823 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2824 */ 2825enum pci_board_num_t { 2826 pbn_default = 0, 2827 2828 pbn_b0_1_115200, 2829 pbn_b0_2_115200, 2830 pbn_b0_4_115200, 2831 pbn_b0_5_115200, 2832 pbn_b0_8_115200, 2833 2834 pbn_b0_1_921600, 2835 pbn_b0_2_921600, 2836 pbn_b0_4_921600, 2837 2838 pbn_b0_2_1130000, 2839 2840 pbn_b0_4_1152000, 2841 2842 pbn_b0_2_1152000_200, 2843 pbn_b0_4_1152000_200, 2844 pbn_b0_8_1152000_200, 2845 2846 pbn_b0_2_1843200, 2847 pbn_b0_4_1843200, 2848 2849 pbn_b0_2_1843200_200, 2850 pbn_b0_4_1843200_200, 2851 pbn_b0_8_1843200_200, 2852 2853 pbn_b0_1_4000000, 2854 2855 pbn_b0_bt_1_115200, 2856 pbn_b0_bt_2_115200, 2857 pbn_b0_bt_4_115200, 2858 pbn_b0_bt_8_115200, 2859 2860 pbn_b0_bt_1_460800, 2861 pbn_b0_bt_2_460800, 2862 pbn_b0_bt_4_460800, 2863 2864 pbn_b0_bt_1_921600, 2865 pbn_b0_bt_2_921600, 2866 pbn_b0_bt_4_921600, 2867 pbn_b0_bt_8_921600, 2868 2869 pbn_b1_1_115200, 2870 pbn_b1_2_115200, 2871 pbn_b1_4_115200, 2872 pbn_b1_8_115200, 2873 pbn_b1_16_115200, 2874 2875 pbn_b1_1_921600, 2876 pbn_b1_2_921600, 2877 pbn_b1_4_921600, 2878 pbn_b1_8_921600, 2879 2880 pbn_b1_2_1250000, 2881 2882 pbn_b1_bt_1_115200, 2883 pbn_b1_bt_2_115200, 2884 pbn_b1_bt_4_115200, 2885 2886 pbn_b1_bt_2_921600, 2887 2888 pbn_b1_1_1382400, 2889 pbn_b1_2_1382400, 2890 pbn_b1_4_1382400, 2891 pbn_b1_8_1382400, 2892 2893 pbn_b2_1_115200, 2894 pbn_b2_2_115200, 2895 pbn_b2_4_115200, 2896 pbn_b2_8_115200, 2897 2898 pbn_b2_1_460800, 2899 pbn_b2_4_460800, 2900 pbn_b2_8_460800, 2901 pbn_b2_16_460800, 2902 2903 pbn_b2_1_921600, 2904 pbn_b2_4_921600, 2905 pbn_b2_8_921600, 2906 2907 pbn_b2_8_1152000, 2908 2909 pbn_b2_bt_1_115200, 2910 pbn_b2_bt_2_115200, 2911 pbn_b2_bt_4_115200, 2912 2913 pbn_b2_bt_2_921600, 2914 pbn_b2_bt_4_921600, 2915 2916 pbn_b3_2_115200, 2917 pbn_b3_4_115200, 2918 pbn_b3_8_115200, 2919 2920 pbn_b4_bt_2_921600, 2921 pbn_b4_bt_4_921600, 2922 pbn_b4_bt_8_921600, 2923 2924 /* 2925 * Board-specific versions. 2926 */ 2927 pbn_panacom, 2928 pbn_panacom2, 2929 pbn_panacom4, 2930 pbn_plx_romulus, 2931 pbn_endrun_2_4000000, 2932 pbn_oxsemi, 2933 pbn_oxsemi_1_4000000, 2934 pbn_oxsemi_2_4000000, 2935 pbn_oxsemi_4_4000000, 2936 pbn_oxsemi_8_4000000, 2937 pbn_intel_i960, 2938 pbn_sgi_ioc3, 2939 pbn_computone_4, 2940 pbn_computone_6, 2941 pbn_computone_8, 2942 pbn_sbsxrsio, 2943 pbn_exar_XR17C152, 2944 pbn_exar_XR17C154, 2945 pbn_exar_XR17C158, 2946 pbn_exar_XR17V352, 2947 pbn_exar_XR17V354, 2948 pbn_exar_XR17V358, 2949 pbn_exar_XR17V4358, 2950 pbn_exar_XR17V8358, 2951 pbn_exar_ibm_saturn, 2952 pbn_pasemi_1682M, 2953 pbn_ni8430_2, 2954 pbn_ni8430_4, 2955 pbn_ni8430_8, 2956 pbn_ni8430_16, 2957 pbn_ADDIDATA_PCIe_1_3906250, 2958 pbn_ADDIDATA_PCIe_2_3906250, 2959 pbn_ADDIDATA_PCIe_4_3906250, 2960 pbn_ADDIDATA_PCIe_8_3906250, 2961 pbn_ce4100_1_115200, 2962 pbn_byt, 2963 pbn_qrk, 2964 pbn_omegapci, 2965 pbn_NETMOS9900_2s_115200, 2966 pbn_brcm_trumanage, 2967 pbn_fintek_4, 2968 pbn_fintek_8, 2969 pbn_fintek_12, 2970 pbn_wch382_2, 2971 pbn_wch384_4, 2972 pbn_pericom_PI7C9X7951, 2973 pbn_pericom_PI7C9X7952, 2974 pbn_pericom_PI7C9X7954, 2975 pbn_pericom_PI7C9X7958, 2976}; 2977 2978/* 2979 * uart_offset - the space between channels 2980 * reg_shift - describes how the UART registers are mapped 2981 * to PCI memory by the card. 2982 * For example IER register on SBS, Inc. PMC-OctPro is located at 2983 * offset 0x10 from the UART base, while UART_IER is defined as 1 2984 * in include/linux/serial_reg.h, 2985 * see first lines of serial_in() and serial_out() in 8250.c 2986*/ 2987 2988static struct pciserial_board pci_boards[] = { 2989 [pbn_default] = { 2990 .flags = FL_BASE0, 2991 .num_ports = 1, 2992 .base_baud = 115200, 2993 .uart_offset = 8, 2994 }, 2995 [pbn_b0_1_115200] = { 2996 .flags = FL_BASE0, 2997 .num_ports = 1, 2998 .base_baud = 115200, 2999 .uart_offset = 8, 3000 }, 3001 [pbn_b0_2_115200] = { 3002 .flags = FL_BASE0, 3003 .num_ports = 2, 3004 .base_baud = 115200, 3005 .uart_offset = 8, 3006 }, 3007 [pbn_b0_4_115200] = { 3008 .flags = FL_BASE0, 3009 .num_ports = 4, 3010 .base_baud = 115200, 3011 .uart_offset = 8, 3012 }, 3013 [pbn_b0_5_115200] = { 3014 .flags = FL_BASE0, 3015 .num_ports = 5, 3016 .base_baud = 115200, 3017 .uart_offset = 8, 3018 }, 3019 [pbn_b0_8_115200] = { 3020 .flags = FL_BASE0, 3021 .num_ports = 8, 3022 .base_baud = 115200, 3023 .uart_offset = 8, 3024 }, 3025 [pbn_b0_1_921600] = { 3026 .flags = FL_BASE0, 3027 .num_ports = 1, 3028 .base_baud = 921600, 3029 .uart_offset = 8, 3030 }, 3031 [pbn_b0_2_921600] = { 3032 .flags = FL_BASE0, 3033 .num_ports = 2, 3034 .base_baud = 921600, 3035 .uart_offset = 8, 3036 }, 3037 [pbn_b0_4_921600] = { 3038 .flags = FL_BASE0, 3039 .num_ports = 4, 3040 .base_baud = 921600, 3041 .uart_offset = 8, 3042 }, 3043 3044 [pbn_b0_2_1130000] = { 3045 .flags = FL_BASE0, 3046 .num_ports = 2, 3047 .base_baud = 1130000, 3048 .uart_offset = 8, 3049 }, 3050 3051 [pbn_b0_4_1152000] = { 3052 .flags = FL_BASE0, 3053 .num_ports = 4, 3054 .base_baud = 1152000, 3055 .uart_offset = 8, 3056 }, 3057 3058 [pbn_b0_2_1152000_200] = { 3059 .flags = FL_BASE0, 3060 .num_ports = 2, 3061 .base_baud = 1152000, 3062 .uart_offset = 0x200, 3063 }, 3064 3065 [pbn_b0_4_1152000_200] = { 3066 .flags = FL_BASE0, 3067 .num_ports = 4, 3068 .base_baud = 1152000, 3069 .uart_offset = 0x200, 3070 }, 3071 3072 [pbn_b0_8_1152000_200] = { 3073 .flags = FL_BASE0, 3074 .num_ports = 8, 3075 .base_baud = 1152000, 3076 .uart_offset = 0x200, 3077 }, 3078 3079 [pbn_b0_2_1843200] = { 3080 .flags = FL_BASE0, 3081 .num_ports = 2, 3082 .base_baud = 1843200, 3083 .uart_offset = 8, 3084 }, 3085 [pbn_b0_4_1843200] = { 3086 .flags = FL_BASE0, 3087 .num_ports = 4, 3088 .base_baud = 1843200, 3089 .uart_offset = 8, 3090 }, 3091 3092 [pbn_b0_2_1843200_200] = { 3093 .flags = FL_BASE0, 3094 .num_ports = 2, 3095 .base_baud = 1843200, 3096 .uart_offset = 0x200, 3097 }, 3098 [pbn_b0_4_1843200_200] = { 3099 .flags = FL_BASE0, 3100 .num_ports = 4, 3101 .base_baud = 1843200, 3102 .uart_offset = 0x200, 3103 }, 3104 [pbn_b0_8_1843200_200] = { 3105 .flags = FL_BASE0, 3106 .num_ports = 8, 3107 .base_baud = 1843200, 3108 .uart_offset = 0x200, 3109 }, 3110 [pbn_b0_1_4000000] = { 3111 .flags = FL_BASE0, 3112 .num_ports = 1, 3113 .base_baud = 4000000, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b0_bt_1_115200] = { 3118 .flags = FL_BASE0|FL_BASE_BARS, 3119 .num_ports = 1, 3120 .base_baud = 115200, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b0_bt_2_115200] = { 3124 .flags = FL_BASE0|FL_BASE_BARS, 3125 .num_ports = 2, 3126 .base_baud = 115200, 3127 .uart_offset = 8, 3128 }, 3129 [pbn_b0_bt_4_115200] = { 3130 .flags = FL_BASE0|FL_BASE_BARS, 3131 .num_ports = 4, 3132 .base_baud = 115200, 3133 .uart_offset = 8, 3134 }, 3135 [pbn_b0_bt_8_115200] = { 3136 .flags = FL_BASE0|FL_BASE_BARS, 3137 .num_ports = 8, 3138 .base_baud = 115200, 3139 .uart_offset = 8, 3140 }, 3141 3142 [pbn_b0_bt_1_460800] = { 3143 .flags = FL_BASE0|FL_BASE_BARS, 3144 .num_ports = 1, 3145 .base_baud = 460800, 3146 .uart_offset = 8, 3147 }, 3148 [pbn_b0_bt_2_460800] = { 3149 .flags = FL_BASE0|FL_BASE_BARS, 3150 .num_ports = 2, 3151 .base_baud = 460800, 3152 .uart_offset = 8, 3153 }, 3154 [pbn_b0_bt_4_460800] = { 3155 .flags = FL_BASE0|FL_BASE_BARS, 3156 .num_ports = 4, 3157 .base_baud = 460800, 3158 .uart_offset = 8, 3159 }, 3160 3161 [pbn_b0_bt_1_921600] = { 3162 .flags = FL_BASE0|FL_BASE_BARS, 3163 .num_ports = 1, 3164 .base_baud = 921600, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b0_bt_2_921600] = { 3168 .flags = FL_BASE0|FL_BASE_BARS, 3169 .num_ports = 2, 3170 .base_baud = 921600, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b0_bt_4_921600] = { 3174 .flags = FL_BASE0|FL_BASE_BARS, 3175 .num_ports = 4, 3176 .base_baud = 921600, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b0_bt_8_921600] = { 3180 .flags = FL_BASE0|FL_BASE_BARS, 3181 .num_ports = 8, 3182 .base_baud = 921600, 3183 .uart_offset = 8, 3184 }, 3185 3186 [pbn_b1_1_115200] = { 3187 .flags = FL_BASE1, 3188 .num_ports = 1, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 [pbn_b1_2_115200] = { 3193 .flags = FL_BASE1, 3194 .num_ports = 2, 3195 .base_baud = 115200, 3196 .uart_offset = 8, 3197 }, 3198 [pbn_b1_4_115200] = { 3199 .flags = FL_BASE1, 3200 .num_ports = 4, 3201 .base_baud = 115200, 3202 .uart_offset = 8, 3203 }, 3204 [pbn_b1_8_115200] = { 3205 .flags = FL_BASE1, 3206 .num_ports = 8, 3207 .base_baud = 115200, 3208 .uart_offset = 8, 3209 }, 3210 [pbn_b1_16_115200] = { 3211 .flags = FL_BASE1, 3212 .num_ports = 16, 3213 .base_baud = 115200, 3214 .uart_offset = 8, 3215 }, 3216 3217 [pbn_b1_1_921600] = { 3218 .flags = FL_BASE1, 3219 .num_ports = 1, 3220 .base_baud = 921600, 3221 .uart_offset = 8, 3222 }, 3223 [pbn_b1_2_921600] = { 3224 .flags = FL_BASE1, 3225 .num_ports = 2, 3226 .base_baud = 921600, 3227 .uart_offset = 8, 3228 }, 3229 [pbn_b1_4_921600] = { 3230 .flags = FL_BASE1, 3231 .num_ports = 4, 3232 .base_baud = 921600, 3233 .uart_offset = 8, 3234 }, 3235 [pbn_b1_8_921600] = { 3236 .flags = FL_BASE1, 3237 .num_ports = 8, 3238 .base_baud = 921600, 3239 .uart_offset = 8, 3240 }, 3241 [pbn_b1_2_1250000] = { 3242 .flags = FL_BASE1, 3243 .num_ports = 2, 3244 .base_baud = 1250000, 3245 .uart_offset = 8, 3246 }, 3247 3248 [pbn_b1_bt_1_115200] = { 3249 .flags = FL_BASE1|FL_BASE_BARS, 3250 .num_ports = 1, 3251 .base_baud = 115200, 3252 .uart_offset = 8, 3253 }, 3254 [pbn_b1_bt_2_115200] = { 3255 .flags = FL_BASE1|FL_BASE_BARS, 3256 .num_ports = 2, 3257 .base_baud = 115200, 3258 .uart_offset = 8, 3259 }, 3260 [pbn_b1_bt_4_115200] = { 3261 .flags = FL_BASE1|FL_BASE_BARS, 3262 .num_ports = 4, 3263 .base_baud = 115200, 3264 .uart_offset = 8, 3265 }, 3266 3267 [pbn_b1_bt_2_921600] = { 3268 .flags = FL_BASE1|FL_BASE_BARS, 3269 .num_ports = 2, 3270 .base_baud = 921600, 3271 .uart_offset = 8, 3272 }, 3273 3274 [pbn_b1_1_1382400] = { 3275 .flags = FL_BASE1, 3276 .num_ports = 1, 3277 .base_baud = 1382400, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b1_2_1382400] = { 3281 .flags = FL_BASE1, 3282 .num_ports = 2, 3283 .base_baud = 1382400, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b1_4_1382400] = { 3287 .flags = FL_BASE1, 3288 .num_ports = 4, 3289 .base_baud = 1382400, 3290 .uart_offset = 8, 3291 }, 3292 [pbn_b1_8_1382400] = { 3293 .flags = FL_BASE1, 3294 .num_ports = 8, 3295 .base_baud = 1382400, 3296 .uart_offset = 8, 3297 }, 3298 3299 [pbn_b2_1_115200] = { 3300 .flags = FL_BASE2, 3301 .num_ports = 1, 3302 .base_baud = 115200, 3303 .uart_offset = 8, 3304 }, 3305 [pbn_b2_2_115200] = { 3306 .flags = FL_BASE2, 3307 .num_ports = 2, 3308 .base_baud = 115200, 3309 .uart_offset = 8, 3310 }, 3311 [pbn_b2_4_115200] = { 3312 .flags = FL_BASE2, 3313 .num_ports = 4, 3314 .base_baud = 115200, 3315 .uart_offset = 8, 3316 }, 3317 [pbn_b2_8_115200] = { 3318 .flags = FL_BASE2, 3319 .num_ports = 8, 3320 .base_baud = 115200, 3321 .uart_offset = 8, 3322 }, 3323 3324 [pbn_b2_1_460800] = { 3325 .flags = FL_BASE2, 3326 .num_ports = 1, 3327 .base_baud = 460800, 3328 .uart_offset = 8, 3329 }, 3330 [pbn_b2_4_460800] = { 3331 .flags = FL_BASE2, 3332 .num_ports = 4, 3333 .base_baud = 460800, 3334 .uart_offset = 8, 3335 }, 3336 [pbn_b2_8_460800] = { 3337 .flags = FL_BASE2, 3338 .num_ports = 8, 3339 .base_baud = 460800, 3340 .uart_offset = 8, 3341 }, 3342 [pbn_b2_16_460800] = { 3343 .flags = FL_BASE2, 3344 .num_ports = 16, 3345 .base_baud = 460800, 3346 .uart_offset = 8, 3347 }, 3348 3349 [pbn_b2_1_921600] = { 3350 .flags = FL_BASE2, 3351 .num_ports = 1, 3352 .base_baud = 921600, 3353 .uart_offset = 8, 3354 }, 3355 [pbn_b2_4_921600] = { 3356 .flags = FL_BASE2, 3357 .num_ports = 4, 3358 .base_baud = 921600, 3359 .uart_offset = 8, 3360 }, 3361 [pbn_b2_8_921600] = { 3362 .flags = FL_BASE2, 3363 .num_ports = 8, 3364 .base_baud = 921600, 3365 .uart_offset = 8, 3366 }, 3367 3368 [pbn_b2_8_1152000] = { 3369 .flags = FL_BASE2, 3370 .num_ports = 8, 3371 .base_baud = 1152000, 3372 .uart_offset = 8, 3373 }, 3374 3375 [pbn_b2_bt_1_115200] = { 3376 .flags = FL_BASE2|FL_BASE_BARS, 3377 .num_ports = 1, 3378 .base_baud = 115200, 3379 .uart_offset = 8, 3380 }, 3381 [pbn_b2_bt_2_115200] = { 3382 .flags = FL_BASE2|FL_BASE_BARS, 3383 .num_ports = 2, 3384 .base_baud = 115200, 3385 .uart_offset = 8, 3386 }, 3387 [pbn_b2_bt_4_115200] = { 3388 .flags = FL_BASE2|FL_BASE_BARS, 3389 .num_ports = 4, 3390 .base_baud = 115200, 3391 .uart_offset = 8, 3392 }, 3393 3394 [pbn_b2_bt_2_921600] = { 3395 .flags = FL_BASE2|FL_BASE_BARS, 3396 .num_ports = 2, 3397 .base_baud = 921600, 3398 .uart_offset = 8, 3399 }, 3400 [pbn_b2_bt_4_921600] = { 3401 .flags = FL_BASE2|FL_BASE_BARS, 3402 .num_ports = 4, 3403 .base_baud = 921600, 3404 .uart_offset = 8, 3405 }, 3406 3407 [pbn_b3_2_115200] = { 3408 .flags = FL_BASE3, 3409 .num_ports = 2, 3410 .base_baud = 115200, 3411 .uart_offset = 8, 3412 }, 3413 [pbn_b3_4_115200] = { 3414 .flags = FL_BASE3, 3415 .num_ports = 4, 3416 .base_baud = 115200, 3417 .uart_offset = 8, 3418 }, 3419 [pbn_b3_8_115200] = { 3420 .flags = FL_BASE3, 3421 .num_ports = 8, 3422 .base_baud = 115200, 3423 .uart_offset = 8, 3424 }, 3425 3426 [pbn_b4_bt_2_921600] = { 3427 .flags = FL_BASE4, 3428 .num_ports = 2, 3429 .base_baud = 921600, 3430 .uart_offset = 8, 3431 }, 3432 [pbn_b4_bt_4_921600] = { 3433 .flags = FL_BASE4, 3434 .num_ports = 4, 3435 .base_baud = 921600, 3436 .uart_offset = 8, 3437 }, 3438 [pbn_b4_bt_8_921600] = { 3439 .flags = FL_BASE4, 3440 .num_ports = 8, 3441 .base_baud = 921600, 3442 .uart_offset = 8, 3443 }, 3444 3445 /* 3446 * Entries following this are board-specific. 3447 */ 3448 3449 /* 3450 * Panacom - IOMEM 3451 */ 3452 [pbn_panacom] = { 3453 .flags = FL_BASE2, 3454 .num_ports = 2, 3455 .base_baud = 921600, 3456 .uart_offset = 0x400, 3457 .reg_shift = 7, 3458 }, 3459 [pbn_panacom2] = { 3460 .flags = FL_BASE2|FL_BASE_BARS, 3461 .num_ports = 2, 3462 .base_baud = 921600, 3463 .uart_offset = 0x400, 3464 .reg_shift = 7, 3465 }, 3466 [pbn_panacom4] = { 3467 .flags = FL_BASE2|FL_BASE_BARS, 3468 .num_ports = 4, 3469 .base_baud = 921600, 3470 .uart_offset = 0x400, 3471 .reg_shift = 7, 3472 }, 3473 3474 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3475 [pbn_plx_romulus] = { 3476 .flags = FL_BASE2, 3477 .num_ports = 4, 3478 .base_baud = 921600, 3479 .uart_offset = 8 << 2, 3480 .reg_shift = 2, 3481 .first_offset = 0x03, 3482 }, 3483 3484 /* 3485 * EndRun Technologies 3486 * Uses the size of PCI Base region 0 to 3487 * signal now many ports are available 3488 * 2 port 952 Uart support 3489 */ 3490 [pbn_endrun_2_4000000] = { 3491 .flags = FL_BASE0, 3492 .num_ports = 2, 3493 .base_baud = 4000000, 3494 .uart_offset = 0x200, 3495 .first_offset = 0x1000, 3496 }, 3497 3498 /* 3499 * This board uses the size of PCI Base region 0 to 3500 * signal now many ports are available 3501 */ 3502 [pbn_oxsemi] = { 3503 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3504 .num_ports = 32, 3505 .base_baud = 115200, 3506 .uart_offset = 8, 3507 }, 3508 [pbn_oxsemi_1_4000000] = { 3509 .flags = FL_BASE0, 3510 .num_ports = 1, 3511 .base_baud = 4000000, 3512 .uart_offset = 0x200, 3513 .first_offset = 0x1000, 3514 }, 3515 [pbn_oxsemi_2_4000000] = { 3516 .flags = FL_BASE0, 3517 .num_ports = 2, 3518 .base_baud = 4000000, 3519 .uart_offset = 0x200, 3520 .first_offset = 0x1000, 3521 }, 3522 [pbn_oxsemi_4_4000000] = { 3523 .flags = FL_BASE0, 3524 .num_ports = 4, 3525 .base_baud = 4000000, 3526 .uart_offset = 0x200, 3527 .first_offset = 0x1000, 3528 }, 3529 [pbn_oxsemi_8_4000000] = { 3530 .flags = FL_BASE0, 3531 .num_ports = 8, 3532 .base_baud = 4000000, 3533 .uart_offset = 0x200, 3534 .first_offset = 0x1000, 3535 }, 3536 3537 3538 /* 3539 * EKF addition for i960 Boards form EKF with serial port. 3540 * Max 256 ports. 3541 */ 3542 [pbn_intel_i960] = { 3543 .flags = FL_BASE0, 3544 .num_ports = 32, 3545 .base_baud = 921600, 3546 .uart_offset = 8 << 2, 3547 .reg_shift = 2, 3548 .first_offset = 0x10000, 3549 }, 3550 [pbn_sgi_ioc3] = { 3551 .flags = FL_BASE0|FL_NOIRQ, 3552 .num_ports = 1, 3553 .base_baud = 458333, 3554 .uart_offset = 8, 3555 .reg_shift = 0, 3556 .first_offset = 0x20178, 3557 }, 3558 3559 /* 3560 * Computone - uses IOMEM. 3561 */ 3562 [pbn_computone_4] = { 3563 .flags = FL_BASE0, 3564 .num_ports = 4, 3565 .base_baud = 921600, 3566 .uart_offset = 0x40, 3567 .reg_shift = 2, 3568 .first_offset = 0x200, 3569 }, 3570 [pbn_computone_6] = { 3571 .flags = FL_BASE0, 3572 .num_ports = 6, 3573 .base_baud = 921600, 3574 .uart_offset = 0x40, 3575 .reg_shift = 2, 3576 .first_offset = 0x200, 3577 }, 3578 [pbn_computone_8] = { 3579 .flags = FL_BASE0, 3580 .num_ports = 8, 3581 .base_baud = 921600, 3582 .uart_offset = 0x40, 3583 .reg_shift = 2, 3584 .first_offset = 0x200, 3585 }, 3586 [pbn_sbsxrsio] = { 3587 .flags = FL_BASE0, 3588 .num_ports = 8, 3589 .base_baud = 460800, 3590 .uart_offset = 256, 3591 .reg_shift = 4, 3592 }, 3593 /* 3594 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3595 * Only basic 16550A support. 3596 * XR17C15[24] are not tested, but they should work. 3597 */ 3598 [pbn_exar_XR17C152] = { 3599 .flags = FL_BASE0, 3600 .num_ports = 2, 3601 .base_baud = 921600, 3602 .uart_offset = 0x200, 3603 }, 3604 [pbn_exar_XR17C154] = { 3605 .flags = FL_BASE0, 3606 .num_ports = 4, 3607 .base_baud = 921600, 3608 .uart_offset = 0x200, 3609 }, 3610 [pbn_exar_XR17C158] = { 3611 .flags = FL_BASE0, 3612 .num_ports = 8, 3613 .base_baud = 921600, 3614 .uart_offset = 0x200, 3615 }, 3616 [pbn_exar_XR17V352] = { 3617 .flags = FL_BASE0, 3618 .num_ports = 2, 3619 .base_baud = 7812500, 3620 .uart_offset = 0x400, 3621 .reg_shift = 0, 3622 .first_offset = 0, 3623 }, 3624 [pbn_exar_XR17V354] = { 3625 .flags = FL_BASE0, 3626 .num_ports = 4, 3627 .base_baud = 7812500, 3628 .uart_offset = 0x400, 3629 .reg_shift = 0, 3630 .first_offset = 0, 3631 }, 3632 [pbn_exar_XR17V358] = { 3633 .flags = FL_BASE0, 3634 .num_ports = 8, 3635 .base_baud = 7812500, 3636 .uart_offset = 0x400, 3637 .reg_shift = 0, 3638 .first_offset = 0, 3639 }, 3640 [pbn_exar_XR17V4358] = { 3641 .flags = FL_BASE0, 3642 .num_ports = 12, 3643 .base_baud = 7812500, 3644 .uart_offset = 0x400, 3645 .reg_shift = 0, 3646 .first_offset = 0, 3647 }, 3648 [pbn_exar_XR17V8358] = { 3649 .flags = FL_BASE0, 3650 .num_ports = 16, 3651 .base_baud = 7812500, 3652 .uart_offset = 0x400, 3653 .reg_shift = 0, 3654 .first_offset = 0, 3655 }, 3656 [pbn_exar_ibm_saturn] = { 3657 .flags = FL_BASE0, 3658 .num_ports = 1, 3659 .base_baud = 921600, 3660 .uart_offset = 0x200, 3661 }, 3662 3663 /* 3664 * PA Semi PWRficient PA6T-1682M on-chip UART 3665 */ 3666 [pbn_pasemi_1682M] = { 3667 .flags = FL_BASE0, 3668 .num_ports = 1, 3669 .base_baud = 8333333, 3670 }, 3671 /* 3672 * National Instruments 843x 3673 */ 3674 [pbn_ni8430_16] = { 3675 .flags = FL_BASE0, 3676 .num_ports = 16, 3677 .base_baud = 3686400, 3678 .uart_offset = 0x10, 3679 .first_offset = 0x800, 3680 }, 3681 [pbn_ni8430_8] = { 3682 .flags = FL_BASE0, 3683 .num_ports = 8, 3684 .base_baud = 3686400, 3685 .uart_offset = 0x10, 3686 .first_offset = 0x800, 3687 }, 3688 [pbn_ni8430_4] = { 3689 .flags = FL_BASE0, 3690 .num_ports = 4, 3691 .base_baud = 3686400, 3692 .uart_offset = 0x10, 3693 .first_offset = 0x800, 3694 }, 3695 [pbn_ni8430_2] = { 3696 .flags = FL_BASE0, 3697 .num_ports = 2, 3698 .base_baud = 3686400, 3699 .uart_offset = 0x10, 3700 .first_offset = 0x800, 3701 }, 3702 /* 3703 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3704 */ 3705 [pbn_ADDIDATA_PCIe_1_3906250] = { 3706 .flags = FL_BASE0, 3707 .num_ports = 1, 3708 .base_baud = 3906250, 3709 .uart_offset = 0x200, 3710 .first_offset = 0x1000, 3711 }, 3712 [pbn_ADDIDATA_PCIe_2_3906250] = { 3713 .flags = FL_BASE0, 3714 .num_ports = 2, 3715 .base_baud = 3906250, 3716 .uart_offset = 0x200, 3717 .first_offset = 0x1000, 3718 }, 3719 [pbn_ADDIDATA_PCIe_4_3906250] = { 3720 .flags = FL_BASE0, 3721 .num_ports = 4, 3722 .base_baud = 3906250, 3723 .uart_offset = 0x200, 3724 .first_offset = 0x1000, 3725 }, 3726 [pbn_ADDIDATA_PCIe_8_3906250] = { 3727 .flags = FL_BASE0, 3728 .num_ports = 8, 3729 .base_baud = 3906250, 3730 .uart_offset = 0x200, 3731 .first_offset = 0x1000, 3732 }, 3733 [pbn_ce4100_1_115200] = { 3734 .flags = FL_BASE_BARS, 3735 .num_ports = 2, 3736 .base_baud = 921600, 3737 .reg_shift = 2, 3738 }, 3739 /* 3740 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3741 * but is overridden by byt_set_termios. 3742 */ 3743 [pbn_byt] = { 3744 .flags = FL_BASE0, 3745 .num_ports = 1, 3746 .base_baud = 2764800, 3747 .uart_offset = 0x80, 3748 .reg_shift = 2, 3749 }, 3750 [pbn_qrk] = { 3751 .flags = FL_BASE0, 3752 .num_ports = 1, 3753 .base_baud = 2764800, 3754 .reg_shift = 2, 3755 }, 3756 [pbn_omegapci] = { 3757 .flags = FL_BASE0, 3758 .num_ports = 8, 3759 .base_baud = 115200, 3760 .uart_offset = 0x200, 3761 }, 3762 [pbn_NETMOS9900_2s_115200] = { 3763 .flags = FL_BASE0, 3764 .num_ports = 2, 3765 .base_baud = 115200, 3766 }, 3767 [pbn_brcm_trumanage] = { 3768 .flags = FL_BASE0, 3769 .num_ports = 1, 3770 .reg_shift = 2, 3771 .base_baud = 115200, 3772 }, 3773 [pbn_fintek_4] = { 3774 .num_ports = 4, 3775 .uart_offset = 8, 3776 .base_baud = 115200, 3777 .first_offset = 0x40, 3778 }, 3779 [pbn_fintek_8] = { 3780 .num_ports = 8, 3781 .uart_offset = 8, 3782 .base_baud = 115200, 3783 .first_offset = 0x40, 3784 }, 3785 [pbn_fintek_12] = { 3786 .num_ports = 12, 3787 .uart_offset = 8, 3788 .base_baud = 115200, 3789 .first_offset = 0x40, 3790 }, 3791 [pbn_wch382_2] = { 3792 .flags = FL_BASE0, 3793 .num_ports = 2, 3794 .base_baud = 115200, 3795 .uart_offset = 8, 3796 .first_offset = 0xC0, 3797 }, 3798 [pbn_wch384_4] = { 3799 .flags = FL_BASE0, 3800 .num_ports = 4, 3801 .base_baud = 115200, 3802 .uart_offset = 8, 3803 .first_offset = 0xC0, 3804 }, 3805 /* 3806 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3807 */ 3808 [pbn_pericom_PI7C9X7951] = { 3809 .flags = FL_BASE0, 3810 .num_ports = 1, 3811 .base_baud = 921600, 3812 .uart_offset = 0x8, 3813 }, 3814 [pbn_pericom_PI7C9X7952] = { 3815 .flags = FL_BASE0, 3816 .num_ports = 2, 3817 .base_baud = 921600, 3818 .uart_offset = 0x8, 3819 }, 3820 [pbn_pericom_PI7C9X7954] = { 3821 .flags = FL_BASE0, 3822 .num_ports = 4, 3823 .base_baud = 921600, 3824 .uart_offset = 0x8, 3825 }, 3826 [pbn_pericom_PI7C9X7958] = { 3827 .flags = FL_BASE0, 3828 .num_ports = 8, 3829 .base_baud = 921600, 3830 .uart_offset = 0x8, 3831 }, 3832}; 3833 3834static const struct pci_device_id blacklist[] = { 3835 /* softmodems */ 3836 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3837 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3838 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3839 3840 /* multi-io cards handled by parport_serial */ 3841 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3842 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3843 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3844 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ 3845 3846 /* Intel platforms with MID UART */ 3847 { PCI_VDEVICE(INTEL, 0x081b), }, 3848 { PCI_VDEVICE(INTEL, 0x081c), }, 3849 { PCI_VDEVICE(INTEL, 0x081d), }, 3850 { PCI_VDEVICE(INTEL, 0x1191), }, 3851 { PCI_VDEVICE(INTEL, 0x19d8), }, 3852}; 3853 3854/* 3855 * Given a complete unknown PCI device, try to use some heuristics to 3856 * guess what the configuration might be, based on the pitiful PCI 3857 * serial specs. Returns 0 on success, 1 on failure. 3858 */ 3859static int 3860serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3861{ 3862 const struct pci_device_id *bldev; 3863 int num_iomem, num_port, first_port = -1, i; 3864 3865 /* 3866 * If it is not a communications device or the programming 3867 * interface is greater than 6, give up. 3868 * 3869 * (Should we try to make guesses for multiport serial devices 3870 * later?) 3871 */ 3872 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3873 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3874 (dev->class & 0xff) > 6) 3875 return -ENODEV; 3876 3877 /* 3878 * Do not access blacklisted devices that are known not to 3879 * feature serial ports or are handled by other modules. 3880 */ 3881 for (bldev = blacklist; 3882 bldev < blacklist + ARRAY_SIZE(blacklist); 3883 bldev++) { 3884 if (dev->vendor == bldev->vendor && 3885 dev->device == bldev->device) 3886 return -ENODEV; 3887 } 3888 3889 num_iomem = num_port = 0; 3890 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3891 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3892 num_port++; 3893 if (first_port == -1) 3894 first_port = i; 3895 } 3896 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3897 num_iomem++; 3898 } 3899 3900 /* 3901 * If there is 1 or 0 iomem regions, and exactly one port, 3902 * use it. We guess the number of ports based on the IO 3903 * region size. 3904 */ 3905 if (num_iomem <= 1 && num_port == 1) { 3906 board->flags = first_port; 3907 board->num_ports = pci_resource_len(dev, first_port) / 8; 3908 return 0; 3909 } 3910 3911 /* 3912 * Now guess if we've got a board which indexes by BARs. 3913 * Each IO BAR should be 8 bytes, and they should follow 3914 * consecutively. 3915 */ 3916 first_port = -1; 3917 num_port = 0; 3918 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3919 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3920 pci_resource_len(dev, i) == 8 && 3921 (first_port == -1 || (first_port + num_port) == i)) { 3922 num_port++; 3923 if (first_port == -1) 3924 first_port = i; 3925 } 3926 } 3927 3928 if (num_port > 1) { 3929 board->flags = first_port | FL_BASE_BARS; 3930 board->num_ports = num_port; 3931 return 0; 3932 } 3933 3934 return -ENODEV; 3935} 3936 3937static inline int 3938serial_pci_matches(const struct pciserial_board *board, 3939 const struct pciserial_board *guessed) 3940{ 3941 return 3942 board->num_ports == guessed->num_ports && 3943 board->base_baud == guessed->base_baud && 3944 board->uart_offset == guessed->uart_offset && 3945 board->reg_shift == guessed->reg_shift && 3946 board->first_offset == guessed->first_offset; 3947} 3948 3949struct serial_private * 3950pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3951{ 3952 struct uart_8250_port uart; 3953 struct serial_private *priv; 3954 struct pci_serial_quirk *quirk; 3955 int rc, nr_ports, i; 3956 3957 nr_ports = board->num_ports; 3958 3959 /* 3960 * Find an init and setup quirks. 3961 */ 3962 quirk = find_quirk(dev); 3963 3964 /* 3965 * Run the new-style initialization function. 3966 * The initialization function returns: 3967 * <0 - error 3968 * 0 - use board->num_ports 3969 * >0 - number of ports 3970 */ 3971 if (quirk->init) { 3972 rc = quirk->init(dev); 3973 if (rc < 0) { 3974 priv = ERR_PTR(rc); 3975 goto err_out; 3976 } 3977 if (rc) 3978 nr_ports = rc; 3979 } 3980 3981 priv = kzalloc(sizeof(struct serial_private) + 3982 sizeof(unsigned int) * nr_ports, 3983 GFP_KERNEL); 3984 if (!priv) { 3985 priv = ERR_PTR(-ENOMEM); 3986 goto err_deinit; 3987 } 3988 3989 priv->dev = dev; 3990 priv->quirk = quirk; 3991 3992 memset(&uart, 0, sizeof(uart)); 3993 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3994 uart.port.uartclk = board->base_baud * 16; 3995 uart.port.irq = get_pci_irq(dev, board); 3996 uart.port.dev = &dev->dev; 3997 3998 for (i = 0; i < nr_ports; i++) { 3999 if (quirk->setup(priv, board, &uart, i)) 4000 break; 4001 4002 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4003 uart.port.iobase, uart.port.irq, uart.port.iotype); 4004 4005 priv->line[i] = serial8250_register_8250_port(&uart); 4006 if (priv->line[i] < 0) { 4007 dev_err(&dev->dev, 4008 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4009 uart.port.iobase, uart.port.irq, 4010 uart.port.iotype, priv->line[i]); 4011 break; 4012 } 4013 } 4014 priv->nr = i; 4015 return priv; 4016 4017err_deinit: 4018 if (quirk->exit) 4019 quirk->exit(dev); 4020err_out: 4021 return priv; 4022} 4023EXPORT_SYMBOL_GPL(pciserial_init_ports); 4024 4025void pciserial_remove_ports(struct serial_private *priv) 4026{ 4027 struct pci_serial_quirk *quirk; 4028 int i; 4029 4030 for (i = 0; i < priv->nr; i++) 4031 serial8250_unregister_port(priv->line[i]); 4032 4033 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 4034 if (priv->remapped_bar[i]) 4035 iounmap(priv->remapped_bar[i]); 4036 priv->remapped_bar[i] = NULL; 4037 } 4038 4039 /* 4040 * Find the exit quirks. 4041 */ 4042 quirk = find_quirk(priv->dev); 4043 if (quirk->exit) 4044 quirk->exit(priv->dev); 4045 4046 kfree(priv); 4047} 4048EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4049 4050void pciserial_suspend_ports(struct serial_private *priv) 4051{ 4052 int i; 4053 4054 for (i = 0; i < priv->nr; i++) 4055 if (priv->line[i] >= 0) 4056 serial8250_suspend_port(priv->line[i]); 4057 4058 /* 4059 * Ensure that every init quirk is properly torn down 4060 */ 4061 if (priv->quirk->exit) 4062 priv->quirk->exit(priv->dev); 4063} 4064EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4065 4066void pciserial_resume_ports(struct serial_private *priv) 4067{ 4068 int i; 4069 4070 /* 4071 * Ensure that the board is correctly configured. 4072 */ 4073 if (priv->quirk->init) 4074 priv->quirk->init(priv->dev); 4075 4076 for (i = 0; i < priv->nr; i++) 4077 if (priv->line[i] >= 0) 4078 serial8250_resume_port(priv->line[i]); 4079} 4080EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4081 4082/* 4083 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4084 * to the arrangement of serial ports on a PCI card. 4085 */ 4086static int 4087pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4088{ 4089 struct pci_serial_quirk *quirk; 4090 struct serial_private *priv; 4091 const struct pciserial_board *board; 4092 struct pciserial_board tmp; 4093 int rc; 4094 4095 quirk = find_quirk(dev); 4096 if (quirk->probe) { 4097 rc = quirk->probe(dev); 4098 if (rc) 4099 return rc; 4100 } 4101 4102 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4103 dev_err(&dev->dev, "invalid driver_data: %ld\n", 4104 ent->driver_data); 4105 return -EINVAL; 4106 } 4107 4108 board = &pci_boards[ent->driver_data]; 4109 4110 rc = pci_enable_device(dev); 4111 pci_save_state(dev); 4112 if (rc) 4113 return rc; 4114 4115 if (ent->driver_data == pbn_default) { 4116 /* 4117 * Use a copy of the pci_board entry for this; 4118 * avoid changing entries in the table. 4119 */ 4120 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4121 board = &tmp; 4122 4123 /* 4124 * We matched one of our class entries. Try to 4125 * determine the parameters of this board. 4126 */ 4127 rc = serial_pci_guess_board(dev, &tmp); 4128 if (rc) 4129 goto disable; 4130 } else { 4131 /* 4132 * We matched an explicit entry. If we are able to 4133 * detect this boards settings with our heuristic, 4134 * then we no longer need this entry. 4135 */ 4136 memcpy(&tmp, &pci_boards[pbn_default], 4137 sizeof(struct pciserial_board)); 4138 rc = serial_pci_guess_board(dev, &tmp); 4139 if (rc == 0 && serial_pci_matches(board, &tmp)) 4140 moan_device("Redundant entry in serial pci_table.", 4141 dev); 4142 } 4143 4144 priv = pciserial_init_ports(dev, board); 4145 if (!IS_ERR(priv)) { 4146 pci_set_drvdata(dev, priv); 4147 return 0; 4148 } 4149 4150 rc = PTR_ERR(priv); 4151 4152 disable: 4153 pci_disable_device(dev); 4154 return rc; 4155} 4156 4157static void pciserial_remove_one(struct pci_dev *dev) 4158{ 4159 struct serial_private *priv = pci_get_drvdata(dev); 4160 4161 pciserial_remove_ports(priv); 4162 4163 pci_disable_device(dev); 4164} 4165 4166#ifdef CONFIG_PM_SLEEP 4167static int pciserial_suspend_one(struct device *dev) 4168{ 4169 struct pci_dev *pdev = to_pci_dev(dev); 4170 struct serial_private *priv = pci_get_drvdata(pdev); 4171 4172 if (priv) 4173 pciserial_suspend_ports(priv); 4174 4175 return 0; 4176} 4177 4178static int pciserial_resume_one(struct device *dev) 4179{ 4180 struct pci_dev *pdev = to_pci_dev(dev); 4181 struct serial_private *priv = pci_get_drvdata(pdev); 4182 int err; 4183 4184 if (priv) { 4185 /* 4186 * The device may have been disabled. Re-enable it. 4187 */ 4188 err = pci_enable_device(pdev); 4189 /* FIXME: We cannot simply error out here */ 4190 if (err) 4191 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4192 pciserial_resume_ports(priv); 4193 } 4194 return 0; 4195} 4196#endif 4197 4198static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4199 pciserial_resume_one); 4200 4201static struct pci_device_id serial_pci_tbl[] = { 4202 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4203 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4204 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4205 pbn_b2_8_921600 }, 4206 /* Advantech also use 0x3618 and 0xf618 */ 4207 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4208 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4209 pbn_b0_4_921600 }, 4210 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4211 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4212 pbn_b0_4_921600 }, 4213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4214 PCI_SUBVENDOR_ID_CONNECT_TECH, 4215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4216 pbn_b1_8_1382400 }, 4217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4218 PCI_SUBVENDOR_ID_CONNECT_TECH, 4219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4220 pbn_b1_4_1382400 }, 4221 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4222 PCI_SUBVENDOR_ID_CONNECT_TECH, 4223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4224 pbn_b1_2_1382400 }, 4225 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4226 PCI_SUBVENDOR_ID_CONNECT_TECH, 4227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4228 pbn_b1_8_1382400 }, 4229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4230 PCI_SUBVENDOR_ID_CONNECT_TECH, 4231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4232 pbn_b1_4_1382400 }, 4233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4234 PCI_SUBVENDOR_ID_CONNECT_TECH, 4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4236 pbn_b1_2_1382400 }, 4237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4238 PCI_SUBVENDOR_ID_CONNECT_TECH, 4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4240 pbn_b1_8_921600 }, 4241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4242 PCI_SUBVENDOR_ID_CONNECT_TECH, 4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4244 pbn_b1_8_921600 }, 4245 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4246 PCI_SUBVENDOR_ID_CONNECT_TECH, 4247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4248 pbn_b1_4_921600 }, 4249 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4250 PCI_SUBVENDOR_ID_CONNECT_TECH, 4251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4252 pbn_b1_4_921600 }, 4253 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4254 PCI_SUBVENDOR_ID_CONNECT_TECH, 4255 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4256 pbn_b1_2_921600 }, 4257 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4258 PCI_SUBVENDOR_ID_CONNECT_TECH, 4259 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4260 pbn_b1_8_921600 }, 4261 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4262 PCI_SUBVENDOR_ID_CONNECT_TECH, 4263 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4264 pbn_b1_8_921600 }, 4265 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4266 PCI_SUBVENDOR_ID_CONNECT_TECH, 4267 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4268 pbn_b1_4_921600 }, 4269 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4270 PCI_SUBVENDOR_ID_CONNECT_TECH, 4271 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4272 pbn_b1_2_1250000 }, 4273 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4274 PCI_SUBVENDOR_ID_CONNECT_TECH, 4275 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4276 pbn_b0_2_1843200 }, 4277 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4278 PCI_SUBVENDOR_ID_CONNECT_TECH, 4279 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4280 pbn_b0_4_1843200 }, 4281 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4282 PCI_VENDOR_ID_AFAVLAB, 4283 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4284 pbn_b0_4_1152000 }, 4285 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4286 PCI_SUBVENDOR_ID_CONNECT_TECH, 4287 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4288 pbn_b0_2_1843200_200 }, 4289 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4290 PCI_SUBVENDOR_ID_CONNECT_TECH, 4291 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4292 pbn_b0_4_1843200_200 }, 4293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4294 PCI_SUBVENDOR_ID_CONNECT_TECH, 4295 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4296 pbn_b0_8_1843200_200 }, 4297 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4298 PCI_SUBVENDOR_ID_CONNECT_TECH, 4299 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4300 pbn_b0_2_1843200_200 }, 4301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4302 PCI_SUBVENDOR_ID_CONNECT_TECH, 4303 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4304 pbn_b0_4_1843200_200 }, 4305 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4306 PCI_SUBVENDOR_ID_CONNECT_TECH, 4307 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4308 pbn_b0_8_1843200_200 }, 4309 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4310 PCI_SUBVENDOR_ID_CONNECT_TECH, 4311 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4312 pbn_b0_2_1843200_200 }, 4313 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4314 PCI_SUBVENDOR_ID_CONNECT_TECH, 4315 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4316 pbn_b0_4_1843200_200 }, 4317 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4318 PCI_SUBVENDOR_ID_CONNECT_TECH, 4319 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4320 pbn_b0_8_1843200_200 }, 4321 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4322 PCI_SUBVENDOR_ID_CONNECT_TECH, 4323 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4324 pbn_b0_2_1843200_200 }, 4325 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4326 PCI_SUBVENDOR_ID_CONNECT_TECH, 4327 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4328 pbn_b0_4_1843200_200 }, 4329 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4330 PCI_SUBVENDOR_ID_CONNECT_TECH, 4331 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4332 pbn_b0_8_1843200_200 }, 4333 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4334 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4335 0, 0, pbn_exar_ibm_saturn }, 4336 4337 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_b2_bt_1_115200 }, 4340 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_b2_bt_2_115200 }, 4343 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4345 pbn_b2_bt_4_115200 }, 4346 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4348 pbn_b2_bt_2_115200 }, 4349 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4351 pbn_b2_bt_4_115200 }, 4352 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_b2_8_115200 }, 4355 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4357 pbn_b2_8_460800 }, 4358 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4360 pbn_b2_8_115200 }, 4361 4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b2_bt_2_115200 }, 4365 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4367 pbn_b2_bt_2_921600 }, 4368 /* 4369 * VScom SPCOM800, from sl@s.pl 4370 */ 4371 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4373 pbn_b2_8_921600 }, 4374 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b2_4_921600 }, 4377 /* Unknown card - subdevice 0x1584 */ 4378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4379 PCI_VENDOR_ID_PLX, 4380 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4381 pbn_b2_4_115200 }, 4382 /* Unknown card - subdevice 0x1588 */ 4383 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4384 PCI_VENDOR_ID_PLX, 4385 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4386 pbn_b2_8_115200 }, 4387 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4388 PCI_SUBVENDOR_ID_KEYSPAN, 4389 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4390 pbn_panacom }, 4391 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4393 pbn_panacom4 }, 4394 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4396 pbn_panacom2 }, 4397 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4398 PCI_VENDOR_ID_ESDGMBH, 4399 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4400 pbn_b2_4_115200 }, 4401 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4402 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4403 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4404 pbn_b2_4_460800 }, 4405 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4406 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4407 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4408 pbn_b2_8_460800 }, 4409 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4410 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4411 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4412 pbn_b2_16_460800 }, 4413 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4414 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4415 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4416 pbn_b2_16_460800 }, 4417 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4418 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4419 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4420 pbn_b2_4_460800 }, 4421 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4422 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4423 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4424 pbn_b2_8_460800 }, 4425 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4426 PCI_SUBVENDOR_ID_EXSYS, 4427 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4428 pbn_b2_4_115200 }, 4429 /* 4430 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4431 * (Exoray@isys.ca) 4432 */ 4433 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4434 0x10b5, 0x106a, 0, 0, 4435 pbn_plx_romulus }, 4436 /* 4437 * EndRun Technologies. PCI express device range. 4438 * EndRun PTP/1588 has 2 Native UARTs. 4439 */ 4440 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_endrun_2_4000000 }, 4443 /* 4444 * Quatech cards. These actually have configurable clocks but for 4445 * now we just use the default. 4446 * 4447 * 100 series are RS232, 200 series RS422, 4448 */ 4449 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_b1_4_115200 }, 4452 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4454 pbn_b1_2_115200 }, 4455 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4457 pbn_b2_2_115200 }, 4458 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4460 pbn_b1_2_115200 }, 4461 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_b2_2_115200 }, 4464 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_b1_4_115200 }, 4467 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_b1_8_115200 }, 4470 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_b1_8_115200 }, 4473 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_b1_4_115200 }, 4476 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_b1_2_115200 }, 4479 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b1_4_115200 }, 4482 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_b1_2_115200 }, 4485 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_b2_4_115200 }, 4488 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_b2_2_115200 }, 4491 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_b2_1_115200 }, 4494 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_b2_4_115200 }, 4497 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_b2_2_115200 }, 4500 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_b2_1_115200 }, 4503 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b0_8_115200 }, 4506 4507 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4508 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4509 0, 0, 4510 pbn_b0_4_921600 }, 4511 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4512 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4513 0, 0, 4514 pbn_b0_4_1152000 }, 4515 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_b0_bt_2_921600 }, 4518 4519 /* 4520 * The below card is a little controversial since it is the 4521 * subject of a PCI vendor/device ID clash. (See 4522 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4523 * For now just used the hex ID 0x950a. 4524 */ 4525 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4526 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4527 0, 0, pbn_b0_2_115200 }, 4528 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4529 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4530 0, 0, pbn_b0_2_115200 }, 4531 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4533 pbn_b0_2_1130000 }, 4534 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4535 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4536 pbn_b0_1_921600 }, 4537 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_b0_4_115200 }, 4540 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4542 pbn_b0_bt_2_921600 }, 4543 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4544 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4545 pbn_b2_8_1152000 }, 4546 4547 /* 4548 * Oxford Semiconductor Inc. Tornado PCI express device range. 4549 */ 4550 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4552 pbn_b0_1_4000000 }, 4553 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4555 pbn_b0_1_4000000 }, 4556 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4558 pbn_oxsemi_1_4000000 }, 4559 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4561 pbn_oxsemi_1_4000000 }, 4562 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_b0_1_4000000 }, 4565 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4567 pbn_b0_1_4000000 }, 4568 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4570 pbn_oxsemi_1_4000000 }, 4571 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_oxsemi_1_4000000 }, 4574 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_b0_1_4000000 }, 4577 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_b0_1_4000000 }, 4580 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_b0_1_4000000 }, 4583 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_b0_1_4000000 }, 4586 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_oxsemi_2_4000000 }, 4589 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_oxsemi_2_4000000 }, 4592 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_oxsemi_4_4000000 }, 4595 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4597 pbn_oxsemi_4_4000000 }, 4598 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_oxsemi_8_4000000 }, 4601 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4603 pbn_oxsemi_8_4000000 }, 4604 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_oxsemi_1_4000000 }, 4607 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_oxsemi_1_4000000 }, 4610 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_oxsemi_1_4000000 }, 4613 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_oxsemi_1_4000000 }, 4616 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_oxsemi_1_4000000 }, 4619 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_oxsemi_1_4000000 }, 4622 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_oxsemi_1_4000000 }, 4625 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_oxsemi_1_4000000 }, 4628 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_oxsemi_1_4000000 }, 4631 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_oxsemi_1_4000000 }, 4634 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_oxsemi_1_4000000 }, 4637 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_oxsemi_1_4000000 }, 4640 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_oxsemi_1_4000000 }, 4643 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_oxsemi_1_4000000 }, 4646 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_oxsemi_1_4000000 }, 4649 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_oxsemi_1_4000000 }, 4652 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_oxsemi_1_4000000 }, 4655 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_oxsemi_1_4000000 }, 4658 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_oxsemi_1_4000000 }, 4661 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_oxsemi_1_4000000 }, 4664 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_oxsemi_1_4000000 }, 4667 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_oxsemi_1_4000000 }, 4670 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_oxsemi_1_4000000 }, 4673 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_oxsemi_1_4000000 }, 4676 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_oxsemi_1_4000000 }, 4679 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_oxsemi_1_4000000 }, 4682 /* 4683 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4684 */ 4685 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4686 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4687 pbn_oxsemi_1_4000000 }, 4688 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4689 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4690 pbn_oxsemi_2_4000000 }, 4691 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4692 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4693 pbn_oxsemi_4_4000000 }, 4694 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4695 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4696 pbn_oxsemi_8_4000000 }, 4697 4698 /* 4699 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4700 */ 4701 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4702 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4703 pbn_oxsemi_2_4000000 }, 4704 4705 /* 4706 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4707 * from skokodyn@yahoo.com 4708 */ 4709 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4710 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4711 pbn_sbsxrsio }, 4712 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4713 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4714 pbn_sbsxrsio }, 4715 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4716 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4717 pbn_sbsxrsio }, 4718 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4719 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4720 pbn_sbsxrsio }, 4721 4722 /* 4723 * Digitan DS560-558, from jimd@esoft.com 4724 */ 4725 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b1_1_115200 }, 4728 4729 /* 4730 * Titan Electronic cards 4731 * The 400L and 800L have a custom setup quirk. 4732 */ 4733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_b0_1_921600 }, 4736 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_b0_2_921600 }, 4739 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_b0_4_921600 }, 4742 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_b0_4_921600 }, 4745 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4747 pbn_b1_1_921600 }, 4748 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_b1_bt_2_921600 }, 4751 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_b0_bt_4_921600 }, 4754 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_b0_bt_8_921600 }, 4757 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_b4_bt_2_921600 }, 4760 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_b4_bt_4_921600 }, 4763 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_b4_bt_8_921600 }, 4766 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_b0_4_921600 }, 4769 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_b0_4_921600 }, 4772 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_b0_4_921600 }, 4775 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_oxsemi_1_4000000 }, 4778 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_oxsemi_2_4000000 }, 4781 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_oxsemi_4_4000000 }, 4784 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_oxsemi_8_4000000 }, 4787 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_oxsemi_2_4000000 }, 4790 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_oxsemi_2_4000000 }, 4793 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_b0_bt_2_921600 }, 4796 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_b0_4_921600 }, 4799 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_b0_4_921600 }, 4802 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_b0_4_921600 }, 4805 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_b0_4_921600 }, 4808 4809 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4811 pbn_b2_1_460800 }, 4812 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4814 pbn_b2_1_460800 }, 4815 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_b2_1_460800 }, 4818 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4820 pbn_b2_bt_2_921600 }, 4821 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4823 pbn_b2_bt_2_921600 }, 4824 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4826 pbn_b2_bt_2_921600 }, 4827 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4829 pbn_b2_bt_4_921600 }, 4830 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4832 pbn_b2_bt_4_921600 }, 4833 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4835 pbn_b2_bt_4_921600 }, 4836 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4838 pbn_b0_1_921600 }, 4839 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4841 pbn_b0_1_921600 }, 4842 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4844 pbn_b0_1_921600 }, 4845 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4847 pbn_b0_bt_2_921600 }, 4848 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4850 pbn_b0_bt_2_921600 }, 4851 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4853 pbn_b0_bt_2_921600 }, 4854 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b0_bt_4_921600 }, 4857 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b0_bt_4_921600 }, 4860 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_bt_4_921600 }, 4863 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_bt_8_921600 }, 4866 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_b0_bt_8_921600 }, 4869 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_bt_8_921600 }, 4872 4873 /* 4874 * Computone devices submitted by Doug McNash dmcnash@computone.com 4875 */ 4876 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4877 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4878 0, 0, pbn_computone_4 }, 4879 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4880 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4881 0, 0, pbn_computone_8 }, 4882 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4883 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4884 0, 0, pbn_computone_6 }, 4885 4886 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4888 pbn_oxsemi }, 4889 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4890 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4891 pbn_b0_bt_1_921600 }, 4892 4893 /* 4894 * SUNIX (TIMEDIA) 4895 */ 4896 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4897 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4898 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4899 pbn_b0_bt_1_921600 }, 4900 4901 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4902 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4903 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4904 pbn_b0_bt_1_921600 }, 4905 4906 /* 4907 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4908 */ 4909 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4911 pbn_b0_bt_8_115200 }, 4912 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4914 pbn_b0_bt_8_115200 }, 4915 4916 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4918 pbn_b0_bt_2_115200 }, 4919 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4921 pbn_b0_bt_2_115200 }, 4922 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4924 pbn_b0_bt_2_115200 }, 4925 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4927 pbn_b0_bt_2_115200 }, 4928 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4930 pbn_b0_bt_2_115200 }, 4931 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4933 pbn_b0_bt_4_460800 }, 4934 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4936 pbn_b0_bt_4_460800 }, 4937 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b0_bt_2_460800 }, 4940 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b0_bt_2_460800 }, 4943 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b0_bt_2_460800 }, 4946 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4948 pbn_b0_bt_1_115200 }, 4949 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4951 pbn_b0_bt_1_460800 }, 4952 4953 /* 4954 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4955 * Cards are identified by their subsystem vendor IDs, which 4956 * (in hex) match the model number. 4957 * 4958 * Note that JC140x are RS422/485 cards which require ox950 4959 * ACR = 0x10, and as such are not currently fully supported. 4960 */ 4961 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4962 0x1204, 0x0004, 0, 0, 4963 pbn_b0_4_921600 }, 4964 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4965 0x1208, 0x0004, 0, 0, 4966 pbn_b0_4_921600 }, 4967/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4968 0x1402, 0x0002, 0, 0, 4969 pbn_b0_2_921600 }, */ 4970/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4971 0x1404, 0x0004, 0, 0, 4972 pbn_b0_4_921600 }, */ 4973 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4974 0x1208, 0x0004, 0, 0, 4975 pbn_b0_4_921600 }, 4976 4977 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4978 0x1204, 0x0004, 0, 0, 4979 pbn_b0_4_921600 }, 4980 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4981 0x1208, 0x0004, 0, 0, 4982 pbn_b0_4_921600 }, 4983 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4984 0x1208, 0x0004, 0, 0, 4985 pbn_b0_4_921600 }, 4986 /* 4987 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4988 */ 4989 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4991 pbn_b1_1_1382400 }, 4992 4993 /* 4994 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4995 */ 4996 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4998 pbn_b1_1_1382400 }, 4999 5000 /* 5001 * RAStel 2 port modem, gerg@moreton.com.au 5002 */ 5003 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5005 pbn_b2_bt_2_115200 }, 5006 5007 /* 5008 * EKF addition for i960 Boards form EKF with serial port 5009 */ 5010 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5011 0xE4BF, PCI_ANY_ID, 0, 0, 5012 pbn_intel_i960 }, 5013 5014 /* 5015 * Xircom Cardbus/Ethernet combos 5016 */ 5017 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5019 pbn_b0_1_115200 }, 5020 /* 5021 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5022 */ 5023 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5025 pbn_b0_1_115200 }, 5026 5027 /* 5028 * Untested PCI modems, sent in from various folks... 5029 */ 5030 5031 /* 5032 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5033 */ 5034 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5035 0x1048, 0x1500, 0, 0, 5036 pbn_b1_1_115200 }, 5037 5038 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5039 0xFF00, 0, 0, 0, 5040 pbn_sgi_ioc3 }, 5041 5042 /* 5043 * HP Diva card 5044 */ 5045 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5046 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5047 pbn_b1_1_115200 }, 5048 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5050 pbn_b0_5_115200 }, 5051 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5053 pbn_b2_1_115200 }, 5054 5055 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_b3_2_115200 }, 5058 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_b3_4_115200 }, 5061 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_b3_8_115200 }, 5064 5065 /* 5066 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 5067 */ 5068 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 5069 PCI_ANY_ID, PCI_ANY_ID, 5070 0, 5071 0, pbn_exar_XR17C152 }, 5072 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 5073 PCI_ANY_ID, PCI_ANY_ID, 5074 0, 5075 0, pbn_exar_XR17C154 }, 5076 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 5077 PCI_ANY_ID, PCI_ANY_ID, 5078 0, 5079 0, pbn_exar_XR17C158 }, 5080 /* 5081 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs 5082 */ 5083 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 5084 PCI_ANY_ID, PCI_ANY_ID, 5085 0, 5086 0, pbn_exar_XR17V352 }, 5087 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 5088 PCI_ANY_ID, PCI_ANY_ID, 5089 0, 5090 0, pbn_exar_XR17V354 }, 5091 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 5092 PCI_ANY_ID, PCI_ANY_ID, 5093 0, 5094 0, pbn_exar_XR17V358 }, 5095 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, 5096 PCI_ANY_ID, PCI_ANY_ID, 5097 0, 5098 0, pbn_exar_XR17V4358 }, 5099 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, 5100 PCI_ANY_ID, PCI_ANY_ID, 5101 0, 5102 0, pbn_exar_XR17V8358 }, 5103 /* 5104 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5105 */ 5106 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5107 PCI_ANY_ID, PCI_ANY_ID, 5108 0, 5109 0, pbn_pericom_PI7C9X7951 }, 5110 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5111 PCI_ANY_ID, PCI_ANY_ID, 5112 0, 5113 0, pbn_pericom_PI7C9X7952 }, 5114 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5115 PCI_ANY_ID, PCI_ANY_ID, 5116 0, 5117 0, pbn_pericom_PI7C9X7954 }, 5118 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5119 PCI_ANY_ID, PCI_ANY_ID, 5120 0, 5121 0, pbn_pericom_PI7C9X7958 }, 5122 /* 5123 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5124 */ 5125 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5127 pbn_b0_1_115200 }, 5128 /* 5129 * ITE 5130 */ 5131 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5132 PCI_ANY_ID, PCI_ANY_ID, 5133 0, 0, 5134 pbn_b1_bt_1_115200 }, 5135 5136 /* 5137 * IntaShield IS-200 5138 */ 5139 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5141 pbn_b2_2_115200 }, 5142 /* 5143 * IntaShield IS-400 5144 */ 5145 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5147 pbn_b2_4_115200 }, 5148 /* 5149 * Perle PCI-RAS cards 5150 */ 5151 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5152 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5153 0, 0, pbn_b2_4_921600 }, 5154 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5155 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5156 0, 0, pbn_b2_8_921600 }, 5157 5158 /* 5159 * Mainpine series cards: Fairly standard layout but fools 5160 * parts of the autodetect in some cases and uses otherwise 5161 * unmatched communications subclasses in the PCI Express case 5162 */ 5163 5164 { /* RockForceDUO */ 5165 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5166 PCI_VENDOR_ID_MAINPINE, 0x0200, 5167 0, 0, pbn_b0_2_115200 }, 5168 { /* RockForceQUATRO */ 5169 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5170 PCI_VENDOR_ID_MAINPINE, 0x0300, 5171 0, 0, pbn_b0_4_115200 }, 5172 { /* RockForceDUO+ */ 5173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5174 PCI_VENDOR_ID_MAINPINE, 0x0400, 5175 0, 0, pbn_b0_2_115200 }, 5176 { /* RockForceQUATRO+ */ 5177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5178 PCI_VENDOR_ID_MAINPINE, 0x0500, 5179 0, 0, pbn_b0_4_115200 }, 5180 { /* RockForce+ */ 5181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5182 PCI_VENDOR_ID_MAINPINE, 0x0600, 5183 0, 0, pbn_b0_2_115200 }, 5184 { /* RockForce+ */ 5185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5186 PCI_VENDOR_ID_MAINPINE, 0x0700, 5187 0, 0, pbn_b0_4_115200 }, 5188 { /* RockForceOCTO+ */ 5189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5190 PCI_VENDOR_ID_MAINPINE, 0x0800, 5191 0, 0, pbn_b0_8_115200 }, 5192 { /* RockForceDUO+ */ 5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5194 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5195 0, 0, pbn_b0_2_115200 }, 5196 { /* RockForceQUARTRO+ */ 5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5198 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5199 0, 0, pbn_b0_4_115200 }, 5200 { /* RockForceOCTO+ */ 5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5202 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5203 0, 0, pbn_b0_8_115200 }, 5204 { /* RockForceD1 */ 5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5206 PCI_VENDOR_ID_MAINPINE, 0x2000, 5207 0, 0, pbn_b0_1_115200 }, 5208 { /* RockForceF1 */ 5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5210 PCI_VENDOR_ID_MAINPINE, 0x2100, 5211 0, 0, pbn_b0_1_115200 }, 5212 { /* RockForceD2 */ 5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5214 PCI_VENDOR_ID_MAINPINE, 0x2200, 5215 0, 0, pbn_b0_2_115200 }, 5216 { /* RockForceF2 */ 5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5218 PCI_VENDOR_ID_MAINPINE, 0x2300, 5219 0, 0, pbn_b0_2_115200 }, 5220 { /* RockForceD4 */ 5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5222 PCI_VENDOR_ID_MAINPINE, 0x2400, 5223 0, 0, pbn_b0_4_115200 }, 5224 { /* RockForceF4 */ 5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5226 PCI_VENDOR_ID_MAINPINE, 0x2500, 5227 0, 0, pbn_b0_4_115200 }, 5228 { /* RockForceD8 */ 5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5230 PCI_VENDOR_ID_MAINPINE, 0x2600, 5231 0, 0, pbn_b0_8_115200 }, 5232 { /* RockForceF8 */ 5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5234 PCI_VENDOR_ID_MAINPINE, 0x2700, 5235 0, 0, pbn_b0_8_115200 }, 5236 { /* IQ Express D1 */ 5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5238 PCI_VENDOR_ID_MAINPINE, 0x3000, 5239 0, 0, pbn_b0_1_115200 }, 5240 { /* IQ Express F1 */ 5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5242 PCI_VENDOR_ID_MAINPINE, 0x3100, 5243 0, 0, pbn_b0_1_115200 }, 5244 { /* IQ Express D2 */ 5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5246 PCI_VENDOR_ID_MAINPINE, 0x3200, 5247 0, 0, pbn_b0_2_115200 }, 5248 { /* IQ Express F2 */ 5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5250 PCI_VENDOR_ID_MAINPINE, 0x3300, 5251 0, 0, pbn_b0_2_115200 }, 5252 { /* IQ Express D4 */ 5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5254 PCI_VENDOR_ID_MAINPINE, 0x3400, 5255 0, 0, pbn_b0_4_115200 }, 5256 { /* IQ Express F4 */ 5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5258 PCI_VENDOR_ID_MAINPINE, 0x3500, 5259 0, 0, pbn_b0_4_115200 }, 5260 { /* IQ Express D8 */ 5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5262 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5263 0, 0, pbn_b0_8_115200 }, 5264 { /* IQ Express F8 */ 5265 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5266 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5267 0, 0, pbn_b0_8_115200 }, 5268 5269 5270 /* 5271 * PA Semi PA6T-1682M on-chip UART 5272 */ 5273 { PCI_VENDOR_ID_PASEMI, 0xa004, 5274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5275 pbn_pasemi_1682M }, 5276 5277 /* 5278 * National Instruments 5279 */ 5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5282 pbn_b1_16_115200 }, 5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5285 pbn_b1_8_115200 }, 5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5288 pbn_b1_bt_4_115200 }, 5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5291 pbn_b1_bt_2_115200 }, 5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5294 pbn_b1_bt_4_115200 }, 5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5297 pbn_b1_bt_2_115200 }, 5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5300 pbn_b1_16_115200 }, 5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5303 pbn_b1_8_115200 }, 5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5306 pbn_b1_bt_4_115200 }, 5307 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5309 pbn_b1_bt_2_115200 }, 5310 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5312 pbn_b1_bt_4_115200 }, 5313 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5315 pbn_b1_bt_2_115200 }, 5316 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5318 pbn_ni8430_2 }, 5319 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5321 pbn_ni8430_2 }, 5322 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5324 pbn_ni8430_4 }, 5325 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5327 pbn_ni8430_4 }, 5328 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5330 pbn_ni8430_8 }, 5331 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5333 pbn_ni8430_8 }, 5334 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5336 pbn_ni8430_16 }, 5337 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5339 pbn_ni8430_16 }, 5340 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5342 pbn_ni8430_2 }, 5343 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5345 pbn_ni8430_2 }, 5346 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5348 pbn_ni8430_4 }, 5349 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5351 pbn_ni8430_4 }, 5352 5353 /* 5354 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5355 */ 5356 { PCI_VENDOR_ID_ADDIDATA, 5357 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5358 PCI_ANY_ID, 5359 PCI_ANY_ID, 5360 0, 5361 0, 5362 pbn_b0_4_115200 }, 5363 5364 { PCI_VENDOR_ID_ADDIDATA, 5365 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5366 PCI_ANY_ID, 5367 PCI_ANY_ID, 5368 0, 5369 0, 5370 pbn_b0_2_115200 }, 5371 5372 { PCI_VENDOR_ID_ADDIDATA, 5373 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5374 PCI_ANY_ID, 5375 PCI_ANY_ID, 5376 0, 5377 0, 5378 pbn_b0_1_115200 }, 5379 5380 { PCI_VENDOR_ID_AMCC, 5381 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5382 PCI_ANY_ID, 5383 PCI_ANY_ID, 5384 0, 5385 0, 5386 pbn_b1_8_115200 }, 5387 5388 { PCI_VENDOR_ID_ADDIDATA, 5389 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5390 PCI_ANY_ID, 5391 PCI_ANY_ID, 5392 0, 5393 0, 5394 pbn_b0_4_115200 }, 5395 5396 { PCI_VENDOR_ID_ADDIDATA, 5397 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5398 PCI_ANY_ID, 5399 PCI_ANY_ID, 5400 0, 5401 0, 5402 pbn_b0_2_115200 }, 5403 5404 { PCI_VENDOR_ID_ADDIDATA, 5405 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5406 PCI_ANY_ID, 5407 PCI_ANY_ID, 5408 0, 5409 0, 5410 pbn_b0_1_115200 }, 5411 5412 { PCI_VENDOR_ID_ADDIDATA, 5413 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5414 PCI_ANY_ID, 5415 PCI_ANY_ID, 5416 0, 5417 0, 5418 pbn_b0_4_115200 }, 5419 5420 { PCI_VENDOR_ID_ADDIDATA, 5421 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5422 PCI_ANY_ID, 5423 PCI_ANY_ID, 5424 0, 5425 0, 5426 pbn_b0_2_115200 }, 5427 5428 { PCI_VENDOR_ID_ADDIDATA, 5429 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5430 PCI_ANY_ID, 5431 PCI_ANY_ID, 5432 0, 5433 0, 5434 pbn_b0_1_115200 }, 5435 5436 { PCI_VENDOR_ID_ADDIDATA, 5437 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5438 PCI_ANY_ID, 5439 PCI_ANY_ID, 5440 0, 5441 0, 5442 pbn_b0_8_115200 }, 5443 5444 { PCI_VENDOR_ID_ADDIDATA, 5445 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5446 PCI_ANY_ID, 5447 PCI_ANY_ID, 5448 0, 5449 0, 5450 pbn_ADDIDATA_PCIe_4_3906250 }, 5451 5452 { PCI_VENDOR_ID_ADDIDATA, 5453 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5454 PCI_ANY_ID, 5455 PCI_ANY_ID, 5456 0, 5457 0, 5458 pbn_ADDIDATA_PCIe_2_3906250 }, 5459 5460 { PCI_VENDOR_ID_ADDIDATA, 5461 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5462 PCI_ANY_ID, 5463 PCI_ANY_ID, 5464 0, 5465 0, 5466 pbn_ADDIDATA_PCIe_1_3906250 }, 5467 5468 { PCI_VENDOR_ID_ADDIDATA, 5469 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5470 PCI_ANY_ID, 5471 PCI_ANY_ID, 5472 0, 5473 0, 5474 pbn_ADDIDATA_PCIe_8_3906250 }, 5475 5476 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5477 PCI_VENDOR_ID_IBM, 0x0299, 5478 0, 0, pbn_b0_bt_2_115200 }, 5479 5480 /* 5481 * other NetMos 9835 devices are most likely handled by the 5482 * parport_serial driver, check drivers/parport/parport_serial.c 5483 * before adding them here. 5484 */ 5485 5486 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5487 0xA000, 0x1000, 5488 0, 0, pbn_b0_1_115200 }, 5489 5490 /* the 9901 is a rebranded 9912 */ 5491 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5492 0xA000, 0x1000, 5493 0, 0, pbn_b0_1_115200 }, 5494 5495 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5496 0xA000, 0x1000, 5497 0, 0, pbn_b0_1_115200 }, 5498 5499 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5500 0xA000, 0x1000, 5501 0, 0, pbn_b0_1_115200 }, 5502 5503 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5504 0xA000, 0x1000, 5505 0, 0, pbn_b0_1_115200 }, 5506 5507 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5508 0xA000, 0x3002, 5509 0, 0, pbn_NETMOS9900_2s_115200 }, 5510 5511 /* 5512 * Best Connectivity and Rosewill PCI Multi I/O cards 5513 */ 5514 5515 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5516 0xA000, 0x1000, 5517 0, 0, pbn_b0_1_115200 }, 5518 5519 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5520 0xA000, 0x3002, 5521 0, 0, pbn_b0_bt_2_115200 }, 5522 5523 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5524 0xA000, 0x3004, 5525 0, 0, pbn_b0_bt_4_115200 }, 5526 /* Intel CE4100 */ 5527 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5529 pbn_ce4100_1_115200 }, 5530 /* Intel BayTrail */ 5531 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5532 PCI_ANY_ID, PCI_ANY_ID, 5533 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5534 pbn_byt }, 5535 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5536 PCI_ANY_ID, PCI_ANY_ID, 5537 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5538 pbn_byt }, 5539 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, 5540 PCI_ANY_ID, PCI_ANY_ID, 5541 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5542 pbn_byt }, 5543 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, 5544 PCI_ANY_ID, PCI_ANY_ID, 5545 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5546 pbn_byt }, 5547 5548 /* Intel Broadwell */ 5549 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1, 5550 PCI_ANY_ID, PCI_ANY_ID, 5551 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5552 pbn_byt }, 5553 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2, 5554 PCI_ANY_ID, PCI_ANY_ID, 5555 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5556 pbn_byt }, 5557 5558 /* 5559 * Intel Quark x1000 5560 */ 5561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, 5562 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5563 pbn_qrk }, 5564 /* 5565 * Cronyx Omega PCI 5566 */ 5567 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5569 pbn_omegapci }, 5570 5571 /* 5572 * Broadcom TruManage 5573 */ 5574 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5576 pbn_brcm_trumanage }, 5577 5578 /* 5579 * AgeStar as-prs2-009 5580 */ 5581 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5582 PCI_ANY_ID, PCI_ANY_ID, 5583 0, 0, pbn_b0_bt_2_115200 }, 5584 5585 /* 5586 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5587 * so not listed here. 5588 */ 5589 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5590 PCI_ANY_ID, PCI_ANY_ID, 5591 0, 0, pbn_b0_bt_4_115200 }, 5592 5593 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5594 PCI_ANY_ID, PCI_ANY_ID, 5595 0, 0, pbn_b0_bt_2_115200 }, 5596 5597 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5598 PCI_ANY_ID, PCI_ANY_ID, 5599 0, 0, pbn_wch382_2 }, 5600 5601 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5602 PCI_ANY_ID, PCI_ANY_ID, 5603 0, 0, pbn_wch384_4 }, 5604 5605 /* 5606 * Commtech, Inc. Fastcom adapters 5607 */ 5608 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5609 PCI_ANY_ID, PCI_ANY_ID, 5610 0, 5611 0, pbn_b0_2_1152000_200 }, 5612 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5613 PCI_ANY_ID, PCI_ANY_ID, 5614 0, 5615 0, pbn_b0_4_1152000_200 }, 5616 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5617 PCI_ANY_ID, PCI_ANY_ID, 5618 0, 5619 0, pbn_b0_4_1152000_200 }, 5620 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5621 PCI_ANY_ID, PCI_ANY_ID, 5622 0, 5623 0, pbn_b0_8_1152000_200 }, 5624 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5625 PCI_ANY_ID, PCI_ANY_ID, 5626 0, 5627 0, pbn_exar_XR17V352 }, 5628 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5629 PCI_ANY_ID, PCI_ANY_ID, 5630 0, 5631 0, pbn_exar_XR17V354 }, 5632 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5633 PCI_ANY_ID, PCI_ANY_ID, 5634 0, 5635 0, pbn_exar_XR17V358 }, 5636 5637 /* Fintek PCI serial cards */ 5638 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5639 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5640 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5641 5642 /* 5643 * These entries match devices with class COMMUNICATION_SERIAL, 5644 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5645 */ 5646 { PCI_ANY_ID, PCI_ANY_ID, 5647 PCI_ANY_ID, PCI_ANY_ID, 5648 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5649 0xffff00, pbn_default }, 5650 { PCI_ANY_ID, PCI_ANY_ID, 5651 PCI_ANY_ID, PCI_ANY_ID, 5652 PCI_CLASS_COMMUNICATION_MODEM << 8, 5653 0xffff00, pbn_default }, 5654 { PCI_ANY_ID, PCI_ANY_ID, 5655 PCI_ANY_ID, PCI_ANY_ID, 5656 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5657 0xffff00, pbn_default }, 5658 { 0, } 5659}; 5660 5661static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5662 pci_channel_state_t state) 5663{ 5664 struct serial_private *priv = pci_get_drvdata(dev); 5665 5666 if (state == pci_channel_io_perm_failure) 5667 return PCI_ERS_RESULT_DISCONNECT; 5668 5669 if (priv) 5670 pciserial_suspend_ports(priv); 5671 5672 pci_disable_device(dev); 5673 5674 return PCI_ERS_RESULT_NEED_RESET; 5675} 5676 5677static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5678{ 5679 int rc; 5680 5681 rc = pci_enable_device(dev); 5682 5683 if (rc) 5684 return PCI_ERS_RESULT_DISCONNECT; 5685 5686 pci_restore_state(dev); 5687 pci_save_state(dev); 5688 5689 return PCI_ERS_RESULT_RECOVERED; 5690} 5691 5692static void serial8250_io_resume(struct pci_dev *dev) 5693{ 5694 struct serial_private *priv = pci_get_drvdata(dev); 5695 5696 if (priv) 5697 pciserial_resume_ports(priv); 5698} 5699 5700static const struct pci_error_handlers serial8250_err_handler = { 5701 .error_detected = serial8250_io_error_detected, 5702 .slot_reset = serial8250_io_slot_reset, 5703 .resume = serial8250_io_resume, 5704}; 5705 5706static struct pci_driver serial_pci_driver = { 5707 .name = "serial", 5708 .probe = pciserial_init_one, 5709 .remove = pciserial_remove_one, 5710 .driver = { 5711 .pm = &pciserial_pm_ops, 5712 }, 5713 .id_table = serial_pci_tbl, 5714 .err_handler = &serial8250_err_handler, 5715}; 5716 5717module_pci_driver(serial_pci_driver); 5718 5719MODULE_LICENSE("GPL"); 5720MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5721MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5722