1/* 2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * File: device_main.c 20 * 21 * Purpose: driver entry for initial, open, close, tx and rx. 22 * 23 * Author: Lyndon Chen 24 * 25 * Date: Jan 8, 2003 26 * 27 * Functions: 28 * 29 * vt6655_probe - module initial (insmod) driver entry 30 * vt6655_remove - module remove entry 31 * device_free_info - device structure resource free function 32 * device_print_info - print out resource 33 * device_rx_srv - rx service function 34 * device_alloc_rx_buf - rx buffer pre-allocated function 35 * device_free_tx_buf - free tx buffer function 36 * device_init_rd0_ring- initial rd dma0 ring 37 * device_init_rd1_ring- initial rd dma1 ring 38 * device_init_td0_ring- initial tx dma0 ring buffer 39 * device_init_td1_ring- initial tx dma1 ring buffer 40 * device_init_registers- initial MAC & BBP & RF internal registers. 41 * device_init_rings- initial tx/rx ring buffer 42 * device_free_rings- free all allocated ring buffer 43 * device_tx_srv- tx interrupt service function 44 * 45 * Revision History: 46 */ 47#undef __NO_VERSION__ 48 49#include <linux/file.h> 50#include "device.h" 51#include "card.h" 52#include "channel.h" 53#include "baseband.h" 54#include "mac.h" 55#include "power.h" 56#include "rxtx.h" 57#include "dpc.h" 58#include "rf.h" 59#include <linux/delay.h> 60#include <linux/kthread.h> 61#include <linux/slab.h> 62 63/*--------------------- Static Definitions -------------------------*/ 64/* 65 * Define module options 66 */ 67MODULE_AUTHOR("VIA Networking Technologies, Inc., <lyndonchen@vntek.com.tw>"); 68MODULE_LICENSE("GPL"); 69MODULE_DESCRIPTION("VIA Networking Solomon-A/B/G Wireless LAN Adapter Driver"); 70 71#define DEVICE_PARAM(N, D) 72 73#define RX_DESC_MIN0 16 74#define RX_DESC_MAX0 128 75#define RX_DESC_DEF0 32 76DEVICE_PARAM(RxDescriptors0, "Number of receive descriptors0"); 77 78#define RX_DESC_MIN1 16 79#define RX_DESC_MAX1 128 80#define RX_DESC_DEF1 32 81DEVICE_PARAM(RxDescriptors1, "Number of receive descriptors1"); 82 83#define TX_DESC_MIN0 16 84#define TX_DESC_MAX0 128 85#define TX_DESC_DEF0 32 86DEVICE_PARAM(TxDescriptors0, "Number of transmit descriptors0"); 87 88#define TX_DESC_MIN1 16 89#define TX_DESC_MAX1 128 90#define TX_DESC_DEF1 64 91DEVICE_PARAM(TxDescriptors1, "Number of transmit descriptors1"); 92 93#define INT_WORKS_DEF 20 94#define INT_WORKS_MIN 10 95#define INT_WORKS_MAX 64 96 97DEVICE_PARAM(int_works, "Number of packets per interrupt services"); 98 99#define RTS_THRESH_DEF 2347 100 101#define FRAG_THRESH_DEF 2346 102 103#define SHORT_RETRY_MIN 0 104#define SHORT_RETRY_MAX 31 105#define SHORT_RETRY_DEF 8 106 107DEVICE_PARAM(ShortRetryLimit, "Short frame retry limits"); 108 109#define LONG_RETRY_MIN 0 110#define LONG_RETRY_MAX 15 111#define LONG_RETRY_DEF 4 112 113DEVICE_PARAM(LongRetryLimit, "long frame retry limits"); 114 115/* BasebandType[] baseband type selected 116 0: indicate 802.11a type 117 1: indicate 802.11b type 118 2: indicate 802.11g type 119*/ 120#define BBP_TYPE_MIN 0 121#define BBP_TYPE_MAX 2 122#define BBP_TYPE_DEF 2 123 124DEVICE_PARAM(BasebandType, "baseband type"); 125 126/* 127 * Static vars definitions 128 */ 129static const struct pci_device_id vt6655_pci_id_table[] = { 130 { PCI_VDEVICE(VIA, 0x3253) }, 131 { 0, } 132}; 133 134/*--------------------- Static Functions --------------------------*/ 135 136static int vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent); 137static void device_free_info(struct vnt_private *priv); 138static void device_print_info(struct vnt_private *priv); 139 140static void device_init_rd0_ring(struct vnt_private *priv); 141static void device_init_rd1_ring(struct vnt_private *priv); 142static void device_init_td0_ring(struct vnt_private *priv); 143static void device_init_td1_ring(struct vnt_private *priv); 144 145static int device_rx_srv(struct vnt_private *priv, unsigned int idx); 146static int device_tx_srv(struct vnt_private *priv, unsigned int idx); 147static bool device_alloc_rx_buf(struct vnt_private *, struct vnt_rx_desc *); 148static void device_init_registers(struct vnt_private *priv); 149static void device_free_tx_buf(struct vnt_private *, struct vnt_tx_desc *); 150static void device_free_td0_ring(struct vnt_private *priv); 151static void device_free_td1_ring(struct vnt_private *priv); 152static void device_free_rd0_ring(struct vnt_private *priv); 153static void device_free_rd1_ring(struct vnt_private *priv); 154static void device_free_rings(struct vnt_private *priv); 155 156/*--------------------- Export Variables --------------------------*/ 157 158/*--------------------- Export Functions --------------------------*/ 159 160static void vt6655_remove(struct pci_dev *pcid) 161{ 162 struct vnt_private *priv = pci_get_drvdata(pcid); 163 164 if (priv == NULL) 165 return; 166 device_free_info(priv); 167} 168 169static void device_get_options(struct vnt_private *priv) 170{ 171 struct vnt_options *opts = &priv->opts; 172 173 opts->rx_descs0 = RX_DESC_DEF0; 174 opts->rx_descs1 = RX_DESC_DEF1; 175 opts->tx_descs[0] = TX_DESC_DEF0; 176 opts->tx_descs[1] = TX_DESC_DEF1; 177 opts->int_works = INT_WORKS_DEF; 178 179 opts->short_retry = SHORT_RETRY_DEF; 180 opts->long_retry = LONG_RETRY_DEF; 181 opts->bbp_type = BBP_TYPE_DEF; 182} 183 184static void 185device_set_options(struct vnt_private *priv) 186{ 187 priv->byShortRetryLimit = priv->opts.short_retry; 188 priv->byLongRetryLimit = priv->opts.long_retry; 189 priv->byBBType = priv->opts.bbp_type; 190 priv->byPacketType = priv->byBBType; 191 priv->byAutoFBCtrl = AUTO_FB_0; 192 priv->bUpdateBBVGA = true; 193 priv->byPreambleType = 0; 194 195 pr_debug(" byShortRetryLimit= %d\n", (int)priv->byShortRetryLimit); 196 pr_debug(" byLongRetryLimit= %d\n", (int)priv->byLongRetryLimit); 197 pr_debug(" byPreambleType= %d\n", (int)priv->byPreambleType); 198 pr_debug(" byShortPreamble= %d\n", (int)priv->byShortPreamble); 199 pr_debug(" byBBType= %d\n", (int)priv->byBBType); 200} 201 202/* 203 * Initialisation of MAC & BBP registers 204 */ 205 206static void device_init_registers(struct vnt_private *priv) 207{ 208 unsigned long flags; 209 unsigned int ii; 210 unsigned char byValue; 211 unsigned char byCCKPwrdBm = 0; 212 unsigned char byOFDMPwrdBm = 0; 213 214 MACbShutdown(priv->PortOffset); 215 BBvSoftwareReset(priv); 216 217 /* Do MACbSoftwareReset in MACvInitialize */ 218 MACbSoftwareReset(priv->PortOffset); 219 220 priv->bAES = false; 221 222 /* Only used in 11g type, sync with ERP IE */ 223 priv->bProtectMode = false; 224 225 priv->bNonERPPresent = false; 226 priv->bBarkerPreambleMd = false; 227 priv->wCurrentRate = RATE_1M; 228 priv->byTopOFDMBasicRate = RATE_24M; 229 priv->byTopCCKBasicRate = RATE_1M; 230 231 /* init MAC */ 232 MACvInitialize(priv->PortOffset); 233 234 /* Get Local ID */ 235 VNSvInPortB(priv->PortOffset + MAC_REG_LOCALID, &priv->byLocalID); 236 237 spin_lock_irqsave(&priv->lock, flags); 238 239 SROMvReadAllContents(priv->PortOffset, priv->abyEEPROM); 240 241 spin_unlock_irqrestore(&priv->lock, flags); 242 243 /* Get Channel range */ 244 priv->byMinChannel = 1; 245 priv->byMaxChannel = CB_MAX_CHANNEL; 246 247 /* Get Antena */ 248 byValue = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_ANTENNA); 249 if (byValue & EEP_ANTINV) 250 priv->bTxRxAntInv = true; 251 else 252 priv->bTxRxAntInv = false; 253 254 byValue &= (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN); 255 /* if not set default is All */ 256 if (byValue == 0) 257 byValue = (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN); 258 259 if (byValue == (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN)) { 260 priv->byAntennaCount = 2; 261 priv->byTxAntennaMode = ANT_B; 262 priv->dwTxAntennaSel = 1; 263 priv->dwRxAntennaSel = 1; 264 265 if (priv->bTxRxAntInv) 266 priv->byRxAntennaMode = ANT_A; 267 else 268 priv->byRxAntennaMode = ANT_B; 269 } else { 270 priv->byAntennaCount = 1; 271 priv->dwTxAntennaSel = 0; 272 priv->dwRxAntennaSel = 0; 273 274 if (byValue & EEP_ANTENNA_AUX) { 275 priv->byTxAntennaMode = ANT_A; 276 277 if (priv->bTxRxAntInv) 278 priv->byRxAntennaMode = ANT_B; 279 else 280 priv->byRxAntennaMode = ANT_A; 281 } else { 282 priv->byTxAntennaMode = ANT_B; 283 284 if (priv->bTxRxAntInv) 285 priv->byRxAntennaMode = ANT_A; 286 else 287 priv->byRxAntennaMode = ANT_B; 288 } 289 } 290 291 /* Set initial antenna mode */ 292 BBvSetTxAntennaMode(priv, priv->byTxAntennaMode); 293 BBvSetRxAntennaMode(priv, priv->byRxAntennaMode); 294 295 /* zonetype initial */ 296 priv->byOriginalZonetype = priv->abyEEPROM[EEP_OFS_ZONETYPE]; 297 298 if (!priv->bZoneRegExist) 299 priv->byZoneType = priv->abyEEPROM[EEP_OFS_ZONETYPE]; 300 301 pr_debug("priv->byZoneType = %x\n", priv->byZoneType); 302 303 /* Init RF module */ 304 RFbInit(priv); 305 306 /* Get Desire Power Value */ 307 priv->byCurPwr = 0xFF; 308 priv->byCCKPwr = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_PWR_CCK); 309 priv->byOFDMPwrG = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_PWR_OFDMG); 310 311 /* Load power Table */ 312 for (ii = 0; ii < CB_MAX_CHANNEL_24G; ii++) { 313 priv->abyCCKPwrTbl[ii + 1] = 314 SROMbyReadEmbedded(priv->PortOffset, 315 (unsigned char)(ii + EEP_OFS_CCK_PWR_TBL)); 316 if (priv->abyCCKPwrTbl[ii + 1] == 0) 317 priv->abyCCKPwrTbl[ii+1] = priv->byCCKPwr; 318 319 priv->abyOFDMPwrTbl[ii + 1] = 320 SROMbyReadEmbedded(priv->PortOffset, 321 (unsigned char)(ii + EEP_OFS_OFDM_PWR_TBL)); 322 if (priv->abyOFDMPwrTbl[ii + 1] == 0) 323 priv->abyOFDMPwrTbl[ii + 1] = priv->byOFDMPwrG; 324 325 priv->abyCCKDefaultPwr[ii + 1] = byCCKPwrdBm; 326 priv->abyOFDMDefaultPwr[ii + 1] = byOFDMPwrdBm; 327 } 328 329 /* recover 12,13 ,14channel for EUROPE by 11 channel */ 330 for (ii = 11; ii < 14; ii++) { 331 priv->abyCCKPwrTbl[ii] = priv->abyCCKPwrTbl[10]; 332 priv->abyOFDMPwrTbl[ii] = priv->abyOFDMPwrTbl[10]; 333 } 334 335 /* Load OFDM A Power Table */ 336 for (ii = 0; ii < CB_MAX_CHANNEL_5G; ii++) { 337 priv->abyOFDMPwrTbl[ii + CB_MAX_CHANNEL_24G + 1] = 338 SROMbyReadEmbedded(priv->PortOffset, 339 (unsigned char)(ii + EEP_OFS_OFDMA_PWR_TBL)); 340 341 priv->abyOFDMDefaultPwr[ii + CB_MAX_CHANNEL_24G + 1] = 342 SROMbyReadEmbedded(priv->PortOffset, 343 (unsigned char)(ii + EEP_OFS_OFDMA_PWR_dBm)); 344 } 345 346 if (priv->byLocalID > REV_ID_VT3253_B1) { 347 MACvSelectPage1(priv->PortOffset); 348 349 VNSvOutPortB(priv->PortOffset + MAC_REG_MSRCTL + 1, 350 (MSRCTL1_TXPWR | MSRCTL1_CSAPAREN)); 351 352 MACvSelectPage0(priv->PortOffset); 353 } 354 355 /* use relative tx timeout and 802.11i D4 */ 356 MACvWordRegBitsOn(priv->PortOffset, 357 MAC_REG_CFG, (CFG_TKIPOPT | CFG_NOTXTIMEOUT)); 358 359 /* set performance parameter by registry */ 360 MACvSetShortRetryLimit(priv->PortOffset, priv->byShortRetryLimit); 361 MACvSetLongRetryLimit(priv->PortOffset, priv->byLongRetryLimit); 362 363 /* reset TSF counter */ 364 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); 365 /* enable TSF counter */ 366 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); 367 368 /* initialize BBP registers */ 369 BBbVT3253Init(priv); 370 371 if (priv->bUpdateBBVGA) { 372 priv->byBBVGACurrent = priv->abyBBVGA[0]; 373 priv->byBBVGANew = priv->byBBVGACurrent; 374 BBvSetVGAGainOffset(priv, priv->abyBBVGA[0]); 375 } 376 377 BBvSetRxAntennaMode(priv, priv->byRxAntennaMode); 378 BBvSetTxAntennaMode(priv, priv->byTxAntennaMode); 379 380 /* Set BB and packet type at the same time. */ 381 /* Set Short Slot Time, xIFS, and RSPINF. */ 382 priv->wCurrentRate = RATE_54M; 383 384 priv->bRadioOff = false; 385 386 priv->byRadioCtl = SROMbyReadEmbedded(priv->PortOffset, 387 EEP_OFS_RADIOCTL); 388 priv->bHWRadioOff = false; 389 390 if (priv->byRadioCtl & EEP_RADIOCTL_ENABLE) { 391 /* Get GPIO */ 392 MACvGPIOIn(priv->PortOffset, &priv->byGPIO); 393 394 if (((priv->byGPIO & GPIO0_DATA) && 395 !(priv->byRadioCtl & EEP_RADIOCTL_INV)) || 396 (!(priv->byGPIO & GPIO0_DATA) && 397 (priv->byRadioCtl & EEP_RADIOCTL_INV))) 398 priv->bHWRadioOff = true; 399 } 400 401 if (priv->bHWRadioOff || priv->bRadioControlOff) 402 CARDbRadioPowerOff(priv); 403 404 /* get Permanent network address */ 405 SROMvReadEtherAddress(priv->PortOffset, priv->abyCurrentNetAddr); 406 pr_debug("Network address = %pM\n", priv->abyCurrentNetAddr); 407 408 /* reset Tx pointer */ 409 CARDvSafeResetRx(priv); 410 /* reset Rx pointer */ 411 CARDvSafeResetTx(priv); 412 413 if (priv->byLocalID <= REV_ID_VT3253_A1) 414 MACvRegBitsOn(priv->PortOffset, MAC_REG_RCR, RCR_WPAERR); 415 416 /* Turn On Rx DMA */ 417 MACvReceive0(priv->PortOffset); 418 MACvReceive1(priv->PortOffset); 419 420 /* start the adapter */ 421 MACvStart(priv->PortOffset); 422} 423 424static void device_print_info(struct vnt_private *priv) 425{ 426 dev_info(&priv->pcid->dev, "MAC=%pM IO=0x%lx Mem=0x%lx IRQ=%d\n", 427 priv->abyCurrentNetAddr, (unsigned long)priv->ioaddr, 428 (unsigned long)priv->PortOffset, priv->pcid->irq); 429} 430 431static void device_free_info(struct vnt_private *priv) 432{ 433 if (!priv) 434 return; 435 436 if (priv->mac_hw) 437 ieee80211_unregister_hw(priv->hw); 438 439 if (priv->PortOffset) 440 iounmap(priv->PortOffset); 441 442 if (priv->pcid) 443 pci_release_regions(priv->pcid); 444 445 if (priv->hw) 446 ieee80211_free_hw(priv->hw); 447} 448 449static bool device_init_rings(struct vnt_private *priv) 450{ 451 void *vir_pool; 452 453 /*allocate all RD/TD rings a single pool*/ 454 vir_pool = dma_zalloc_coherent(&priv->pcid->dev, 455 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) + 456 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) + 457 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) + 458 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc), 459 &priv->pool_dma, GFP_ATOMIC); 460 if (vir_pool == NULL) { 461 dev_err(&priv->pcid->dev, "allocate desc dma memory failed\n"); 462 return false; 463 } 464 465 priv->aRD0Ring = vir_pool; 466 priv->aRD1Ring = vir_pool + 467 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc); 468 469 priv->rd0_pool_dma = priv->pool_dma; 470 priv->rd1_pool_dma = priv->rd0_pool_dma + 471 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc); 472 473 priv->tx0_bufs = dma_zalloc_coherent(&priv->pcid->dev, 474 priv->opts.tx_descs[0] * PKT_BUF_SZ + 475 priv->opts.tx_descs[1] * PKT_BUF_SZ + 476 CB_BEACON_BUF_SIZE + 477 CB_MAX_BUF_SIZE, 478 &priv->tx_bufs_dma0, 479 GFP_ATOMIC); 480 if (priv->tx0_bufs == NULL) { 481 dev_err(&priv->pcid->dev, "allocate buf dma memory failed\n"); 482 483 dma_free_coherent(&priv->pcid->dev, 484 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) + 485 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) + 486 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) + 487 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc), 488 vir_pool, priv->pool_dma); 489 return false; 490 } 491 492 priv->td0_pool_dma = priv->rd1_pool_dma + 493 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc); 494 495 priv->td1_pool_dma = priv->td0_pool_dma + 496 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc); 497 498 /* vir_pool: pvoid type */ 499 priv->apTD0Rings = vir_pool 500 + priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) 501 + priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc); 502 503 priv->apTD1Rings = vir_pool 504 + priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) 505 + priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) 506 + priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc); 507 508 priv->tx1_bufs = priv->tx0_bufs + 509 priv->opts.tx_descs[0] * PKT_BUF_SZ; 510 511 priv->tx_beacon_bufs = priv->tx1_bufs + 512 priv->opts.tx_descs[1] * PKT_BUF_SZ; 513 514 priv->pbyTmpBuff = priv->tx_beacon_bufs + 515 CB_BEACON_BUF_SIZE; 516 517 priv->tx_bufs_dma1 = priv->tx_bufs_dma0 + 518 priv->opts.tx_descs[0] * PKT_BUF_SZ; 519 520 priv->tx_beacon_dma = priv->tx_bufs_dma1 + 521 priv->opts.tx_descs[1] * PKT_BUF_SZ; 522 523 return true; 524} 525 526static void device_free_rings(struct vnt_private *priv) 527{ 528 dma_free_coherent(&priv->pcid->dev, 529 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) + 530 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) + 531 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) + 532 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc), 533 priv->aRD0Ring, priv->pool_dma); 534 535 if (priv->tx0_bufs) 536 dma_free_coherent(&priv->pcid->dev, 537 priv->opts.tx_descs[0] * PKT_BUF_SZ + 538 priv->opts.tx_descs[1] * PKT_BUF_SZ + 539 CB_BEACON_BUF_SIZE + 540 CB_MAX_BUF_SIZE, 541 priv->tx0_bufs, priv->tx_bufs_dma0); 542} 543 544static void device_init_rd0_ring(struct vnt_private *priv) 545{ 546 int i; 547 dma_addr_t curr = priv->rd0_pool_dma; 548 struct vnt_rx_desc *desc; 549 550 /* Init the RD0 ring entries */ 551 for (i = 0; i < priv->opts.rx_descs0; 552 i ++, curr += sizeof(struct vnt_rx_desc)) { 553 desc = &priv->aRD0Ring[i]; 554 desc->rd_info = kzalloc(sizeof(*desc->rd_info), GFP_ATOMIC); 555 556 if (!device_alloc_rx_buf(priv, desc)) 557 dev_err(&priv->pcid->dev, "can not alloc rx bufs\n"); 558 559 desc->next = &(priv->aRD0Ring[(i+1) % priv->opts.rx_descs0]); 560 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_rx_desc)); 561 } 562 563 if (i > 0) 564 priv->aRD0Ring[i-1].next_desc = cpu_to_le32(priv->rd0_pool_dma); 565 priv->pCurrRD[0] = &priv->aRD0Ring[0]; 566} 567 568static void device_init_rd1_ring(struct vnt_private *priv) 569{ 570 int i; 571 dma_addr_t curr = priv->rd1_pool_dma; 572 struct vnt_rx_desc *desc; 573 574 /* Init the RD1 ring entries */ 575 for (i = 0; i < priv->opts.rx_descs1; 576 i ++, curr += sizeof(struct vnt_rx_desc)) { 577 desc = &priv->aRD1Ring[i]; 578 desc->rd_info = kzalloc(sizeof(*desc->rd_info), GFP_ATOMIC); 579 580 if (!device_alloc_rx_buf(priv, desc)) 581 dev_err(&priv->pcid->dev, "can not alloc rx bufs\n"); 582 583 desc->next = &(priv->aRD1Ring[(i+1) % priv->opts.rx_descs1]); 584 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_rx_desc)); 585 } 586 587 if (i > 0) 588 priv->aRD1Ring[i-1].next_desc = cpu_to_le32(priv->rd1_pool_dma); 589 priv->pCurrRD[1] = &priv->aRD1Ring[0]; 590} 591 592static void device_free_rd0_ring(struct vnt_private *priv) 593{ 594 int i; 595 596 for (i = 0; i < priv->opts.rx_descs0; i++) { 597 struct vnt_rx_desc *desc = &(priv->aRD0Ring[i]); 598 struct vnt_rd_info *rd_info = desc->rd_info; 599 600 dma_unmap_single(&priv->pcid->dev, rd_info->skb_dma, 601 priv->rx_buf_sz, DMA_FROM_DEVICE); 602 603 dev_kfree_skb(rd_info->skb); 604 605 kfree(desc->rd_info); 606 } 607} 608 609static void device_free_rd1_ring(struct vnt_private *priv) 610{ 611 int i; 612 613 for (i = 0; i < priv->opts.rx_descs1; i++) { 614 struct vnt_rx_desc *desc = &priv->aRD1Ring[i]; 615 struct vnt_rd_info *rd_info = desc->rd_info; 616 617 dma_unmap_single(&priv->pcid->dev, rd_info->skb_dma, 618 priv->rx_buf_sz, DMA_FROM_DEVICE); 619 620 dev_kfree_skb(rd_info->skb); 621 622 kfree(desc->rd_info); 623 } 624} 625 626static void device_init_td0_ring(struct vnt_private *priv) 627{ 628 int i; 629 dma_addr_t curr; 630 struct vnt_tx_desc *desc; 631 632 curr = priv->td0_pool_dma; 633 for (i = 0; i < priv->opts.tx_descs[0]; 634 i++, curr += sizeof(struct vnt_tx_desc)) { 635 desc = &priv->apTD0Rings[i]; 636 desc->td_info = kzalloc(sizeof(*desc->td_info), GFP_ATOMIC); 637 638 desc->td_info->buf = priv->tx0_bufs + i * PKT_BUF_SZ; 639 desc->td_info->buf_dma = priv->tx_bufs_dma0 + i * PKT_BUF_SZ; 640 641 desc->next = &(priv->apTD0Rings[(i+1) % priv->opts.tx_descs[0]]); 642 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_tx_desc)); 643 } 644 645 if (i > 0) 646 priv->apTD0Rings[i-1].next_desc = cpu_to_le32(priv->td0_pool_dma); 647 priv->apTailTD[0] = priv->apCurrTD[0] = &priv->apTD0Rings[0]; 648} 649 650static void device_init_td1_ring(struct vnt_private *priv) 651{ 652 int i; 653 dma_addr_t curr; 654 struct vnt_tx_desc *desc; 655 656 /* Init the TD ring entries */ 657 curr = priv->td1_pool_dma; 658 for (i = 0; i < priv->opts.tx_descs[1]; 659 i++, curr += sizeof(struct vnt_tx_desc)) { 660 desc = &priv->apTD1Rings[i]; 661 desc->td_info = kzalloc(sizeof(*desc->td_info), GFP_ATOMIC); 662 663 desc->td_info->buf = priv->tx1_bufs + i * PKT_BUF_SZ; 664 desc->td_info->buf_dma = priv->tx_bufs_dma1 + i * PKT_BUF_SZ; 665 666 desc->next = &(priv->apTD1Rings[(i + 1) % priv->opts.tx_descs[1]]); 667 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_tx_desc)); 668 } 669 670 if (i > 0) 671 priv->apTD1Rings[i-1].next_desc = cpu_to_le32(priv->td1_pool_dma); 672 priv->apTailTD[1] = priv->apCurrTD[1] = &priv->apTD1Rings[0]; 673} 674 675static void device_free_td0_ring(struct vnt_private *priv) 676{ 677 int i; 678 679 for (i = 0; i < priv->opts.tx_descs[0]; i++) { 680 struct vnt_tx_desc *desc = &priv->apTD0Rings[i]; 681 struct vnt_td_info *td_info = desc->td_info; 682 683 dev_kfree_skb(td_info->skb); 684 kfree(desc->td_info); 685 } 686} 687 688static void device_free_td1_ring(struct vnt_private *priv) 689{ 690 int i; 691 692 for (i = 0; i < priv->opts.tx_descs[1]; i++) { 693 struct vnt_tx_desc *desc = &priv->apTD1Rings[i]; 694 struct vnt_td_info *td_info = desc->td_info; 695 696 dev_kfree_skb(td_info->skb); 697 kfree(desc->td_info); 698 } 699} 700 701/*-----------------------------------------------------------------*/ 702 703static int device_rx_srv(struct vnt_private *priv, unsigned int idx) 704{ 705 struct vnt_rx_desc *rd; 706 int works = 0; 707 708 for (rd = priv->pCurrRD[idx]; 709 rd->rd0.owner == OWNED_BY_HOST; 710 rd = rd->next) { 711 if (works++ > 15) 712 break; 713 714 if (!rd->rd_info->skb) 715 break; 716 717 if (vnt_receive_frame(priv, rd)) { 718 if (!device_alloc_rx_buf(priv, rd)) { 719 dev_err(&priv->pcid->dev, 720 "can not allocate rx buf\n"); 721 break; 722 } 723 } 724 rd->rd0.owner = OWNED_BY_NIC; 725 } 726 727 priv->pCurrRD[idx] = rd; 728 729 return works; 730} 731 732static bool device_alloc_rx_buf(struct vnt_private *priv, 733 struct vnt_rx_desc *rd) 734{ 735 struct vnt_rd_info *rd_info = rd->rd_info; 736 737 rd_info->skb = dev_alloc_skb((int)priv->rx_buf_sz); 738 if (rd_info->skb == NULL) 739 return false; 740 741 rd_info->skb_dma = 742 dma_map_single(&priv->pcid->dev, 743 skb_put(rd_info->skb, skb_tailroom(rd_info->skb)), 744 priv->rx_buf_sz, DMA_FROM_DEVICE); 745 746 *((unsigned int *)&rd->rd0) = 0; /* FIX cast */ 747 748 rd->rd0.res_count = cpu_to_le16(priv->rx_buf_sz); 749 rd->rd0.owner = OWNED_BY_NIC; 750 rd->rd1.req_count = cpu_to_le16(priv->rx_buf_sz); 751 rd->buff_addr = cpu_to_le32(rd_info->skb_dma); 752 753 return true; 754} 755 756static const u8 fallback_rate0[5][5] = { 757 {RATE_18M, RATE_18M, RATE_12M, RATE_12M, RATE_12M}, 758 {RATE_24M, RATE_24M, RATE_18M, RATE_12M, RATE_12M}, 759 {RATE_36M, RATE_36M, RATE_24M, RATE_18M, RATE_18M}, 760 {RATE_48M, RATE_48M, RATE_36M, RATE_24M, RATE_24M}, 761 {RATE_54M, RATE_54M, RATE_48M, RATE_36M, RATE_36M} 762}; 763 764static const u8 fallback_rate1[5][5] = { 765 {RATE_18M, RATE_18M, RATE_12M, RATE_6M, RATE_6M}, 766 {RATE_24M, RATE_24M, RATE_18M, RATE_6M, RATE_6M}, 767 {RATE_36M, RATE_36M, RATE_24M, RATE_12M, RATE_12M}, 768 {RATE_48M, RATE_48M, RATE_24M, RATE_12M, RATE_12M}, 769 {RATE_54M, RATE_54M, RATE_36M, RATE_18M, RATE_18M} 770}; 771 772static int vnt_int_report_rate(struct vnt_private *priv, 773 struct vnt_td_info *context, u8 tsr0, u8 tsr1) 774{ 775 struct vnt_tx_fifo_head *fifo_head; 776 struct ieee80211_tx_info *info; 777 struct ieee80211_rate *rate; 778 u16 fb_option; 779 u8 tx_retry = (tsr0 & TSR0_NCR); 780 s8 idx; 781 782 if (!context) 783 return -ENOMEM; 784 785 if (!context->skb) 786 return -EINVAL; 787 788 fifo_head = (struct vnt_tx_fifo_head *)context->buf; 789 fb_option = (le16_to_cpu(fifo_head->fifo_ctl) & 790 (FIFOCTL_AUTO_FB_0 | FIFOCTL_AUTO_FB_1)); 791 792 info = IEEE80211_SKB_CB(context->skb); 793 idx = info->control.rates[0].idx; 794 795 if (fb_option && !(tsr1 & TSR1_TERR)) { 796 u8 tx_rate; 797 u8 retry = tx_retry; 798 799 rate = ieee80211_get_tx_rate(priv->hw, info); 800 tx_rate = rate->hw_value - RATE_18M; 801 802 if (retry > 4) 803 retry = 4; 804 805 if (fb_option & FIFOCTL_AUTO_FB_0) 806 tx_rate = fallback_rate0[tx_rate][retry]; 807 else if (fb_option & FIFOCTL_AUTO_FB_1) 808 tx_rate = fallback_rate1[tx_rate][retry]; 809 810 if (info->band == IEEE80211_BAND_5GHZ) 811 idx = tx_rate - RATE_6M; 812 else 813 idx = tx_rate; 814 } 815 816 ieee80211_tx_info_clear_status(info); 817 818 info->status.rates[0].count = tx_retry; 819 820 if (!(tsr1 & TSR1_TERR)) { 821 info->status.rates[0].idx = idx; 822 823 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 824 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 825 else 826 info->flags |= IEEE80211_TX_STAT_ACK; 827 } 828 829 return 0; 830} 831 832static int device_tx_srv(struct vnt_private *priv, unsigned int idx) 833{ 834 struct vnt_tx_desc *desc; 835 int works = 0; 836 unsigned char byTsr0; 837 unsigned char byTsr1; 838 839 for (desc = priv->apTailTD[idx]; priv->iTDUsed[idx] > 0; desc = desc->next) { 840 if (desc->td0.owner == OWNED_BY_NIC) 841 break; 842 if (works++ > 15) 843 break; 844 845 byTsr0 = desc->td0.tsr0; 846 byTsr1 = desc->td0.tsr1; 847 848 /* Only the status of first TD in the chain is correct */ 849 if (desc->td1.tcr & TCR_STP) { 850 if ((desc->td_info->flags & TD_FLAGS_NETIF_SKB) != 0) { 851 if (!(byTsr1 & TSR1_TERR)) { 852 if (byTsr0 != 0) { 853 pr_debug(" Tx[%d] OK but has error. tsr1[%02X] tsr0[%02X]\n", 854 (int)idx, byTsr1, 855 byTsr0); 856 } 857 } else { 858 pr_debug(" Tx[%d] dropped & tsr1[%02X] tsr0[%02X]\n", 859 (int)idx, byTsr1, byTsr0); 860 } 861 } 862 863 if (byTsr1 & TSR1_TERR) { 864 if ((desc->td_info->flags & TD_FLAGS_PRIV_SKB) != 0) { 865 pr_debug(" Tx[%d] fail has error. tsr1[%02X] tsr0[%02X]\n", 866 (int)idx, byTsr1, byTsr0); 867 } 868 } 869 870 vnt_int_report_rate(priv, desc->td_info, byTsr0, byTsr1); 871 872 device_free_tx_buf(priv, desc); 873 priv->iTDUsed[idx]--; 874 } 875 } 876 877 priv->apTailTD[idx] = desc; 878 879 return works; 880} 881 882static void device_error(struct vnt_private *priv, unsigned short status) 883{ 884 if (status & ISR_FETALERR) { 885 dev_err(&priv->pcid->dev, "Hardware fatal error\n"); 886 887 MACbShutdown(priv->PortOffset); 888 return; 889 } 890} 891 892static void device_free_tx_buf(struct vnt_private *priv, 893 struct vnt_tx_desc *desc) 894{ 895 struct vnt_td_info *td_info = desc->td_info; 896 struct sk_buff *skb = td_info->skb; 897 898 if (skb) 899 ieee80211_tx_status_irqsafe(priv->hw, skb); 900 901 td_info->skb = NULL; 902 td_info->flags = 0; 903} 904 905static void vnt_check_bb_vga(struct vnt_private *priv) 906{ 907 long dbm; 908 int i; 909 910 if (!priv->bUpdateBBVGA) 911 return; 912 913 if (priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 914 return; 915 916 if (!(priv->vif->bss_conf.assoc && priv->uCurrRSSI)) 917 return; 918 919 RFvRSSITodBm(priv, (u8)priv->uCurrRSSI, &dbm); 920 921 for (i = 0; i < BB_VGA_LEVEL; i++) { 922 if (dbm < priv->ldBmThreshold[i]) { 923 priv->byBBVGANew = priv->abyBBVGA[i]; 924 break; 925 } 926 } 927 928 if (priv->byBBVGANew == priv->byBBVGACurrent) { 929 priv->uBBVGADiffCount = 1; 930 return; 931 } 932 933 priv->uBBVGADiffCount++; 934 935 if (priv->uBBVGADiffCount == 1) { 936 /* first VGA diff gain */ 937 BBvSetVGAGainOffset(priv, priv->byBBVGANew); 938 939 dev_dbg(&priv->pcid->dev, 940 "First RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n", 941 (int)dbm, priv->byBBVGANew, 942 priv->byBBVGACurrent, 943 (int)priv->uBBVGADiffCount); 944 } 945 946 if (priv->uBBVGADiffCount >= BB_VGA_CHANGE_THRESHOLD) { 947 dev_dbg(&priv->pcid->dev, 948 "RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n", 949 (int)dbm, priv->byBBVGANew, 950 priv->byBBVGACurrent, 951 (int)priv->uBBVGADiffCount); 952 953 BBvSetVGAGainOffset(priv, priv->byBBVGANew); 954 } 955} 956 957static void vnt_interrupt_process(struct vnt_private *priv) 958{ 959 struct ieee80211_low_level_stats *low_stats = &priv->low_stats; 960 int max_count = 0; 961 u32 mib_counter; 962 u32 isr; 963 unsigned long flags; 964 965 MACvReadISR(priv->PortOffset, &isr); 966 967 if (isr == 0) 968 return; 969 970 if (isr == 0xffffffff) { 971 pr_debug("isr = 0xffff\n"); 972 return; 973 } 974 975 MACvIntDisable(priv->PortOffset); 976 977 spin_lock_irqsave(&priv->lock, flags); 978 979 /* Read low level stats */ 980 MACvReadMIBCounter(priv->PortOffset, &mib_counter); 981 982 low_stats->dot11RTSSuccessCount += mib_counter & 0xff; 983 low_stats->dot11RTSFailureCount += (mib_counter >> 8) & 0xff; 984 low_stats->dot11ACKFailureCount += (mib_counter >> 16) & 0xff; 985 low_stats->dot11FCSErrorCount += (mib_counter >> 24) & 0xff; 986 987 /* 988 * TBD.... 989 * Must do this after doing rx/tx, cause ISR bit is slow 990 * than RD/TD write back 991 * update ISR counter 992 */ 993 while (isr && priv->vif) { 994 MACvWriteISR(priv->PortOffset, isr); 995 996 if (isr & ISR_FETALERR) { 997 pr_debug(" ISR_FETALERR\n"); 998 VNSvOutPortB(priv->PortOffset + MAC_REG_SOFTPWRCTL, 0); 999 VNSvOutPortW(priv->PortOffset + 1000 MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI); 1001 device_error(priv, isr); 1002 } 1003 1004 if (isr & ISR_TBTT) { 1005 if (priv->op_mode != NL80211_IFTYPE_ADHOC) 1006 vnt_check_bb_vga(priv); 1007 1008 priv->bBeaconSent = false; 1009 if (priv->bEnablePSMode) 1010 PSbIsNextTBTTWakeUp((void *)priv); 1011 1012 if ((priv->op_mode == NL80211_IFTYPE_AP || 1013 priv->op_mode == NL80211_IFTYPE_ADHOC) && 1014 priv->vif->bss_conf.enable_beacon) { 1015 MACvOneShotTimer1MicroSec(priv->PortOffset, 1016 (priv->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10); 1017 } 1018 1019 /* TODO: adhoc PS mode */ 1020 1021 } 1022 1023 if (isr & ISR_BNTX) { 1024 if (priv->op_mode == NL80211_IFTYPE_ADHOC) { 1025 priv->bIsBeaconBufReadySet = false; 1026 priv->cbBeaconBufReadySetCnt = 0; 1027 } 1028 1029 priv->bBeaconSent = true; 1030 } 1031 1032 if (isr & ISR_RXDMA0) 1033 max_count += device_rx_srv(priv, TYPE_RXDMA0); 1034 1035 if (isr & ISR_RXDMA1) 1036 max_count += device_rx_srv(priv, TYPE_RXDMA1); 1037 1038 if (isr & ISR_TXDMA0) 1039 max_count += device_tx_srv(priv, TYPE_TXDMA0); 1040 1041 if (isr & ISR_AC0DMA) 1042 max_count += device_tx_srv(priv, TYPE_AC0DMA); 1043 1044 if (isr & ISR_SOFTTIMER1) { 1045 if (priv->vif->bss_conf.enable_beacon) 1046 vnt_beacon_make(priv, priv->vif); 1047 } 1048 1049 /* If both buffers available wake the queue */ 1050 if (AVAIL_TD(priv, TYPE_TXDMA0) && 1051 AVAIL_TD(priv, TYPE_AC0DMA) && 1052 ieee80211_queue_stopped(priv->hw, 0)) 1053 ieee80211_wake_queues(priv->hw); 1054 1055 MACvReadISR(priv->PortOffset, &isr); 1056 1057 MACvReceive0(priv->PortOffset); 1058 MACvReceive1(priv->PortOffset); 1059 1060 if (max_count > priv->opts.int_works) 1061 break; 1062 } 1063 1064 spin_unlock_irqrestore(&priv->lock, flags); 1065 1066 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE); 1067} 1068 1069static void vnt_interrupt_work(struct work_struct *work) 1070{ 1071 struct vnt_private *priv = 1072 container_of(work, struct vnt_private, interrupt_work); 1073 1074 if (priv->vif) 1075 vnt_interrupt_process(priv); 1076} 1077 1078static irqreturn_t vnt_interrupt(int irq, void *arg) 1079{ 1080 struct vnt_private *priv = arg; 1081 1082 if (priv->vif) 1083 schedule_work(&priv->interrupt_work); 1084 1085 return IRQ_HANDLED; 1086} 1087 1088static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) 1089{ 1090 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1091 struct vnt_tx_desc *head_td; 1092 u32 dma_idx; 1093 unsigned long flags; 1094 1095 spin_lock_irqsave(&priv->lock, flags); 1096 1097 if (ieee80211_is_data(hdr->frame_control)) 1098 dma_idx = TYPE_AC0DMA; 1099 else 1100 dma_idx = TYPE_TXDMA0; 1101 1102 if (AVAIL_TD(priv, dma_idx) < 1) { 1103 spin_unlock_irqrestore(&priv->lock, flags); 1104 ieee80211_stop_queues(priv->hw); 1105 return -ENOMEM; 1106 } 1107 1108 head_td = priv->apCurrTD[dma_idx]; 1109 1110 head_td->td1.tcr = 0; 1111 1112 head_td->td_info->skb = skb; 1113 1114 if (dma_idx == TYPE_AC0DMA) 1115 head_td->td_info->flags = TD_FLAGS_NETIF_SKB; 1116 1117 priv->apCurrTD[dma_idx] = head_td->next; 1118 1119 spin_unlock_irqrestore(&priv->lock, flags); 1120 1121 vnt_generate_fifo_header(priv, dma_idx, head_td, skb); 1122 1123 spin_lock_irqsave(&priv->lock, flags); 1124 1125 priv->bPWBitOn = false; 1126 1127 /* Set TSR1 & ReqCount in TxDescHead */ 1128 head_td->td1.tcr |= (TCR_STP | TCR_EDP | EDMSDU); 1129 head_td->td1.req_count = cpu_to_le16(head_td->td_info->req_count); 1130 1131 head_td->buff_addr = cpu_to_le32(head_td->td_info->buf_dma); 1132 1133 /* Poll Transmit the adapter */ 1134 wmb(); 1135 head_td->td0.owner = OWNED_BY_NIC; 1136 wmb(); /* second memory barrier */ 1137 1138 if (head_td->td_info->flags & TD_FLAGS_NETIF_SKB) 1139 MACvTransmitAC0(priv->PortOffset); 1140 else 1141 MACvTransmit0(priv->PortOffset); 1142 1143 priv->iTDUsed[dma_idx]++; 1144 1145 spin_unlock_irqrestore(&priv->lock, flags); 1146 1147 return 0; 1148} 1149 1150static void vnt_tx_80211(struct ieee80211_hw *hw, 1151 struct ieee80211_tx_control *control, 1152 struct sk_buff *skb) 1153{ 1154 struct vnt_private *priv = hw->priv; 1155 1156 if (vnt_tx_packet(priv, skb)) 1157 ieee80211_free_txskb(hw, skb); 1158} 1159 1160static int vnt_start(struct ieee80211_hw *hw) 1161{ 1162 struct vnt_private *priv = hw->priv; 1163 int ret; 1164 1165 priv->rx_buf_sz = PKT_BUF_SZ; 1166 if (!device_init_rings(priv)) 1167 return -ENOMEM; 1168 1169 ret = request_irq(priv->pcid->irq, &vnt_interrupt, 1170 IRQF_SHARED, "vt6655", priv); 1171 if (ret) { 1172 dev_dbg(&priv->pcid->dev, "failed to start irq\n"); 1173 return ret; 1174 } 1175 1176 dev_dbg(&priv->pcid->dev, "call device init rd0 ring\n"); 1177 device_init_rd0_ring(priv); 1178 device_init_rd1_ring(priv); 1179 device_init_td0_ring(priv); 1180 device_init_td1_ring(priv); 1181 1182 device_init_registers(priv); 1183 1184 dev_dbg(&priv->pcid->dev, "call MACvIntEnable\n"); 1185 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE); 1186 1187 ieee80211_wake_queues(hw); 1188 1189 return 0; 1190} 1191 1192static void vnt_stop(struct ieee80211_hw *hw) 1193{ 1194 struct vnt_private *priv = hw->priv; 1195 1196 ieee80211_stop_queues(hw); 1197 1198 cancel_work_sync(&priv->interrupt_work); 1199 1200 MACbShutdown(priv->PortOffset); 1201 MACbSoftwareReset(priv->PortOffset); 1202 CARDbRadioPowerOff(priv); 1203 1204 device_free_td0_ring(priv); 1205 device_free_td1_ring(priv); 1206 device_free_rd0_ring(priv); 1207 device_free_rd1_ring(priv); 1208 device_free_rings(priv); 1209 1210 free_irq(priv->pcid->irq, priv); 1211} 1212 1213static int vnt_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1214{ 1215 struct vnt_private *priv = hw->priv; 1216 1217 priv->vif = vif; 1218 1219 switch (vif->type) { 1220 case NL80211_IFTYPE_STATION: 1221 break; 1222 case NL80211_IFTYPE_ADHOC: 1223 MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST); 1224 1225 MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC); 1226 1227 break; 1228 case NL80211_IFTYPE_AP: 1229 MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST); 1230 1231 MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP); 1232 1233 break; 1234 default: 1235 return -EOPNOTSUPP; 1236 } 1237 1238 priv->op_mode = vif->type; 1239 1240 return 0; 1241} 1242 1243static void vnt_remove_interface(struct ieee80211_hw *hw, 1244 struct ieee80211_vif *vif) 1245{ 1246 struct vnt_private *priv = hw->priv; 1247 1248 switch (vif->type) { 1249 case NL80211_IFTYPE_STATION: 1250 break; 1251 case NL80211_IFTYPE_ADHOC: 1252 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX); 1253 MACvRegBitsOff(priv->PortOffset, 1254 MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); 1255 MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC); 1256 break; 1257 case NL80211_IFTYPE_AP: 1258 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX); 1259 MACvRegBitsOff(priv->PortOffset, 1260 MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); 1261 MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP); 1262 break; 1263 default: 1264 break; 1265 } 1266 1267 priv->op_mode = NL80211_IFTYPE_UNSPECIFIED; 1268} 1269 1270 1271static int vnt_config(struct ieee80211_hw *hw, u32 changed) 1272{ 1273 struct vnt_private *priv = hw->priv; 1274 struct ieee80211_conf *conf = &hw->conf; 1275 u8 bb_type; 1276 1277 if (changed & IEEE80211_CONF_CHANGE_PS) { 1278 if (conf->flags & IEEE80211_CONF_PS) 1279 PSvEnablePowerSaving(priv, conf->listen_interval); 1280 else 1281 PSvDisablePowerSaving(priv); 1282 } 1283 1284 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || 1285 (conf->flags & IEEE80211_CONF_OFFCHANNEL)) { 1286 set_channel(priv, conf->chandef.chan); 1287 1288 if (conf->chandef.chan->band == IEEE80211_BAND_5GHZ) 1289 bb_type = BB_TYPE_11A; 1290 else 1291 bb_type = BB_TYPE_11G; 1292 1293 if (priv->byBBType != bb_type) { 1294 priv->byBBType = bb_type; 1295 1296 CARDbSetPhyParameter(priv, priv->byBBType); 1297 } 1298 } 1299 1300 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1301 if (priv->byBBType == BB_TYPE_11B) 1302 priv->wCurrentRate = RATE_1M; 1303 else 1304 priv->wCurrentRate = RATE_54M; 1305 1306 RFbSetPower(priv, priv->wCurrentRate, 1307 conf->chandef.chan->hw_value); 1308 } 1309 1310 return 0; 1311} 1312 1313static void vnt_bss_info_changed(struct ieee80211_hw *hw, 1314 struct ieee80211_vif *vif, struct ieee80211_bss_conf *conf, 1315 u32 changed) 1316{ 1317 struct vnt_private *priv = hw->priv; 1318 1319 priv->current_aid = conf->aid; 1320 1321 if (changed & BSS_CHANGED_BSSID && conf->bssid) { 1322 unsigned long flags; 1323 1324 spin_lock_irqsave(&priv->lock, flags); 1325 1326 MACvWriteBSSIDAddress(priv->PortOffset, (u8 *)conf->bssid); 1327 1328 spin_unlock_irqrestore(&priv->lock, flags); 1329 } 1330 1331 if (changed & BSS_CHANGED_BASIC_RATES) { 1332 priv->basic_rates = conf->basic_rates; 1333 1334 CARDvUpdateBasicTopRate(priv); 1335 1336 dev_dbg(&priv->pcid->dev, 1337 "basic rates %x\n", conf->basic_rates); 1338 } 1339 1340 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1341 if (conf->use_short_preamble) { 1342 MACvEnableBarkerPreambleMd(priv->PortOffset); 1343 priv->byPreambleType = true; 1344 } else { 1345 MACvDisableBarkerPreambleMd(priv->PortOffset); 1346 priv->byPreambleType = false; 1347 } 1348 } 1349 1350 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1351 if (conf->use_cts_prot) 1352 MACvEnableProtectMD(priv->PortOffset); 1353 else 1354 MACvDisableProtectMD(priv->PortOffset); 1355 } 1356 1357 if (changed & BSS_CHANGED_ERP_SLOT) { 1358 if (conf->use_short_slot) 1359 priv->bShortSlotTime = true; 1360 else 1361 priv->bShortSlotTime = false; 1362 1363 CARDbSetPhyParameter(priv, priv->byBBType); 1364 BBvSetVGAGainOffset(priv, priv->abyBBVGA[0]); 1365 } 1366 1367 if (changed & BSS_CHANGED_TXPOWER) 1368 RFbSetPower(priv, priv->wCurrentRate, 1369 conf->chandef.chan->hw_value); 1370 1371 if (changed & BSS_CHANGED_BEACON_ENABLED) { 1372 dev_dbg(&priv->pcid->dev, 1373 "Beacon enable %d\n", conf->enable_beacon); 1374 1375 if (conf->enable_beacon) { 1376 vnt_beacon_enable(priv, vif, conf); 1377 1378 MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR, 1379 TCR_AUTOBCNTX); 1380 } else { 1381 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, 1382 TCR_AUTOBCNTX); 1383 } 1384 } 1385 1386 if (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INFO) && 1387 priv->op_mode != NL80211_IFTYPE_AP) { 1388 if (conf->assoc && conf->beacon_rate) { 1389 CARDbUpdateTSF(priv, conf->beacon_rate->hw_value, 1390 conf->sync_tsf); 1391 1392 CARDbSetBeaconPeriod(priv, conf->beacon_int); 1393 1394 CARDvSetFirstNextTBTT(priv, conf->beacon_int); 1395 } else { 1396 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, 1397 TFTCTL_TSFCNTRST); 1398 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, 1399 TFTCTL_TSFCNTREN); 1400 } 1401 } 1402} 1403 1404static u64 vnt_prepare_multicast(struct ieee80211_hw *hw, 1405 struct netdev_hw_addr_list *mc_list) 1406{ 1407 struct vnt_private *priv = hw->priv; 1408 struct netdev_hw_addr *ha; 1409 u64 mc_filter = 0; 1410 u32 bit_nr = 0; 1411 1412 netdev_hw_addr_list_for_each(ha, mc_list) { 1413 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1414 1415 mc_filter |= 1ULL << (bit_nr & 0x3f); 1416 } 1417 1418 priv->mc_list_count = mc_list->count; 1419 1420 return mc_filter; 1421} 1422 1423static void vnt_configure(struct ieee80211_hw *hw, 1424 unsigned int changed_flags, unsigned int *total_flags, u64 multicast) 1425{ 1426 struct vnt_private *priv = hw->priv; 1427 u8 rx_mode = 0; 1428 1429 *total_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC; 1430 1431 VNSvInPortB(priv->PortOffset + MAC_REG_RCR, &rx_mode); 1432 1433 dev_dbg(&priv->pcid->dev, "rx mode in = %x\n", rx_mode); 1434 1435 if (changed_flags & FIF_ALLMULTI) { 1436 if (*total_flags & FIF_ALLMULTI) { 1437 unsigned long flags; 1438 1439 spin_lock_irqsave(&priv->lock, flags); 1440 1441 if (priv->mc_list_count > 2) { 1442 MACvSelectPage1(priv->PortOffset); 1443 1444 VNSvOutPortD(priv->PortOffset + 1445 MAC_REG_MAR0, 0xffffffff); 1446 VNSvOutPortD(priv->PortOffset + 1447 MAC_REG_MAR0 + 4, 0xffffffff); 1448 1449 MACvSelectPage0(priv->PortOffset); 1450 } else { 1451 MACvSelectPage1(priv->PortOffset); 1452 1453 VNSvOutPortD(priv->PortOffset + 1454 MAC_REG_MAR0, (u32)multicast); 1455 VNSvOutPortD(priv->PortOffset + 1456 MAC_REG_MAR0 + 4, 1457 (u32)(multicast >> 32)); 1458 1459 MACvSelectPage0(priv->PortOffset); 1460 } 1461 1462 spin_unlock_irqrestore(&priv->lock, flags); 1463 1464 rx_mode |= RCR_MULTICAST | RCR_BROADCAST; 1465 } else { 1466 rx_mode &= ~(RCR_MULTICAST | RCR_BROADCAST); 1467 } 1468 } 1469 1470 if (changed_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC)) { 1471 rx_mode |= RCR_MULTICAST | RCR_BROADCAST; 1472 1473 if (*total_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC)) 1474 rx_mode &= ~RCR_BSSID; 1475 else 1476 rx_mode |= RCR_BSSID; 1477 } 1478 1479 VNSvOutPortB(priv->PortOffset + MAC_REG_RCR, rx_mode); 1480 1481 dev_dbg(&priv->pcid->dev, "rx mode out= %x\n", rx_mode); 1482} 1483 1484static int vnt_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 1485 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 1486 struct ieee80211_key_conf *key) 1487{ 1488 struct vnt_private *priv = hw->priv; 1489 1490 switch (cmd) { 1491 case SET_KEY: 1492 if (vnt_set_keys(hw, sta, vif, key)) 1493 return -EOPNOTSUPP; 1494 break; 1495 case DISABLE_KEY: 1496 if (test_bit(key->hw_key_idx, &priv->key_entry_inuse)) 1497 clear_bit(key->hw_key_idx, &priv->key_entry_inuse); 1498 default: 1499 break; 1500 } 1501 1502 return 0; 1503} 1504 1505static int vnt_get_stats(struct ieee80211_hw *hw, 1506 struct ieee80211_low_level_stats *stats) 1507{ 1508 struct vnt_private *priv = hw->priv; 1509 1510 memcpy(stats, &priv->low_stats, sizeof(*stats)); 1511 1512 return 0; 1513} 1514 1515static u64 vnt_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1516{ 1517 struct vnt_private *priv = hw->priv; 1518 u64 tsf; 1519 1520 CARDbGetCurrentTSF(priv, &tsf); 1521 1522 return tsf; 1523} 1524 1525static void vnt_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1526 u64 tsf) 1527{ 1528 struct vnt_private *priv = hw->priv; 1529 1530 CARDvUpdateNextTBTT(priv, tsf, vif->bss_conf.beacon_int); 1531} 1532 1533static void vnt_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1534{ 1535 struct vnt_private *priv = hw->priv; 1536 1537 /* reset TSF counter */ 1538 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); 1539} 1540 1541static const struct ieee80211_ops vnt_mac_ops = { 1542 .tx = vnt_tx_80211, 1543 .start = vnt_start, 1544 .stop = vnt_stop, 1545 .add_interface = vnt_add_interface, 1546 .remove_interface = vnt_remove_interface, 1547 .config = vnt_config, 1548 .bss_info_changed = vnt_bss_info_changed, 1549 .prepare_multicast = vnt_prepare_multicast, 1550 .configure_filter = vnt_configure, 1551 .set_key = vnt_set_key, 1552 .get_stats = vnt_get_stats, 1553 .get_tsf = vnt_get_tsf, 1554 .set_tsf = vnt_set_tsf, 1555 .reset_tsf = vnt_reset_tsf, 1556}; 1557 1558static int vnt_init(struct vnt_private *priv) 1559{ 1560 SET_IEEE80211_PERM_ADDR(priv->hw, priv->abyCurrentNetAddr); 1561 1562 vnt_init_bands(priv); 1563 1564 if (ieee80211_register_hw(priv->hw)) 1565 return -ENODEV; 1566 1567 priv->mac_hw = true; 1568 1569 CARDbRadioPowerOff(priv); 1570 1571 return 0; 1572} 1573 1574static int 1575vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent) 1576{ 1577 struct vnt_private *priv; 1578 struct ieee80211_hw *hw; 1579 struct wiphy *wiphy; 1580 int rc; 1581 1582 dev_notice(&pcid->dev, 1583 "%s Ver. %s\n", DEVICE_FULL_DRV_NAM, DEVICE_VERSION); 1584 1585 dev_notice(&pcid->dev, 1586 "Copyright (c) 2003 VIA Networking Technologies, Inc.\n"); 1587 1588 hw = ieee80211_alloc_hw(sizeof(*priv), &vnt_mac_ops); 1589 if (!hw) { 1590 dev_err(&pcid->dev, "could not register ieee80211_hw\n"); 1591 return -ENOMEM; 1592 } 1593 1594 priv = hw->priv; 1595 priv->pcid = pcid; 1596 1597 spin_lock_init(&priv->lock); 1598 1599 priv->hw = hw; 1600 1601 SET_IEEE80211_DEV(priv->hw, &pcid->dev); 1602 1603 if (pci_enable_device(pcid)) { 1604 device_free_info(priv); 1605 return -ENODEV; 1606 } 1607 1608 dev_dbg(&pcid->dev, 1609 "Before get pci_info memaddr is %x\n", priv->memaddr); 1610 1611 pci_set_master(pcid); 1612 1613 priv->memaddr = pci_resource_start(pcid, 0); 1614 priv->ioaddr = pci_resource_start(pcid, 1); 1615 priv->PortOffset = ioremap(priv->memaddr & PCI_BASE_ADDRESS_MEM_MASK, 1616 256); 1617 if (!priv->PortOffset) { 1618 dev_err(&pcid->dev, ": Failed to IO remapping ..\n"); 1619 device_free_info(priv); 1620 return -ENODEV; 1621 } 1622 1623 rc = pci_request_regions(pcid, DEVICE_NAME); 1624 if (rc) { 1625 dev_err(&pcid->dev, ": Failed to find PCI device\n"); 1626 device_free_info(priv); 1627 return -ENODEV; 1628 } 1629 1630 if (dma_set_mask(&pcid->dev, DMA_BIT_MASK(32))) { 1631 dev_err(&pcid->dev, ": Failed to set dma 32 bit mask\n"); 1632 device_free_info(priv); 1633 return -ENODEV; 1634 } 1635 1636 INIT_WORK(&priv->interrupt_work, vnt_interrupt_work); 1637 1638 /* do reset */ 1639 if (!MACbSoftwareReset(priv->PortOffset)) { 1640 dev_err(&pcid->dev, ": Failed to access MAC hardware..\n"); 1641 device_free_info(priv); 1642 return -ENODEV; 1643 } 1644 /* initial to reload eeprom */ 1645 MACvInitialize(priv->PortOffset); 1646 MACvReadEtherAddress(priv->PortOffset, priv->abyCurrentNetAddr); 1647 1648 /* Get RFType */ 1649 priv->byRFType = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_RFTYPE); 1650 priv->byRFType &= RF_MASK; 1651 1652 dev_dbg(&pcid->dev, "RF Type = %x\n", priv->byRFType); 1653 1654 device_get_options(priv); 1655 device_set_options(priv); 1656 1657 wiphy = priv->hw->wiphy; 1658 1659 wiphy->frag_threshold = FRAG_THRESH_DEF; 1660 wiphy->rts_threshold = RTS_THRESH_DEF; 1661 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1662 BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); 1663 1664 ieee80211_hw_set(priv->hw, TIMING_BEACON_ONLY); 1665 ieee80211_hw_set(priv->hw, SIGNAL_DBM); 1666 ieee80211_hw_set(priv->hw, RX_INCLUDES_FCS); 1667 ieee80211_hw_set(priv->hw, REPORTS_TX_ACK_STATUS); 1668 ieee80211_hw_set(priv->hw, SUPPORTS_PS); 1669 1670 priv->hw->max_signal = 100; 1671 1672 if (vnt_init(priv)) 1673 return -ENODEV; 1674 1675 device_print_info(priv); 1676 pci_set_drvdata(pcid, priv); 1677 1678 return 0; 1679} 1680 1681/*------------------------------------------------------------------*/ 1682 1683#ifdef CONFIG_PM 1684static int vt6655_suspend(struct pci_dev *pcid, pm_message_t state) 1685{ 1686 struct vnt_private *priv = pci_get_drvdata(pcid); 1687 unsigned long flags; 1688 1689 spin_lock_irqsave(&priv->lock, flags); 1690 1691 pci_save_state(pcid); 1692 1693 MACbShutdown(priv->PortOffset); 1694 1695 pci_disable_device(pcid); 1696 pci_set_power_state(pcid, pci_choose_state(pcid, state)); 1697 1698 spin_unlock_irqrestore(&priv->lock, flags); 1699 1700 return 0; 1701} 1702 1703static int vt6655_resume(struct pci_dev *pcid) 1704{ 1705 1706 pci_set_power_state(pcid, PCI_D0); 1707 pci_enable_wake(pcid, PCI_D0, 0); 1708 pci_restore_state(pcid); 1709 1710 return 0; 1711} 1712#endif 1713 1714MODULE_DEVICE_TABLE(pci, vt6655_pci_id_table); 1715 1716static struct pci_driver device_driver = { 1717 .name = DEVICE_NAME, 1718 .id_table = vt6655_pci_id_table, 1719 .probe = vt6655_probe, 1720 .remove = vt6655_remove, 1721#ifdef CONFIG_PM 1722 .suspend = vt6655_suspend, 1723 .resume = vt6655_resume, 1724#endif 1725}; 1726 1727module_pci_driver(device_driver); 1728