1#ifndef DDK750_SII164_H__ 2#define DDK750_SII164_H__ 3 4#define USE_DVICHIP 5 6/* Hot Plug detection mode structure */ 7typedef enum _sii164_hot_plug_mode_t { 8 SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */ 9 SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */ 10 SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */ 11 SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */ 12} sii164_hot_plug_mode_t; 13 14 15/* Silicon Image SiI164 chip prototype */ 16long sii164InitChip( 17 unsigned char edgeSelect, 18 unsigned char busSelect, 19 unsigned char dualEdgeClkSelect, 20 unsigned char hsyncEnable, 21 unsigned char vsyncEnable, 22 unsigned char deskewEnable, 23 unsigned char deskewSetting, 24 unsigned char continuousSyncEnable, 25 unsigned char pllFilterEnable, 26 unsigned char pllFilterValue 27); 28 29unsigned short sii164GetVendorID(void); 30unsigned short sii164GetDeviceID(void); 31 32 33#ifdef SII164_FULL_FUNCTIONS 34void sii164ResetChip(void); 35char *sii164GetChipString(void); 36void sii164SetPower(unsigned char powerUp); 37void sii164EnableHotPlugDetection(unsigned char enableHotPlug); 38unsigned char sii164IsConnected(void); 39unsigned char sii164CheckInterrupt(void); 40void sii164ClearInterrupt(void); 41#endif 42/* below register definination is used for Silicon Image SiI164 DVI controller chip */ 43/* 44 * Vendor ID registers 45 */ 46#define SII164_VENDOR_ID_LOW 0x00 47#define SII164_VENDOR_ID_HIGH 0x01 48 49/* 50 * Device ID registers 51 */ 52#define SII164_DEVICE_ID_LOW 0x02 53#define SII164_DEVICE_ID_HIGH 0x03 54 55/* 56 * Device Revision 57 */ 58#define SII164_DEVICE_REVISION 0x04 59 60/* 61 * Frequency Limitation registers 62 */ 63#define SII164_FREQUENCY_LIMIT_LOW 0x06 64#define SII164_FREQUENCY_LIMIT_HIGH 0x07 65 66/* 67 * Power Down and Input Signal Configuration registers 68 */ 69#define SII164_CONFIGURATION 0x08 70 71/* Power down (PD) */ 72#define SII164_CONFIGURATION_POWER_DOWN 0x00 73#define SII164_CONFIGURATION_POWER_NORMAL 0x01 74#define SII164_CONFIGURATION_POWER_MASK 0x01 75 76/* Input Edge Latch Select (EDGE) */ 77#define SII164_CONFIGURATION_LATCH_FALLING 0x00 78#define SII164_CONFIGURATION_LATCH_RISING 0x02 79 80/* Bus Select (BSEL) */ 81#define SII164_CONFIGURATION_BUS_12BITS 0x00 82#define SII164_CONFIGURATION_BUS_24BITS 0x04 83 84/* Dual Edge Clock Select (DSEL) */ 85#define SII164_CONFIGURATION_CLOCK_SINGLE 0x00 86#define SII164_CONFIGURATION_CLOCK_DUAL 0x08 87 88/* Horizontal Sync Enable (HEN) */ 89#define SII164_CONFIGURATION_HSYNC_FORCE_LOW 0x00 90#define SII164_CONFIGURATION_HSYNC_AS_IS 0x10 91 92/* Vertical Sync Enable (VEN) */ 93#define SII164_CONFIGURATION_VSYNC_FORCE_LOW 0x00 94#define SII164_CONFIGURATION_VSYNC_AS_IS 0x20 95 96/* 97 * Detection registers 98 */ 99#define SII164_DETECT 0x09 100 101/* Monitor Detect Interrupt (MDI) */ 102#define SII164_DETECT_MONITOR_STATE_CHANGE 0x00 103#define SII164_DETECT_MONITOR_STATE_NO_CHANGE 0x01 104#define SII164_DETECT_MONITOR_STATE_CLEAR 0x01 105#define SII164_DETECT_MONITOR_STATE_MASK 0x01 106 107/* Hot Plug detect Input (HTPLG) */ 108#define SII164_DETECT_HOT_PLUG_STATUS_OFF 0x00 109#define SII164_DETECT_HOT_PLUG_STATUS_ON 0x02 110#define SII164_DETECT_HOT_PLUG_STATUS_MASK 0x02 111 112/* Receiver Sense (RSEN) */ 113#define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED 0x00 114#define SII164_DETECT_RECEIVER_SENSE_DETECTED 0x04 115 116/* Interrupt Generation Method (TSEL) */ 117#define SII164_DETECT_INTERRUPT_BY_RSEN_PIN 0x00 118#define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN 0x08 119#define SII164_DETECT_INTERRUPT_MASK 0x08 120 121/* Monitor Sense Output (MSEN) */ 122#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH 0x00 123#define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI 0x10 124#define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN 0x20 125#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG 0x30 126#define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG 0x30 127 128/* 129 * Skewing registers 130 */ 131#define SII164_DESKEW 0x0A 132 133/* General Purpose Input (CTL[3:1]) */ 134#define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK 0x0E 135 136/* De-skewing Enable bit (DKEN) */ 137#define SII164_DESKEW_DISABLE 0x00 138#define SII164_DESKEW_ENABLE 0x10 139 140/* De-skewing Setting (DK[3:1])*/ 141#define SII164_DESKEW_1_STEP 0x00 142#define SII164_DESKEW_2_STEP 0x20 143#define SII164_DESKEW_3_STEP 0x40 144#define SII164_DESKEW_4_STEP 0x60 145#define SII164_DESKEW_5_STEP 0x80 146#define SII164_DESKEW_6_STEP 0xA0 147#define SII164_DESKEW_7_STEP 0xC0 148#define SII164_DESKEW_8_STEP 0xE0 149 150/* 151 * User Configuration Data registers (CFG 7:0) 152 */ 153#define SII164_USER_CONFIGURATION 0x0B 154 155/* 156 * PLL registers 157 */ 158#define SII164_PLL 0x0C 159 160/* PLL Filter Value (PLLF) */ 161#define SII164_PLL_FILTER_VALUE_MASK 0x0E 162 163/* PLL Filter Enable (PFEN) */ 164#define SII164_PLL_FILTER_DISABLE 0x00 165#define SII164_PLL_FILTER_ENABLE 0x01 166 167/* Sync Continuous (SCNT) */ 168#define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE 0x00 169#define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE 0x80 170 171#endif 172