1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23#include <linux/blkdev.h> 24#include <linux/kthread.h> 25#include <linux/sched.h> 26 27#include "rtsx.h" 28#include "spi.h" 29 30static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) 31{ 32 struct spi_info *spi = &(chip->spi); 33 34 spi->err_code = err_code; 35} 36 37static int spi_init(struct rtsx_chip *chip) 38{ 39 int retval; 40 41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 42 CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 | SPI_AUTO); 43 if (retval) { 44 rtsx_trace(chip); 45 return retval; 46 } 47 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 48 SAMPLE_DELAY_HALF); 49 if (retval) { 50 rtsx_trace(chip); 51 return retval; 52 } 53 54 return STATUS_SUCCESS; 55} 56 57static int spi_set_init_para(struct rtsx_chip *chip) 58{ 59 struct spi_info *spi = &(chip->spi); 60 int retval; 61 62 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 63 (u8)(spi->clk_div >> 8)); 64 if (retval) { 65 rtsx_trace(chip); 66 return retval; 67 } 68 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 69 (u8)(spi->clk_div)); 70 if (retval) { 71 rtsx_trace(chip); 72 return retval; 73 } 74 75 retval = switch_clock(chip, spi->spi_clock); 76 if (retval != STATUS_SUCCESS) { 77 rtsx_trace(chip); 78 return STATUS_FAIL; 79 } 80 81 retval = select_card(chip, SPI_CARD); 82 if (retval != STATUS_SUCCESS) { 83 rtsx_trace(chip); 84 return STATUS_FAIL; 85 } 86 87 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 88 SPI_CLK_EN); 89 if (retval) { 90 rtsx_trace(chip); 91 return retval; 92 } 93 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 94 SPI_OUTPUT_EN); 95 if (retval) { 96 rtsx_trace(chip); 97 return retval; 98 } 99 100 wait_timeout(10); 101 102 retval = spi_init(chip); 103 if (retval != STATUS_SUCCESS) { 104 rtsx_trace(chip); 105 return STATUS_FAIL; 106 } 107 108 return STATUS_SUCCESS; 109} 110 111static int sf_polling_status(struct rtsx_chip *chip, int msec) 112{ 113 int retval; 114 115 rtsx_init_cmd(chip); 116 117 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); 118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 119 SPI_TRANSFER0_START | SPI_POLLING_MODE0); 120 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 121 SPI_TRANSFER0_END); 122 123 retval = rtsx_send_cmd(chip, 0, msec); 124 if (retval < 0) { 125 rtsx_clear_spi_error(chip); 126 spi_set_err_code(chip, SPI_BUSY_ERR); 127 rtsx_trace(chip); 128 return STATUS_FAIL; 129 } 130 131 return STATUS_SUCCESS; 132} 133 134static int sf_enable_write(struct rtsx_chip *chip, u8 ins) 135{ 136 struct spi_info *spi = &(chip->spi); 137 int retval; 138 139 if (!spi->write_en) 140 return STATUS_SUCCESS; 141 142 rtsx_init_cmd(chip); 143 144 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 145 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 146 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 147 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 148 SPI_TRANSFER0_START | SPI_C_MODE0); 149 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 150 SPI_TRANSFER0_END); 151 152 retval = rtsx_send_cmd(chip, 0, 100); 153 if (retval < 0) { 154 rtsx_clear_spi_error(chip); 155 spi_set_err_code(chip, SPI_HW_ERR); 156 rtsx_trace(chip); 157 return STATUS_FAIL; 158 } 159 160 return STATUS_SUCCESS; 161} 162 163static int sf_disable_write(struct rtsx_chip *chip, u8 ins) 164{ 165 struct spi_info *spi = &(chip->spi); 166 int retval; 167 168 if (!spi->write_en) 169 return STATUS_SUCCESS; 170 171 rtsx_init_cmd(chip); 172 173 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 174 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 175 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 176 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 177 SPI_TRANSFER0_START | SPI_C_MODE0); 178 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 179 SPI_TRANSFER0_END); 180 181 retval = rtsx_send_cmd(chip, 0, 100); 182 if (retval < 0) { 183 rtsx_clear_spi_error(chip); 184 spi_set_err_code(chip, SPI_HW_ERR); 185 rtsx_trace(chip); 186 return STATUS_FAIL; 187 } 188 189 return STATUS_SUCCESS; 190} 191 192static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr, 193 u16 len) 194{ 195 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 196 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 197 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 198 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len); 199 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8)); 200 if (addr_mode) { 201 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 202 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 203 (u8)(addr >> 8)); 204 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 205 (u8)(addr >> 16)); 206 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 207 SPI_TRANSFER0_START | SPI_CADO_MODE0); 208 } else { 209 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 210 SPI_TRANSFER0_START | SPI_CDO_MODE0); 211 } 212 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 213 SPI_TRANSFER0_END); 214} 215 216static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr) 217{ 218 int retval; 219 220 rtsx_init_cmd(chip); 221 222 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 223 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 224 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 225 if (addr_mode) { 226 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 227 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 228 (u8)(addr >> 8)); 229 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 230 (u8)(addr >> 16)); 231 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 232 SPI_TRANSFER0_START | SPI_CA_MODE0); 233 } else { 234 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 235 SPI_TRANSFER0_START | SPI_C_MODE0); 236 } 237 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 238 SPI_TRANSFER0_END); 239 240 retval = rtsx_send_cmd(chip, 0, 100); 241 if (retval < 0) { 242 rtsx_clear_spi_error(chip); 243 spi_set_err_code(chip, SPI_HW_ERR); 244 rtsx_trace(chip); 245 return STATUS_FAIL; 246 } 247 248 return STATUS_SUCCESS; 249} 250 251static int spi_init_eeprom(struct rtsx_chip *chip) 252{ 253 int retval; 254 int clk; 255 256 if (chip->asic_code) 257 clk = 30; 258 else 259 clk = CLK_30; 260 261 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); 262 if (retval) { 263 rtsx_trace(chip); 264 return retval; 265 } 266 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); 267 if (retval) { 268 rtsx_trace(chip); 269 return retval; 270 } 271 272 retval = switch_clock(chip, clk); 273 if (retval != STATUS_SUCCESS) { 274 rtsx_trace(chip); 275 return STATUS_FAIL; 276 } 277 278 retval = select_card(chip, SPI_CARD); 279 if (retval != STATUS_SUCCESS) { 280 rtsx_trace(chip); 281 return STATUS_FAIL; 282 } 283 284 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 285 SPI_CLK_EN); 286 if (retval) { 287 rtsx_trace(chip); 288 return retval; 289 } 290 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 291 SPI_OUTPUT_EN); 292 if (retval) { 293 rtsx_trace(chip); 294 return retval; 295 } 296 297 wait_timeout(10); 298 299 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 300 CS_POLARITY_HIGH | SPI_EEPROM_AUTO); 301 if (retval) { 302 rtsx_trace(chip); 303 return retval; 304 } 305 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 306 SAMPLE_DELAY_HALF); 307 if (retval) { 308 rtsx_trace(chip); 309 return retval; 310 } 311 312 return STATUS_SUCCESS; 313} 314 315static int spi_eeprom_program_enable(struct rtsx_chip *chip) 316{ 317 int retval; 318 319 rtsx_init_cmd(chip); 320 321 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86); 322 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13); 323 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 324 SPI_TRANSFER0_START | SPI_CA_MODE0); 325 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 326 SPI_TRANSFER0_END); 327 328 retval = rtsx_send_cmd(chip, 0, 100); 329 if (retval < 0) { 330 rtsx_trace(chip); 331 return STATUS_FAIL; 332 } 333 334 return STATUS_SUCCESS; 335} 336 337int spi_erase_eeprom_chip(struct rtsx_chip *chip) 338{ 339 int retval; 340 341 retval = spi_init_eeprom(chip); 342 if (retval != STATUS_SUCCESS) { 343 rtsx_trace(chip); 344 return STATUS_FAIL; 345 } 346 347 retval = spi_eeprom_program_enable(chip); 348 if (retval != STATUS_SUCCESS) { 349 rtsx_trace(chip); 350 return STATUS_FAIL; 351 } 352 353 rtsx_init_cmd(chip); 354 355 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 356 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 357 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12); 358 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84); 359 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 360 SPI_TRANSFER0_START | SPI_CA_MODE0); 361 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 362 SPI_TRANSFER0_END); 363 364 retval = rtsx_send_cmd(chip, 0, 100); 365 if (retval < 0) { 366 rtsx_trace(chip); 367 return STATUS_FAIL; 368 } 369 370 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 371 if (retval) { 372 rtsx_trace(chip); 373 return retval; 374 } 375 376 return STATUS_SUCCESS; 377} 378 379int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) 380{ 381 int retval; 382 383 retval = spi_init_eeprom(chip); 384 if (retval != STATUS_SUCCESS) { 385 rtsx_trace(chip); 386 return STATUS_FAIL; 387 } 388 389 retval = spi_eeprom_program_enable(chip); 390 if (retval != STATUS_SUCCESS) { 391 rtsx_trace(chip); 392 return STATUS_FAIL; 393 } 394 395 rtsx_init_cmd(chip); 396 397 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 398 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 399 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07); 400 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 401 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 402 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 403 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 404 SPI_TRANSFER0_START | SPI_CA_MODE0); 405 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 406 SPI_TRANSFER0_END); 407 408 retval = rtsx_send_cmd(chip, 0, 100); 409 if (retval < 0) { 410 rtsx_trace(chip); 411 return STATUS_FAIL; 412 } 413 414 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 415 if (retval) { 416 rtsx_trace(chip); 417 return retval; 418 } 419 420 return STATUS_SUCCESS; 421} 422 423 424int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) 425{ 426 int retval; 427 u8 data; 428 429 retval = spi_init_eeprom(chip); 430 if (retval != STATUS_SUCCESS) { 431 rtsx_trace(chip); 432 return STATUS_FAIL; 433 } 434 435 rtsx_init_cmd(chip); 436 437 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 438 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 439 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06); 440 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 441 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 442 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 443 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 444 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 445 SPI_TRANSFER0_START | SPI_CADI_MODE0); 446 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 447 SPI_TRANSFER0_END); 448 449 retval = rtsx_send_cmd(chip, 0, 100); 450 if (retval < 0) { 451 rtsx_trace(chip); 452 return STATUS_FAIL; 453 } 454 455 wait_timeout(5); 456 retval = rtsx_read_register(chip, SPI_DATA, &data); 457 if (retval) { 458 rtsx_trace(chip); 459 return retval; 460 } 461 462 if (val) 463 *val = data; 464 465 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 466 if (retval) { 467 rtsx_trace(chip); 468 return retval; 469 } 470 471 return STATUS_SUCCESS; 472} 473 474int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) 475{ 476 int retval; 477 478 retval = spi_init_eeprom(chip); 479 if (retval != STATUS_SUCCESS) { 480 rtsx_trace(chip); 481 return STATUS_FAIL; 482 } 483 484 retval = spi_eeprom_program_enable(chip); 485 if (retval != STATUS_SUCCESS) { 486 rtsx_trace(chip); 487 return STATUS_FAIL; 488 } 489 490 rtsx_init_cmd(chip); 491 492 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 493 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 494 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05); 495 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); 496 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr); 497 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8)); 498 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E); 499 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 500 SPI_TRANSFER0_START | SPI_CA_MODE0); 501 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 502 SPI_TRANSFER0_END); 503 504 retval = rtsx_send_cmd(chip, 0, 100); 505 if (retval < 0) { 506 rtsx_trace(chip); 507 return STATUS_FAIL; 508 } 509 510 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 511 if (retval) { 512 rtsx_trace(chip); 513 return retval; 514 } 515 516 return STATUS_SUCCESS; 517} 518 519 520int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 521{ 522 struct spi_info *spi = &(chip->spi); 523 524 dev_dbg(rtsx_dev(chip), "spi_get_status: err_code = 0x%x\n", 525 spi->err_code); 526 rtsx_stor_set_xfer_buf(&(spi->err_code), 527 min_t(int, scsi_bufflen(srb), 1), srb); 528 scsi_set_resid(srb, scsi_bufflen(srb) - 1); 529 530 return STATUS_SUCCESS; 531} 532 533int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) 534{ 535 struct spi_info *spi = &(chip->spi); 536 537 spi_set_err_code(chip, SPI_NO_ERR); 538 539 if (chip->asic_code) 540 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; 541 else 542 spi->spi_clock = srb->cmnd[3]; 543 544 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 545 spi->write_en = srb->cmnd[6]; 546 547 dev_dbg(rtsx_dev(chip), "spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n", 548 spi->spi_clock, spi->clk_div, spi->write_en); 549 550 return STATUS_SUCCESS; 551} 552 553int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 554{ 555 int retval; 556 u16 len; 557 u8 *buf; 558 559 spi_set_err_code(chip, SPI_NO_ERR); 560 561 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 562 if (len > 512) { 563 spi_set_err_code(chip, SPI_INVALID_COMMAND); 564 rtsx_trace(chip); 565 return STATUS_FAIL; 566 } 567 568 retval = spi_set_init_para(chip); 569 if (retval != STATUS_SUCCESS) { 570 spi_set_err_code(chip, SPI_HW_ERR); 571 rtsx_trace(chip); 572 return STATUS_FAIL; 573 } 574 575 rtsx_init_cmd(chip); 576 577 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 578 PINGPONG_BUFFER); 579 580 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]); 581 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]); 582 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]); 583 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]); 584 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 585 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 586 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]); 587 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]); 588 589 if (len == 0) { 590 if (srb->cmnd[9]) { 591 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 592 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0); 593 } else { 594 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 595 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); 596 } 597 } else { 598 if (srb->cmnd[9]) { 599 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 600 SPI_TRANSFER0_START | SPI_CADI_MODE0); 601 } else { 602 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 603 SPI_TRANSFER0_START | SPI_CDI_MODE0); 604 } 605 } 606 607 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 608 SPI_TRANSFER0_END); 609 610 retval = rtsx_send_cmd(chip, 0, 100); 611 if (retval < 0) { 612 rtsx_clear_spi_error(chip); 613 spi_set_err_code(chip, SPI_HW_ERR); 614 rtsx_trace(chip); 615 return STATUS_FAIL; 616 } 617 618 if (len) { 619 buf = kmalloc(len, GFP_KERNEL); 620 if (!buf) { 621 rtsx_trace(chip); 622 return STATUS_ERROR; 623 } 624 625 retval = rtsx_read_ppbuf(chip, buf, len); 626 if (retval != STATUS_SUCCESS) { 627 spi_set_err_code(chip, SPI_READ_ERR); 628 kfree(buf); 629 rtsx_trace(chip); 630 return STATUS_FAIL; 631 } 632 633 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 634 scsi_set_resid(srb, 0); 635 636 kfree(buf); 637 } 638 639 return STATUS_SUCCESS; 640} 641 642int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 643{ 644 int retval; 645 unsigned int index = 0, offset = 0; 646 u8 ins, slow_read; 647 u32 addr; 648 u16 len; 649 u8 *buf; 650 651 spi_set_err_code(chip, SPI_NO_ERR); 652 653 ins = srb->cmnd[3]; 654 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 655 << 8) | srb->cmnd[6]; 656 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 657 slow_read = srb->cmnd[9]; 658 659 retval = spi_set_init_para(chip); 660 if (retval != STATUS_SUCCESS) { 661 spi_set_err_code(chip, SPI_HW_ERR); 662 rtsx_trace(chip); 663 return STATUS_FAIL; 664 } 665 666 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 667 if (buf == NULL) { 668 rtsx_trace(chip); 669 return STATUS_ERROR; 670 } 671 672 while (len) { 673 u16 pagelen = SF_PAGE_LEN - (u8)addr; 674 675 if (pagelen > len) 676 pagelen = len; 677 678 rtsx_init_cmd(chip); 679 680 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256); 681 682 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 683 684 if (slow_read) { 685 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, 686 (u8)addr); 687 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 688 (u8)(addr >> 8)); 689 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 690 (u8)(addr >> 16)); 691 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 692 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 693 } else { 694 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 695 (u8)addr); 696 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 697 (u8)(addr >> 8)); 698 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF, 699 (u8)(addr >> 16)); 700 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 701 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32); 702 } 703 704 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 705 (u8)(pagelen >> 8)); 706 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 707 (u8)pagelen); 708 709 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 710 SPI_TRANSFER0_START | SPI_CADI_MODE0); 711 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, 712 SPI_TRANSFER0_END, SPI_TRANSFER0_END); 713 714 rtsx_send_cmd_no_wait(chip); 715 716 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 717 DMA_FROM_DEVICE, 10000); 718 if (retval < 0) { 719 kfree(buf); 720 rtsx_clear_spi_error(chip); 721 spi_set_err_code(chip, SPI_HW_ERR); 722 rtsx_trace(chip); 723 return STATUS_FAIL; 724 } 725 726 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset, 727 TO_XFER_BUF); 728 729 addr += pagelen; 730 len -= pagelen; 731 } 732 733 scsi_set_resid(srb, 0); 734 kfree(buf); 735 736 return STATUS_SUCCESS; 737} 738 739int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 740{ 741 int retval; 742 u8 ins, program_mode; 743 u32 addr; 744 u16 len; 745 u8 *buf; 746 unsigned int index = 0, offset = 0; 747 748 spi_set_err_code(chip, SPI_NO_ERR); 749 750 ins = srb->cmnd[3]; 751 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 752 << 8) | srb->cmnd[6]; 753 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 754 program_mode = srb->cmnd[9]; 755 756 retval = spi_set_init_para(chip); 757 if (retval != STATUS_SUCCESS) { 758 spi_set_err_code(chip, SPI_HW_ERR); 759 rtsx_trace(chip); 760 return STATUS_FAIL; 761 } 762 763 if (program_mode == BYTE_PROGRAM) { 764 buf = kmalloc(4, GFP_KERNEL); 765 if (!buf) { 766 rtsx_trace(chip); 767 return STATUS_ERROR; 768 } 769 770 while (len) { 771 retval = sf_enable_write(chip, SPI_WREN); 772 if (retval != STATUS_SUCCESS) { 773 kfree(buf); 774 rtsx_trace(chip); 775 return STATUS_FAIL; 776 } 777 778 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 779 FROM_XFER_BUF); 780 781 rtsx_init_cmd(chip); 782 783 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 784 0x01, PINGPONG_BUFFER); 785 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 786 buf[0]); 787 sf_program(chip, ins, 1, addr, 1); 788 789 retval = rtsx_send_cmd(chip, 0, 100); 790 if (retval < 0) { 791 kfree(buf); 792 rtsx_clear_spi_error(chip); 793 spi_set_err_code(chip, SPI_HW_ERR); 794 rtsx_trace(chip); 795 return STATUS_FAIL; 796 } 797 798 retval = sf_polling_status(chip, 100); 799 if (retval != STATUS_SUCCESS) { 800 kfree(buf); 801 rtsx_trace(chip); 802 return STATUS_FAIL; 803 } 804 805 addr++; 806 len--; 807 } 808 809 kfree(buf); 810 811 } else if (program_mode == AAI_PROGRAM) { 812 int first_byte = 1; 813 814 retval = sf_enable_write(chip, SPI_WREN); 815 if (retval != STATUS_SUCCESS) { 816 rtsx_trace(chip); 817 return STATUS_FAIL; 818 } 819 820 buf = kmalloc(4, GFP_KERNEL); 821 if (!buf) { 822 rtsx_trace(chip); 823 return STATUS_ERROR; 824 } 825 826 while (len) { 827 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 828 FROM_XFER_BUF); 829 830 rtsx_init_cmd(chip); 831 832 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 833 0x01, PINGPONG_BUFFER); 834 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 835 buf[0]); 836 if (first_byte) { 837 sf_program(chip, ins, 1, addr, 1); 838 first_byte = 0; 839 } else { 840 sf_program(chip, ins, 0, 0, 1); 841 } 842 843 retval = rtsx_send_cmd(chip, 0, 100); 844 if (retval < 0) { 845 kfree(buf); 846 rtsx_clear_spi_error(chip); 847 spi_set_err_code(chip, SPI_HW_ERR); 848 rtsx_trace(chip); 849 return STATUS_FAIL; 850 } 851 852 retval = sf_polling_status(chip, 100); 853 if (retval != STATUS_SUCCESS) { 854 kfree(buf); 855 rtsx_trace(chip); 856 return STATUS_FAIL; 857 } 858 859 len--; 860 } 861 862 kfree(buf); 863 864 retval = sf_disable_write(chip, SPI_WRDI); 865 if (retval != STATUS_SUCCESS) { 866 rtsx_trace(chip); 867 return STATUS_FAIL; 868 } 869 870 retval = sf_polling_status(chip, 100); 871 if (retval != STATUS_SUCCESS) { 872 rtsx_trace(chip); 873 return STATUS_FAIL; 874 } 875 } else if (program_mode == PAGE_PROGRAM) { 876 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 877 if (!buf) { 878 rtsx_trace(chip); 879 return STATUS_NOMEM; 880 } 881 882 while (len) { 883 u16 pagelen = SF_PAGE_LEN - (u8)addr; 884 885 if (pagelen > len) 886 pagelen = len; 887 888 retval = sf_enable_write(chip, SPI_WREN); 889 if (retval != STATUS_SUCCESS) { 890 kfree(buf); 891 rtsx_trace(chip); 892 return STATUS_FAIL; 893 } 894 895 rtsx_init_cmd(chip); 896 897 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256); 898 sf_program(chip, ins, 1, addr, pagelen); 899 900 rtsx_send_cmd_no_wait(chip); 901 902 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, 903 &offset, FROM_XFER_BUF); 904 905 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 906 DMA_TO_DEVICE, 100); 907 if (retval < 0) { 908 kfree(buf); 909 rtsx_clear_spi_error(chip); 910 spi_set_err_code(chip, SPI_HW_ERR); 911 rtsx_trace(chip); 912 return STATUS_FAIL; 913 } 914 915 retval = sf_polling_status(chip, 100); 916 if (retval != STATUS_SUCCESS) { 917 kfree(buf); 918 rtsx_trace(chip); 919 return STATUS_FAIL; 920 } 921 922 addr += pagelen; 923 len -= pagelen; 924 } 925 926 kfree(buf); 927 } else { 928 spi_set_err_code(chip, SPI_INVALID_COMMAND); 929 rtsx_trace(chip); 930 return STATUS_FAIL; 931 } 932 933 return STATUS_SUCCESS; 934} 935 936int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 937{ 938 int retval; 939 u8 ins, erase_mode; 940 u32 addr; 941 942 spi_set_err_code(chip, SPI_NO_ERR); 943 944 ins = srb->cmnd[3]; 945 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 946 << 8) | srb->cmnd[6]; 947 erase_mode = srb->cmnd[9]; 948 949 retval = spi_set_init_para(chip); 950 if (retval != STATUS_SUCCESS) { 951 spi_set_err_code(chip, SPI_HW_ERR); 952 rtsx_trace(chip); 953 return STATUS_FAIL; 954 } 955 956 if (erase_mode == PAGE_ERASE) { 957 retval = sf_enable_write(chip, SPI_WREN); 958 if (retval != STATUS_SUCCESS) { 959 rtsx_trace(chip); 960 return STATUS_FAIL; 961 } 962 963 retval = sf_erase(chip, ins, 1, addr); 964 if (retval != STATUS_SUCCESS) { 965 rtsx_trace(chip); 966 return STATUS_FAIL; 967 } 968 } else if (erase_mode == CHIP_ERASE) { 969 retval = sf_enable_write(chip, SPI_WREN); 970 if (retval != STATUS_SUCCESS) { 971 rtsx_trace(chip); 972 return STATUS_FAIL; 973 } 974 975 retval = sf_erase(chip, ins, 0, 0); 976 if (retval != STATUS_SUCCESS) { 977 rtsx_trace(chip); 978 return STATUS_FAIL; 979 } 980 } else { 981 spi_set_err_code(chip, SPI_INVALID_COMMAND); 982 rtsx_trace(chip); 983 return STATUS_FAIL; 984 } 985 986 return STATUS_SUCCESS; 987} 988 989int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 990{ 991 int retval; 992 u8 ins, status, ewsr; 993 994 ins = srb->cmnd[3]; 995 status = srb->cmnd[4]; 996 ewsr = srb->cmnd[5]; 997 998 retval = spi_set_init_para(chip); 999 if (retval != STATUS_SUCCESS) { 1000 spi_set_err_code(chip, SPI_HW_ERR); 1001 rtsx_trace(chip); 1002 return STATUS_FAIL; 1003 } 1004 1005 retval = sf_enable_write(chip, ewsr); 1006 if (retval != STATUS_SUCCESS) { 1007 rtsx_trace(chip); 1008 return STATUS_FAIL; 1009 } 1010 1011 rtsx_init_cmd(chip); 1012 1013 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 1014 PINGPONG_BUFFER); 1015 1016 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 1017 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 1018 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 1019 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0); 1020 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 1021 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); 1022 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 1023 SPI_TRANSFER0_START | SPI_CDO_MODE0); 1024 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 1025 SPI_TRANSFER0_END); 1026 1027 retval = rtsx_send_cmd(chip, 0, 100); 1028 if (retval != STATUS_SUCCESS) { 1029 rtsx_clear_spi_error(chip); 1030 spi_set_err_code(chip, SPI_HW_ERR); 1031 rtsx_trace(chip); 1032 return STATUS_FAIL; 1033 } 1034 1035 return STATUS_SUCCESS; 1036} 1037