1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20#ifndef __HALPWRSEQCMD_H__
21#define __HALPWRSEQCMD_H__
22
23#include <drv_types.h>
24
25/* The value of cmd: 4 bits */
26#define PWR_CMD_READ		0x00
27#define PWR_CMD_WRITE		0x01
28#define PWR_CMD_POLLING		0x02
29#define PWR_CMD_DELAY		0x03
30#define PWR_CMD_END		0x04
31
32/* The value of base: 4 bits */
33/*  define the base address of each block */
34#define PWR_BASEADDR_MAC	0x00
35#define PWR_BASEADDR_USB	0x01
36#define PWR_BASEADDR_PCIE	0x02
37#define PWR_BASEADDR_SDIO	0x03
38
39/* The value of interface_msk: 4 bits */
40#define PWR_INTF_SDIO_MSK	BIT(0)
41#define PWR_INTF_USB_MSK	BIT(1)
42#define PWR_INTF_PCI_MSK	BIT(2)
43#define PWR_INTF_ALL_MSK	(BIT(0)|BIT(1)|BIT(2)|BIT(3))
44
45/* The value of fab_msk: 4 bits */
46#define PWR_FAB_TSMC_MSK	BIT(0)
47#define PWR_FAB_UMC_MSK		BIT(1)
48#define PWR_FAB_ALL_MSK		(BIT(0)|BIT(1)|BIT(2)|BIT(3))
49
50/* The value of cut_msk: 8 bits */
51#define PWR_CUT_TESTCHIP_MSK	BIT(0)
52#define PWR_CUT_A_MSK		BIT(1)
53#define PWR_CUT_B_MSK		BIT(2)
54#define PWR_CUT_C_MSK		BIT(3)
55#define PWR_CUT_D_MSK		BIT(4)
56#define PWR_CUT_E_MSK		BIT(5)
57#define PWR_CUT_F_MSK		BIT(6)
58#define PWR_CUT_G_MSK		BIT(7)
59#define PWR_CUT_ALL_MSK		0xFF
60
61
62enum pwrseq_cmd_delat_unit {
63	PWRSEQ_DELAY_US,
64	PWRSEQ_DELAY_MS,
65};
66
67struct wl_pwr_cfg {
68	u16 offset;
69	u8 cut_msk;
70	u8 fab_msk:4;
71	u8 interface_msk:4;
72	u8 base:4;
73	u8 cmd:4;
74	u8 msk;
75	u8 value;
76};
77
78#define GET_PWR_CFG_OFFSET(__PWR_CMD)		__PWR_CMD.offset
79#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		__PWR_CMD.cut_msk
80#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		__PWR_CMD.fab_msk
81#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	__PWR_CMD.interface_msk
82#define GET_PWR_CFG_BASE(__PWR_CMD)		__PWR_CMD.base
83#define GET_PWR_CFG_CMD(__PWR_CMD)		__PWR_CMD.cmd
84#define GET_PWR_CFG_MASK(__PWR_CMD)		__PWR_CMD.msk
85#define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value
86
87u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
88			    u8 ifacetype, struct wl_pwr_cfg pwrcfgCmd[]);
89
90#endif
91