1/* 2 * Copyright 2003 Digi International (www.digi.com) 3 * Scott H Kilau <Scott_Kilau at digi dot com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/sched.h> /* For jiffies, task states */ 18#include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */ 19#include <linux/delay.h> /* For udelay */ 20#include <linux/io.h> /* For read[bwl]/write[bwl] */ 21#include <linux/serial.h> /* For struct async_serial */ 22#include <linux/serial_reg.h> /* For the various UART offsets */ 23 24#include "dgnc_driver.h" /* Driver main header file */ 25#include "dgnc_neo.h" /* Our header file */ 26#include "dgnc_tty.h" 27 28static inline void neo_parse_lsr(struct dgnc_board *brd, uint port); 29static inline void neo_parse_isr(struct dgnc_board *brd, uint port); 30static void neo_copy_data_from_uart_to_queue(struct channel_t *ch); 31static inline void neo_clear_break(struct channel_t *ch, int force); 32static inline void neo_set_cts_flow_control(struct channel_t *ch); 33static inline void neo_set_rts_flow_control(struct channel_t *ch); 34static inline void neo_set_ixon_flow_control(struct channel_t *ch); 35static inline void neo_set_ixoff_flow_control(struct channel_t *ch); 36static inline void neo_set_no_output_flow_control(struct channel_t *ch); 37static inline void neo_set_no_input_flow_control(struct channel_t *ch); 38static inline void neo_set_new_start_stop_chars(struct channel_t *ch); 39static void neo_parse_modem(struct channel_t *ch, unsigned char signals); 40static void neo_tasklet(unsigned long data); 41static void neo_vpd(struct dgnc_board *brd); 42static void neo_uart_init(struct channel_t *ch); 43static void neo_uart_off(struct channel_t *ch); 44static int neo_drain(struct tty_struct *tty, uint seconds); 45static void neo_param(struct tty_struct *tty); 46static void neo_assert_modem_signals(struct channel_t *ch); 47static void neo_flush_uart_write(struct channel_t *ch); 48static void neo_flush_uart_read(struct channel_t *ch); 49static void neo_disable_receiver(struct channel_t *ch); 50static void neo_enable_receiver(struct channel_t *ch); 51static void neo_send_break(struct channel_t *ch, int msecs); 52static void neo_send_start_character(struct channel_t *ch); 53static void neo_send_stop_character(struct channel_t *ch); 54static void neo_copy_data_from_queue_to_uart(struct channel_t *ch); 55static uint neo_get_uart_bytes_left(struct channel_t *ch); 56static void neo_send_immediate_char(struct channel_t *ch, unsigned char c); 57static irqreturn_t neo_intr(int irq, void *voidbrd); 58 59struct board_ops dgnc_neo_ops = { 60 .tasklet = neo_tasklet, 61 .intr = neo_intr, 62 .uart_init = neo_uart_init, 63 .uart_off = neo_uart_off, 64 .drain = neo_drain, 65 .param = neo_param, 66 .vpd = neo_vpd, 67 .assert_modem_signals = neo_assert_modem_signals, 68 .flush_uart_write = neo_flush_uart_write, 69 .flush_uart_read = neo_flush_uart_read, 70 .disable_receiver = neo_disable_receiver, 71 .enable_receiver = neo_enable_receiver, 72 .send_break = neo_send_break, 73 .send_start_character = neo_send_start_character, 74 .send_stop_character = neo_send_stop_character, 75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 76 .get_uart_bytes_left = neo_get_uart_bytes_left, 77 .send_immediate_char = neo_send_immediate_char 78}; 79 80static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 81 82/* 83 * This function allows calls to ensure that all outstanding 84 * PCI writes have been completed, by doing a PCI read against 85 * a non-destructive, read-only location on the Neo card. 86 * 87 * In this case, we are reading the DVID (Read-only Device Identification) 88 * value of the Neo card. 89 */ 90static inline void neo_pci_posting_flush(struct dgnc_board *bd) 91{ 92 readb(bd->re_map_membase + 0x8D); 93} 94 95static inline void neo_set_cts_flow_control(struct channel_t *ch) 96{ 97 unsigned char ier = readb(&ch->ch_neo_uart->ier); 98 unsigned char efr = readb(&ch->ch_neo_uart->efr); 99 100 /* Turn on auto CTS flow control */ 101#if 1 102 ier |= UART_17158_IER_CTSDSR; 103#else 104 ier &= ~(UART_17158_IER_CTSDSR); 105#endif 106 107 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 108 109 /* Turn off auto Xon flow control */ 110 efr &= ~UART_17158_EFR_IXON; 111 112 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 113 writeb(0, &ch->ch_neo_uart->efr); 114 115 /* Turn on UART enhanced bits */ 116 writeb(efr, &ch->ch_neo_uart->efr); 117 118 /* Turn on table D, with 8 char hi/low watermarks */ 119 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 120 121 /* Feed the UART our trigger levels */ 122 writeb(8, &ch->ch_neo_uart->tfifo); 123 ch->ch_t_tlevel = 8; 124 125 writeb(ier, &ch->ch_neo_uart->ier); 126 127 neo_pci_posting_flush(ch->ch_bd); 128} 129 130static inline void neo_set_rts_flow_control(struct channel_t *ch) 131{ 132 unsigned char ier = readb(&ch->ch_neo_uart->ier); 133 unsigned char efr = readb(&ch->ch_neo_uart->efr); 134 135 /* Turn on auto RTS flow control */ 136#if 1 137 ier |= UART_17158_IER_RTSDTR; 138#else 139 ier &= ~(UART_17158_IER_RTSDTR); 140#endif 141 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 142 143 /* Turn off auto Xoff flow control */ 144 ier &= ~UART_17158_IER_XOFF; 145 efr &= ~UART_17158_EFR_IXOFF; 146 147 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 148 writeb(0, &ch->ch_neo_uart->efr); 149 150 /* Turn on UART enhanced bits */ 151 writeb(efr, &ch->ch_neo_uart->efr); 152 153 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 154 ch->ch_r_watermark = 4; 155 156 writeb(32, &ch->ch_neo_uart->rfifo); 157 ch->ch_r_tlevel = 32; 158 159 writeb(ier, &ch->ch_neo_uart->ier); 160 161 /* 162 * From the Neo UART spec sheet: 163 * The auto RTS/DTR function must be started by asserting 164 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 165 * it is enabled. 166 */ 167 ch->ch_mostat |= UART_MCR_RTS; 168 169 neo_pci_posting_flush(ch->ch_bd); 170} 171 172static inline void neo_set_ixon_flow_control(struct channel_t *ch) 173{ 174 unsigned char ier = readb(&ch->ch_neo_uart->ier); 175 unsigned char efr = readb(&ch->ch_neo_uart->efr); 176 177 /* Turn off auto CTS flow control */ 178 ier &= ~UART_17158_IER_CTSDSR; 179 efr &= ~UART_17158_EFR_CTSDSR; 180 181 /* Turn on auto Xon flow control */ 182 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 183 184 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 185 writeb(0, &ch->ch_neo_uart->efr); 186 187 /* Turn on UART enhanced bits */ 188 writeb(efr, &ch->ch_neo_uart->efr); 189 190 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 191 ch->ch_r_watermark = 4; 192 193 writeb(32, &ch->ch_neo_uart->rfifo); 194 ch->ch_r_tlevel = 32; 195 196 /* Tell UART what start/stop chars it should be looking for */ 197 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 198 writeb(0, &ch->ch_neo_uart->xonchar2); 199 200 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 201 writeb(0, &ch->ch_neo_uart->xoffchar2); 202 203 writeb(ier, &ch->ch_neo_uart->ier); 204 205 neo_pci_posting_flush(ch->ch_bd); 206} 207 208static inline void neo_set_ixoff_flow_control(struct channel_t *ch) 209{ 210 unsigned char ier = readb(&ch->ch_neo_uart->ier); 211 unsigned char efr = readb(&ch->ch_neo_uart->efr); 212 213 /* Turn off auto RTS flow control */ 214 ier &= ~UART_17158_IER_RTSDTR; 215 efr &= ~UART_17158_EFR_RTSDTR; 216 217 /* Turn on auto Xoff flow control */ 218 ier |= UART_17158_IER_XOFF; 219 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 220 221 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 222 writeb(0, &ch->ch_neo_uart->efr); 223 224 /* Turn on UART enhanced bits */ 225 writeb(efr, &ch->ch_neo_uart->efr); 226 227 /* Turn on table D, with 8 char hi/low watermarks */ 228 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 229 230 writeb(8, &ch->ch_neo_uart->tfifo); 231 ch->ch_t_tlevel = 8; 232 233 /* Tell UART what start/stop chars it should be looking for */ 234 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 235 writeb(0, &ch->ch_neo_uart->xonchar2); 236 237 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 238 writeb(0, &ch->ch_neo_uart->xoffchar2); 239 240 writeb(ier, &ch->ch_neo_uart->ier); 241 242 neo_pci_posting_flush(ch->ch_bd); 243} 244 245static inline void neo_set_no_input_flow_control(struct channel_t *ch) 246{ 247 unsigned char ier = readb(&ch->ch_neo_uart->ier); 248 unsigned char efr = readb(&ch->ch_neo_uart->efr); 249 250 /* Turn off auto RTS flow control */ 251 ier &= ~UART_17158_IER_RTSDTR; 252 efr &= ~UART_17158_EFR_RTSDTR; 253 254 /* Turn off auto Xoff flow control */ 255 ier &= ~UART_17158_IER_XOFF; 256 if (ch->ch_c_iflag & IXON) 257 efr &= ~(UART_17158_EFR_IXOFF); 258 else 259 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 260 261 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 262 writeb(0, &ch->ch_neo_uart->efr); 263 264 /* Turn on UART enhanced bits */ 265 writeb(efr, &ch->ch_neo_uart->efr); 266 267 /* Turn on table D, with 8 char hi/low watermarks */ 268 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 269 270 ch->ch_r_watermark = 0; 271 272 writeb(16, &ch->ch_neo_uart->tfifo); 273 ch->ch_t_tlevel = 16; 274 275 writeb(16, &ch->ch_neo_uart->rfifo); 276 ch->ch_r_tlevel = 16; 277 278 writeb(ier, &ch->ch_neo_uart->ier); 279 280 neo_pci_posting_flush(ch->ch_bd); 281} 282 283static inline void neo_set_no_output_flow_control(struct channel_t *ch) 284{ 285 unsigned char ier = readb(&ch->ch_neo_uart->ier); 286 unsigned char efr = readb(&ch->ch_neo_uart->efr); 287 288 /* Turn off auto CTS flow control */ 289 ier &= ~UART_17158_IER_CTSDSR; 290 efr &= ~UART_17158_EFR_CTSDSR; 291 292 /* Turn off auto Xon flow control */ 293 if (ch->ch_c_iflag & IXOFF) 294 efr &= ~UART_17158_EFR_IXON; 295 else 296 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 297 298 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 299 writeb(0, &ch->ch_neo_uart->efr); 300 301 /* Turn on UART enhanced bits */ 302 writeb(efr, &ch->ch_neo_uart->efr); 303 304 /* Turn on table D, with 8 char hi/low watermarks */ 305 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 306 307 ch->ch_r_watermark = 0; 308 309 writeb(16, &ch->ch_neo_uart->tfifo); 310 ch->ch_t_tlevel = 16; 311 312 writeb(16, &ch->ch_neo_uart->rfifo); 313 ch->ch_r_tlevel = 16; 314 315 writeb(ier, &ch->ch_neo_uart->ier); 316 317 neo_pci_posting_flush(ch->ch_bd); 318} 319 320/* change UARTs start/stop chars */ 321static inline void neo_set_new_start_stop_chars(struct channel_t *ch) 322{ 323 /* if hardware flow control is set, then skip this whole thing */ 324 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS) 325 return; 326 327 /* Tell UART what start/stop chars it should be looking for */ 328 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 329 writeb(0, &ch->ch_neo_uart->xonchar2); 330 331 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 332 writeb(0, &ch->ch_neo_uart->xoffchar2); 333 334 neo_pci_posting_flush(ch->ch_bd); 335} 336 337/* 338 * No locks are assumed to be held when calling this function. 339 */ 340static inline void neo_clear_break(struct channel_t *ch, int force) 341{ 342 unsigned long flags; 343 344 spin_lock_irqsave(&ch->ch_lock, flags); 345 346 /* Bail if we aren't currently sending a break. */ 347 if (!ch->ch_stop_sending_break) { 348 spin_unlock_irqrestore(&ch->ch_lock, flags); 349 return; 350 } 351 352 /* Turn break off, and unset some variables */ 353 if (ch->ch_flags & CH_BREAK_SENDING) { 354 if (time_after_eq(jiffies, ch->ch_stop_sending_break) 355 || force) { 356 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 357 358 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 359 neo_pci_posting_flush(ch->ch_bd); 360 ch->ch_flags &= ~(CH_BREAK_SENDING); 361 ch->ch_stop_sending_break = 0; 362 } 363 } 364 spin_unlock_irqrestore(&ch->ch_lock, flags); 365} 366 367/* 368 * Parse the ISR register. 369 */ 370static inline void neo_parse_isr(struct dgnc_board *brd, uint port) 371{ 372 struct channel_t *ch; 373 unsigned char isr; 374 unsigned char cause; 375 unsigned long flags; 376 377 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 378 return; 379 380 if (port >= brd->maxports) 381 return; 382 383 ch = brd->channels[port]; 384 if (ch->magic != DGNC_CHANNEL_MAGIC) 385 return; 386 387 /* Here we try to figure out what caused the interrupt to happen */ 388 while (1) { 389 isr = readb(&ch->ch_neo_uart->isr_fcr); 390 391 /* Bail if no pending interrupt */ 392 if (isr & UART_IIR_NO_INT) 393 break; 394 395 /* 396 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 397 */ 398 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 399 400 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 401 /* Read data from uart -> queue */ 402 brd->intr_rx++; 403 ch->ch_intr_rx++; 404 neo_copy_data_from_uart_to_queue(ch); 405 406 /* Call our tty layer to enforce queue flow control if needed. */ 407 spin_lock_irqsave(&ch->ch_lock, flags); 408 dgnc_check_queue_flow_control(ch); 409 spin_unlock_irqrestore(&ch->ch_lock, flags); 410 } 411 412 if (isr & UART_IIR_THRI) { 413 brd->intr_tx++; 414 ch->ch_intr_tx++; 415 /* Transfer data (if any) from Write Queue -> UART. */ 416 spin_lock_irqsave(&ch->ch_lock, flags); 417 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 418 spin_unlock_irqrestore(&ch->ch_lock, flags); 419 neo_copy_data_from_queue_to_uart(ch); 420 } 421 422 if (isr & UART_17158_IIR_XONXOFF) { 423 cause = readb(&ch->ch_neo_uart->xoffchar1); 424 425 /* 426 * Since the UART detected either an XON or 427 * XOFF match, we need to figure out which 428 * one it was, so we can suspend or resume data flow. 429 */ 430 if (cause == UART_17158_XON_DETECT) { 431 /* Is output stopped right now, if so, resume it */ 432 if (brd->channels[port]->ch_flags & CH_STOP) { 433 spin_lock_irqsave(&ch->ch_lock, 434 flags); 435 ch->ch_flags &= ~(CH_STOP); 436 spin_unlock_irqrestore(&ch->ch_lock, 437 flags); 438 } 439 } else if (cause == UART_17158_XOFF_DETECT) { 440 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 441 spin_lock_irqsave(&ch->ch_lock, 442 flags); 443 ch->ch_flags |= CH_STOP; 444 spin_unlock_irqrestore(&ch->ch_lock, 445 flags); 446 } 447 } 448 } 449 450 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 451 /* 452 * If we get here, this means the hardware is doing auto flow control. 453 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 454 */ 455 brd->intr_modem++; 456 ch->ch_intr_modem++; 457 cause = readb(&ch->ch_neo_uart->mcr); 458 /* Which pin is doing auto flow? RTS or DTR? */ 459 if ((cause & 0x4) == 0) { 460 if (cause & UART_MCR_RTS) { 461 spin_lock_irqsave(&ch->ch_lock, 462 flags); 463 ch->ch_mostat |= UART_MCR_RTS; 464 spin_unlock_irqrestore(&ch->ch_lock, 465 flags); 466 } else { 467 spin_lock_irqsave(&ch->ch_lock, 468 flags); 469 ch->ch_mostat &= ~(UART_MCR_RTS); 470 spin_unlock_irqrestore(&ch->ch_lock, 471 flags); 472 } 473 } else { 474 if (cause & UART_MCR_DTR) { 475 spin_lock_irqsave(&ch->ch_lock, 476 flags); 477 ch->ch_mostat |= UART_MCR_DTR; 478 spin_unlock_irqrestore(&ch->ch_lock, 479 flags); 480 } else { 481 spin_lock_irqsave(&ch->ch_lock, 482 flags); 483 ch->ch_mostat &= ~(UART_MCR_DTR); 484 spin_unlock_irqrestore(&ch->ch_lock, 485 flags); 486 } 487 } 488 } 489 490 /* Parse any modem signal changes */ 491 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 492 } 493} 494 495static inline void neo_parse_lsr(struct dgnc_board *brd, uint port) 496{ 497 struct channel_t *ch; 498 int linestatus; 499 unsigned long flags; 500 501 /* 502 * Check to make sure it didn't receive interrupt with a null board 503 * associated or a board pointer that wasn't ours. 504 */ 505 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 506 return; 507 508 if (port >= brd->maxports) 509 return; 510 511 ch = brd->channels[port]; 512 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 513 return; 514 515 linestatus = readb(&ch->ch_neo_uart->lsr); 516 517 ch->ch_cached_lsr |= linestatus; 518 519 if (ch->ch_cached_lsr & UART_LSR_DR) { 520 brd->intr_rx++; 521 ch->ch_intr_rx++; 522 /* Read data from uart -> queue */ 523 neo_copy_data_from_uart_to_queue(ch); 524 spin_lock_irqsave(&ch->ch_lock, flags); 525 dgnc_check_queue_flow_control(ch); 526 spin_unlock_irqrestore(&ch->ch_lock, flags); 527 } 528 529 /* 530 * The next 3 tests should *NOT* happen, as the above test 531 * should encapsulate all 3... At least, thats what Exar says. 532 */ 533 534 if (linestatus & UART_LSR_PE) 535 ch->ch_err_parity++; 536 537 if (linestatus & UART_LSR_FE) 538 ch->ch_err_frame++; 539 540 if (linestatus & UART_LSR_BI) 541 ch->ch_err_break++; 542 543 if (linestatus & UART_LSR_OE) { 544 /* 545 * Rx Oruns. Exar says that an orun will NOT corrupt 546 * the FIFO. It will just replace the holding register 547 * with this new data byte. So basically just ignore this. 548 * Probably we should eventually have an orun stat in our driver... 549 */ 550 ch->ch_err_overrun++; 551 } 552 553 if (linestatus & UART_LSR_THRE) { 554 brd->intr_tx++; 555 ch->ch_intr_tx++; 556 spin_lock_irqsave(&ch->ch_lock, flags); 557 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 558 spin_unlock_irqrestore(&ch->ch_lock, flags); 559 560 /* Transfer data (if any) from Write Queue -> UART. */ 561 neo_copy_data_from_queue_to_uart(ch); 562 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 563 brd->intr_tx++; 564 ch->ch_intr_tx++; 565 spin_lock_irqsave(&ch->ch_lock, flags); 566 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 567 spin_unlock_irqrestore(&ch->ch_lock, flags); 568 569 /* Transfer data (if any) from Write Queue -> UART. */ 570 neo_copy_data_from_queue_to_uart(ch); 571 } 572} 573 574/* 575 * neo_param() 576 * Send any/all changes to the line to the UART. 577 */ 578static void neo_param(struct tty_struct *tty) 579{ 580 unsigned char lcr = 0; 581 unsigned char uart_lcr = 0; 582 unsigned char ier = 0; 583 unsigned char uart_ier = 0; 584 uint baud = 9600; 585 int quot = 0; 586 struct dgnc_board *bd; 587 struct channel_t *ch; 588 struct un_t *un; 589 590 if (!tty || tty->magic != TTY_MAGIC) 591 return; 592 593 un = (struct un_t *)tty->driver_data; 594 if (!un || un->magic != DGNC_UNIT_MAGIC) 595 return; 596 597 ch = un->un_ch; 598 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 599 return; 600 601 bd = ch->ch_bd; 602 if (!bd || bd->magic != DGNC_BOARD_MAGIC) 603 return; 604 605 /* 606 * If baud rate is zero, flush queues, and set mval to drop DTR. 607 */ 608 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 609 ch->ch_r_head = 0; 610 ch->ch_r_tail = 0; 611 ch->ch_e_head = 0; 612 ch->ch_e_tail = 0; 613 ch->ch_w_head = 0; 614 ch->ch_w_tail = 0; 615 616 neo_flush_uart_write(ch); 617 neo_flush_uart_read(ch); 618 619 /* The baudrate is B0 so all modem lines are to be dropped. */ 620 ch->ch_flags |= (CH_BAUD0); 621 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 622 neo_assert_modem_signals(ch); 623 ch->ch_old_baud = 0; 624 return; 625 626 } else if (ch->ch_custom_speed) { 627 baud = ch->ch_custom_speed; 628 /* Handle transition from B0 */ 629 if (ch->ch_flags & CH_BAUD0) { 630 ch->ch_flags &= ~(CH_BAUD0); 631 632 /* 633 * Bring back up RTS and DTR... 634 * Also handle RTS or DTR toggle if set. 635 */ 636 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 637 ch->ch_mostat |= (UART_MCR_RTS); 638 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 639 ch->ch_mostat |= (UART_MCR_DTR); 640 } 641 } else { 642 int iindex = 0; 643 int jindex = 0; 644 645 ulong bauds[4][16] = { 646 { /* slowbaud */ 647 0, 50, 75, 110, 648 134, 150, 200, 300, 649 600, 1200, 1800, 2400, 650 4800, 9600, 19200, 38400 }, 651 { /* slowbaud & CBAUDEX */ 652 0, 57600, 115200, 230400, 653 460800, 150, 200, 921600, 654 600, 1200, 1800, 2400, 655 4800, 9600, 19200, 38400 }, 656 { /* fastbaud */ 657 0, 57600, 76800, 115200, 658 131657, 153600, 230400, 460800, 659 921600, 1200, 1800, 2400, 660 4800, 9600, 19200, 38400 }, 661 { /* fastbaud & CBAUDEX */ 662 0, 57600, 115200, 230400, 663 460800, 150, 200, 921600, 664 600, 1200, 1800, 2400, 665 4800, 9600, 19200, 38400 } 666 }; 667 668 /* Only use the TXPrint baud rate if the terminal unit is NOT open */ 669 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT)) 670 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff; 671 else 672 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff; 673 674 if (ch->ch_c_cflag & CBAUDEX) 675 iindex = 1; 676 677 if (ch->ch_digi.digi_flags & DIGI_FAST) 678 iindex += 2; 679 680 jindex = baud; 681 682 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) 683 baud = bauds[iindex][jindex]; 684 else 685 baud = 0; 686 687 if (baud == 0) 688 baud = 9600; 689 690 /* Handle transition from B0 */ 691 if (ch->ch_flags & CH_BAUD0) { 692 ch->ch_flags &= ~(CH_BAUD0); 693 694 /* 695 * Bring back up RTS and DTR... 696 * Also handle RTS or DTR toggle if set. 697 */ 698 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 699 ch->ch_mostat |= (UART_MCR_RTS); 700 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 701 ch->ch_mostat |= (UART_MCR_DTR); 702 } 703 } 704 705 if (ch->ch_c_cflag & PARENB) 706 lcr |= UART_LCR_PARITY; 707 708 if (!(ch->ch_c_cflag & PARODD)) 709 lcr |= UART_LCR_EPAR; 710 711 /* 712 * Not all platforms support mark/space parity, 713 * so this will hide behind an ifdef. 714 */ 715#ifdef CMSPAR 716 if (ch->ch_c_cflag & CMSPAR) 717 lcr |= UART_LCR_SPAR; 718#endif 719 720 if (ch->ch_c_cflag & CSTOPB) 721 lcr |= UART_LCR_STOP; 722 723 switch (ch->ch_c_cflag & CSIZE) { 724 case CS5: 725 lcr |= UART_LCR_WLEN5; 726 break; 727 case CS6: 728 lcr |= UART_LCR_WLEN6; 729 break; 730 case CS7: 731 lcr |= UART_LCR_WLEN7; 732 break; 733 case CS8: 734 default: 735 lcr |= UART_LCR_WLEN8; 736 break; 737 } 738 739 uart_ier = readb(&ch->ch_neo_uart->ier); 740 ier = uart_ier; 741 742 uart_lcr = readb(&ch->ch_neo_uart->lcr); 743 744 if (baud == 0) 745 baud = 9600; 746 747 quot = ch->ch_bd->bd_dividend / baud; 748 749 if (quot != 0 && ch->ch_old_baud != baud) { 750 ch->ch_old_baud = baud; 751 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 752 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 753 writeb((quot >> 8), &ch->ch_neo_uart->ier); 754 writeb(lcr, &ch->ch_neo_uart->lcr); 755 } 756 757 if (uart_lcr != lcr) 758 writeb(lcr, &ch->ch_neo_uart->lcr); 759 760 if (ch->ch_c_cflag & CREAD) 761 ier |= (UART_IER_RDI | UART_IER_RLSI); 762 else 763 ier &= ~(UART_IER_RDI | UART_IER_RLSI); 764 765 /* 766 * Have the UART interrupt on modem signal changes ONLY when 767 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set. 768 */ 769 if ((ch->ch_digi.digi_flags & CTSPACE) || 770 (ch->ch_digi.digi_flags & RTSPACE) || 771 (ch->ch_c_cflag & CRTSCTS) || 772 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) || 773 !(ch->ch_c_cflag & CLOCAL)) 774 ier |= UART_IER_MSI; 775 else 776 ier &= ~UART_IER_MSI; 777 778 ier |= UART_IER_THRI; 779 780 if (ier != uart_ier) 781 writeb(ier, &ch->ch_neo_uart->ier); 782 783 /* Set new start/stop chars */ 784 neo_set_new_start_stop_chars(ch); 785 786 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) { 787 neo_set_cts_flow_control(ch); 788 } else if (ch->ch_c_iflag & IXON) { 789 /* If start/stop is set to disable, then we should disable flow control */ 790 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE)) 791 neo_set_no_output_flow_control(ch); 792 else 793 neo_set_ixon_flow_control(ch); 794 } else { 795 neo_set_no_output_flow_control(ch); 796 } 797 798 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) { 799 neo_set_rts_flow_control(ch); 800 } else if (ch->ch_c_iflag & IXOFF) { 801 /* If start/stop is set to disable, then we should disable flow control */ 802 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE)) 803 neo_set_no_input_flow_control(ch); 804 else 805 neo_set_ixoff_flow_control(ch); 806 } else { 807 neo_set_no_input_flow_control(ch); 808 } 809 810 /* 811 * Adjust the RX FIFO Trigger level if baud is less than 9600. 812 * Not exactly elegant, but this is needed because of the Exar chip's 813 * delay on firing off the RX FIFO interrupt on slower baud rates. 814 */ 815 if (baud < 9600) { 816 writeb(1, &ch->ch_neo_uart->rfifo); 817 ch->ch_r_tlevel = 1; 818 } 819 820 neo_assert_modem_signals(ch); 821 822 /* Get current status of the modem signals now */ 823 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 824} 825 826/* 827 * Our board poller function. 828 */ 829static void neo_tasklet(unsigned long data) 830{ 831 struct dgnc_board *bd = (struct dgnc_board *)data; 832 struct channel_t *ch; 833 unsigned long flags; 834 int i; 835 int state = 0; 836 int ports = 0; 837 838 if (!bd || bd->magic != DGNC_BOARD_MAGIC) 839 return; 840 841 /* Cache a couple board values */ 842 spin_lock_irqsave(&bd->bd_lock, flags); 843 state = bd->state; 844 ports = bd->nasync; 845 spin_unlock_irqrestore(&bd->bd_lock, flags); 846 847 /* 848 * Do NOT allow the interrupt routine to read the intr registers 849 * Until we release this lock. 850 */ 851 spin_lock_irqsave(&bd->bd_intr_lock, flags); 852 853 /* 854 * If board is ready, parse deeper to see if there is anything to do. 855 */ 856 if ((state == BOARD_READY) && (ports > 0)) { 857 /* Loop on each port */ 858 for (i = 0; i < ports; i++) { 859 ch = bd->channels[i]; 860 861 /* Just being careful... */ 862 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 863 continue; 864 865 /* 866 * NOTE: Remember you CANNOT hold any channel 867 * locks when calling the input routine. 868 * 869 * During input processing, its possible we 870 * will call the Linux ld, which might in turn, 871 * do a callback right back into us, resulting 872 * in us trying to grab the channel lock twice! 873 */ 874 dgnc_input(ch); 875 876 /* 877 * Channel lock is grabbed and then released 878 * inside both of these routines, but neither 879 * call anything else that could call back into us. 880 */ 881 neo_copy_data_from_queue_to_uart(ch); 882 dgnc_wakeup_writes(ch); 883 884 /* 885 * Call carrier carrier function, in case something 886 * has changed. 887 */ 888 dgnc_carrier(ch); 889 890 /* 891 * Check to see if we need to turn off a sending break. 892 * The timing check is done inside clear_break() 893 */ 894 if (ch->ch_stop_sending_break) 895 neo_clear_break(ch, 0); 896 } 897 } 898 899 /* Allow interrupt routine to access the interrupt register again */ 900 spin_unlock_irqrestore(&bd->bd_intr_lock, flags); 901} 902 903/* 904 * dgnc_neo_intr() 905 * 906 * Neo specific interrupt handler. 907 */ 908static irqreturn_t neo_intr(int irq, void *voidbrd) 909{ 910 struct dgnc_board *brd = voidbrd; 911 struct channel_t *ch; 912 int port = 0; 913 int type = 0; 914 int current_port; 915 u32 tmp; 916 u32 uart_poll; 917 unsigned long flags; 918 unsigned long flags2; 919 920 /* 921 * Check to make sure it didn't receive interrupt with a null board 922 * associated or a board pointer that wasn't ours. 923 */ 924 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 925 return IRQ_NONE; 926 927 brd->intr_count++; 928 929 /* Lock out the slow poller from running on this board. */ 930 spin_lock_irqsave(&brd->bd_intr_lock, flags); 931 932 /* 933 * Read in "extended" IRQ information from the 32bit Neo register. 934 * Bits 0-7: What port triggered the interrupt. 935 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 936 */ 937 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 938 939 /* 940 * If 0, no interrupts pending. 941 * This can happen if the IRQ is shared among a couple Neo/Classic boards. 942 */ 943 if (!uart_poll) { 944 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 945 return IRQ_NONE; 946 } 947 948 /* At this point, we have at least SOMETHING to service, dig further... */ 949 950 current_port = 0; 951 952 /* Loop on each port */ 953 while ((uart_poll & 0xff) != 0) { 954 tmp = uart_poll; 955 956 /* Check current port to see if it has interrupt pending */ 957 if ((tmp & dgnc_offset_table[current_port]) != 0) { 958 port = current_port; 959 type = tmp >> (8 + (port * 3)); 960 type &= 0x7; 961 } else { 962 current_port++; 963 continue; 964 } 965 966 /* Remove this port + type from uart_poll */ 967 uart_poll &= ~(dgnc_offset_table[port]); 968 969 if (!type) { 970 /* If no type, just ignore it, and move onto next port */ 971 continue; 972 } 973 974 /* Switch on type of interrupt we have */ 975 switch (type) { 976 case UART_17158_RXRDY_TIMEOUT: 977 /* 978 * RXRDY Time-out is cleared by reading data in the 979 * RX FIFO until it falls below the trigger level. 980 */ 981 982 /* Verify the port is in range. */ 983 if (port >= brd->nasync) 984 continue; 985 986 ch = brd->channels[port]; 987 neo_copy_data_from_uart_to_queue(ch); 988 989 /* Call our tty layer to enforce queue flow control if needed. */ 990 spin_lock_irqsave(&ch->ch_lock, flags2); 991 dgnc_check_queue_flow_control(ch); 992 spin_unlock_irqrestore(&ch->ch_lock, flags2); 993 994 continue; 995 996 case UART_17158_RX_LINE_STATUS: 997 /* 998 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 999 */ 1000 neo_parse_lsr(brd, port); 1001 continue; 1002 1003 case UART_17158_TXRDY: 1004 /* 1005 * TXRDY interrupt clears after reading ISR register for the UART channel. 1006 */ 1007 1008 /* 1009 * Yes, this is odd... 1010 * Why would I check EVERY possibility of type of 1011 * interrupt, when we know its TXRDY??? 1012 * Becuz for some reason, even tho we got triggered for TXRDY, 1013 * it seems to be occasionally wrong. Instead of TX, which 1014 * it should be, I was getting things like RXDY too. Weird. 1015 */ 1016 neo_parse_isr(brd, port); 1017 continue; 1018 1019 case UART_17158_MSR: 1020 /* 1021 * MSR or flow control was seen. 1022 */ 1023 neo_parse_isr(brd, port); 1024 continue; 1025 1026 default: 1027 /* 1028 * The UART triggered us with a bogus interrupt type. 1029 * It appears the Exar chip, when REALLY bogged down, will throw 1030 * these once and awhile. 1031 * Its harmless, just ignore it and move on. 1032 */ 1033 continue; 1034 } 1035 } 1036 1037 /* 1038 * Schedule tasklet to more in-depth servicing at a better time. 1039 */ 1040 tasklet_schedule(&brd->helper_tasklet); 1041 1042 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 1043 1044 return IRQ_HANDLED; 1045} 1046 1047/* 1048 * Neo specific way of turning off the receiver. 1049 * Used as a way to enforce queue flow control when in 1050 * hardware flow control mode. 1051 */ 1052static void neo_disable_receiver(struct channel_t *ch) 1053{ 1054 unsigned char tmp = readb(&ch->ch_neo_uart->ier); 1055 1056 tmp &= ~(UART_IER_RDI); 1057 writeb(tmp, &ch->ch_neo_uart->ier); 1058 neo_pci_posting_flush(ch->ch_bd); 1059} 1060 1061/* 1062 * Neo specific way of turning on the receiver. 1063 * Used as a way to un-enforce queue flow control when in 1064 * hardware flow control mode. 1065 */ 1066static void neo_enable_receiver(struct channel_t *ch) 1067{ 1068 unsigned char tmp = readb(&ch->ch_neo_uart->ier); 1069 1070 tmp |= (UART_IER_RDI); 1071 writeb(tmp, &ch->ch_neo_uart->ier); 1072 neo_pci_posting_flush(ch->ch_bd); 1073} 1074 1075static void neo_copy_data_from_uart_to_queue(struct channel_t *ch) 1076{ 1077 int qleft = 0; 1078 unsigned char linestatus = 0; 1079 unsigned char error_mask = 0; 1080 int n = 0; 1081 int total = 0; 1082 ushort head; 1083 ushort tail; 1084 unsigned long flags; 1085 1086 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1087 return; 1088 1089 spin_lock_irqsave(&ch->ch_lock, flags); 1090 1091 /* cache head and tail of queue */ 1092 head = ch->ch_r_head & RQUEUEMASK; 1093 tail = ch->ch_r_tail & RQUEUEMASK; 1094 1095 /* Get our cached LSR */ 1096 linestatus = ch->ch_cached_lsr; 1097 ch->ch_cached_lsr = 0; 1098 1099 /* Store how much space we have left in the queue */ 1100 qleft = tail - head - 1; 1101 if (qleft < 0) 1102 qleft += RQUEUEMASK + 1; 1103 1104 /* 1105 * If the UART is not in FIFO mode, force the FIFO copy to 1106 * NOT be run, by setting total to 0. 1107 * 1108 * On the other hand, if the UART IS in FIFO mode, then ask 1109 * the UART to give us an approximation of data it has RX'ed. 1110 */ 1111 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 1112 total = 0; 1113 else { 1114 total = readb(&ch->ch_neo_uart->rfifo); 1115 1116 /* 1117 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 1118 * 1119 * This resolves a problem/bug with the Exar chip that sometimes 1120 * returns a bogus value in the rfifo register. 1121 * The count can be any where from 0-3 bytes "off". 1122 * Bizarre, but true. 1123 */ 1124 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID) 1125 total -= 1; 1126 else 1127 total -= 3; 1128 } 1129 1130 /* 1131 * Finally, bound the copy to make sure we don't overflow 1132 * our own queue... 1133 * The byte by byte copy loop below this loop this will 1134 * deal with the queue overflow possibility. 1135 */ 1136 total = min(total, qleft); 1137 1138 while (total > 0) { 1139 /* 1140 * Grab the linestatus register, we need to check 1141 * to see if there are any errors in the FIFO. 1142 */ 1143 linestatus = readb(&ch->ch_neo_uart->lsr); 1144 1145 /* 1146 * Break out if there is a FIFO error somewhere. 1147 * This will allow us to go byte by byte down below, 1148 * finding the exact location of the error. 1149 */ 1150 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 1151 break; 1152 1153 /* Make sure we don't go over the end of our queue */ 1154 n = min(((uint)total), (RQUEUESIZE - (uint)head)); 1155 1156 /* 1157 * Cut down n even further if needed, this is to fix 1158 * a problem with memcpy_fromio() with the Neo on the 1159 * IBM pSeries platform. 1160 * 15 bytes max appears to be the magic number. 1161 */ 1162 n = min_t(uint, n, 12); 1163 1164 /* 1165 * Since we are grabbing the linestatus register, which 1166 * will reset some bits after our read, we need to ensure 1167 * we don't miss our TX FIFO emptys. 1168 */ 1169 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 1170 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1171 1172 linestatus = 0; 1173 1174 /* Copy data from uart to the queue */ 1175 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 1176 1177 /* 1178 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 1179 * that all the data currently in the FIFO is free of 1180 * breaks and parity/frame/orun errors. 1181 */ 1182 memset(ch->ch_equeue + head, 0, n); 1183 1184 /* Add to and flip head if needed */ 1185 head = (head + n) & RQUEUEMASK; 1186 total -= n; 1187 qleft -= n; 1188 ch->ch_rxcount += n; 1189 } 1190 1191 /* 1192 * Create a mask to determine whether we should 1193 * insert the character (if any) into our queue. 1194 */ 1195 if (ch->ch_c_iflag & IGNBRK) 1196 error_mask |= UART_LSR_BI; 1197 1198 /* 1199 * Now cleanup any leftover bytes still in the UART. 1200 * Also deal with any possible queue overflow here as well. 1201 */ 1202 while (1) { 1203 /* 1204 * Its possible we have a linestatus from the loop above 1205 * this, so we "OR" on any extra bits. 1206 */ 1207 linestatus |= readb(&ch->ch_neo_uart->lsr); 1208 1209 /* 1210 * If the chip tells us there is no more data pending to 1211 * be read, we can then leave. 1212 * But before we do, cache the linestatus, just in case. 1213 */ 1214 if (!(linestatus & UART_LSR_DR)) { 1215 ch->ch_cached_lsr = linestatus; 1216 break; 1217 } 1218 1219 /* No need to store this bit */ 1220 linestatus &= ~UART_LSR_DR; 1221 1222 /* 1223 * Since we are grabbing the linestatus register, which 1224 * will reset some bits after our read, we need to ensure 1225 * we don't miss our TX FIFO emptys. 1226 */ 1227 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 1228 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 1229 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1230 } 1231 1232 /* 1233 * Discard character if we are ignoring the error mask. 1234 */ 1235 if (linestatus & error_mask) { 1236 unsigned char discard; 1237 1238 linestatus = 0; 1239 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 1240 continue; 1241 } 1242 1243 /* 1244 * If our queue is full, we have no choice but to drop some data. 1245 * The assumption is that HWFLOW or SWFLOW should have stopped 1246 * things way way before we got to this point. 1247 * 1248 * I decided that I wanted to ditch the oldest data first, 1249 * I hope thats okay with everyone? Yes? Good. 1250 */ 1251 while (qleft < 1) { 1252 tail = (tail + 1) & RQUEUEMASK; 1253 ch->ch_r_tail = tail; 1254 ch->ch_err_overrun++; 1255 qleft++; 1256 } 1257 1258 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 1259 ch->ch_equeue[head] = (unsigned char)linestatus; 1260 1261 /* Ditch any remaining linestatus value. */ 1262 linestatus = 0; 1263 1264 /* Add to and flip head if needed */ 1265 head = (head + 1) & RQUEUEMASK; 1266 1267 qleft--; 1268 ch->ch_rxcount++; 1269 } 1270 1271 /* 1272 * Write new final heads to channel structure. 1273 */ 1274 ch->ch_r_head = head & RQUEUEMASK; 1275 ch->ch_e_head = head & EQUEUEMASK; 1276 1277 spin_unlock_irqrestore(&ch->ch_lock, flags); 1278} 1279 1280/* 1281 * This function basically goes to sleep for secs, or until 1282 * it gets signalled that the port has fully drained. 1283 */ 1284static int neo_drain(struct tty_struct *tty, uint seconds) 1285{ 1286 unsigned long flags; 1287 struct channel_t *ch; 1288 struct un_t *un; 1289 int rc = 0; 1290 1291 if (!tty || tty->magic != TTY_MAGIC) 1292 return -ENXIO; 1293 1294 un = (struct un_t *)tty->driver_data; 1295 if (!un || un->magic != DGNC_UNIT_MAGIC) 1296 return -ENXIO; 1297 1298 ch = un->un_ch; 1299 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1300 return -ENXIO; 1301 1302 spin_lock_irqsave(&ch->ch_lock, flags); 1303 un->un_flags |= UN_EMPTY; 1304 spin_unlock_irqrestore(&ch->ch_lock, flags); 1305 1306 /* 1307 * Go to sleep waiting for the tty layer to wake me back up when 1308 * the empty flag goes away. 1309 * 1310 * NOTE: TODO: Do something with time passed in. 1311 */ 1312 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0)); 1313 1314 /* If ret is non-zero, user ctrl-c'ed us */ 1315 return rc; 1316} 1317 1318/* 1319 * Flush the WRITE FIFO on the Neo. 1320 * 1321 * NOTE: Channel lock MUST be held before calling this function! 1322 */ 1323static void neo_flush_uart_write(struct channel_t *ch) 1324{ 1325 unsigned char tmp = 0; 1326 int i = 0; 1327 1328 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1329 return; 1330 1331 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1332 neo_pci_posting_flush(ch->ch_bd); 1333 1334 for (i = 0; i < 10; i++) { 1335 /* Check to see if the UART feels it completely flushed the FIFO. */ 1336 tmp = readb(&ch->ch_neo_uart->isr_fcr); 1337 if (tmp & 4) 1338 udelay(10); 1339 else 1340 break; 1341 } 1342 1343 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1344} 1345 1346/* 1347 * Flush the READ FIFO on the Neo. 1348 * 1349 * NOTE: Channel lock MUST be held before calling this function! 1350 */ 1351static void neo_flush_uart_read(struct channel_t *ch) 1352{ 1353 unsigned char tmp = 0; 1354 int i = 0; 1355 1356 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1357 return; 1358 1359 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 1360 neo_pci_posting_flush(ch->ch_bd); 1361 1362 for (i = 0; i < 10; i++) { 1363 /* Check to see if the UART feels it completely flushed the FIFO. */ 1364 tmp = readb(&ch->ch_neo_uart->isr_fcr); 1365 if (tmp & 2) 1366 udelay(10); 1367 else 1368 break; 1369 } 1370} 1371 1372static void neo_copy_data_from_queue_to_uart(struct channel_t *ch) 1373{ 1374 ushort head; 1375 ushort tail; 1376 int n; 1377 int s; 1378 int qlen; 1379 uint len_written = 0; 1380 unsigned long flags; 1381 1382 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1383 return; 1384 1385 spin_lock_irqsave(&ch->ch_lock, flags); 1386 1387 /* No data to write to the UART */ 1388 if (ch->ch_w_tail == ch->ch_w_head) 1389 goto exit_unlock; 1390 1391 /* If port is "stopped", don't send any data to the UART */ 1392 if ((ch->ch_flags & CH_FORCED_STOP) || 1393 (ch->ch_flags & CH_BREAK_SENDING)) 1394 goto exit_unlock; 1395 1396 /* 1397 * If FIFOs are disabled. Send data directly to txrx register 1398 */ 1399 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 1400 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr); 1401 1402 /* Cache the LSR bits for later parsing */ 1403 ch->ch_cached_lsr |= lsrbits; 1404 if (ch->ch_cached_lsr & UART_LSR_THRE) { 1405 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 1406 1407 /* 1408 * If RTS Toggle mode is on, turn on RTS now if not already set, 1409 * and make sure we get an event when the data transfer has completed. 1410 */ 1411 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { 1412 if (!(ch->ch_mostat & UART_MCR_RTS)) { 1413 ch->ch_mostat |= (UART_MCR_RTS); 1414 neo_assert_modem_signals(ch); 1415 } 1416 ch->ch_tun.un_flags |= (UN_EMPTY); 1417 } 1418 /* 1419 * If DTR Toggle mode is on, turn on DTR now if not already set, 1420 * and make sure we get an event when the data transfer has completed. 1421 */ 1422 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { 1423 if (!(ch->ch_mostat & UART_MCR_DTR)) { 1424 ch->ch_mostat |= (UART_MCR_DTR); 1425 neo_assert_modem_signals(ch); 1426 } 1427 ch->ch_tun.un_flags |= (UN_EMPTY); 1428 } 1429 1430 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx); 1431 ch->ch_w_tail++; 1432 ch->ch_w_tail &= WQUEUEMASK; 1433 ch->ch_txcount++; 1434 } 1435 1436 goto exit_unlock; 1437 } 1438 1439 /* 1440 * We have to do it this way, because of the EXAR TXFIFO count bug. 1441 */ 1442 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) { 1443 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 1444 goto exit_unlock; 1445 1446 len_written = 0; 1447 1448 n = readb(&ch->ch_neo_uart->tfifo); 1449 1450 if ((unsigned int)n > ch->ch_t_tlevel) 1451 goto exit_unlock; 1452 1453 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 1454 } else { 1455 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo); 1456 } 1457 1458 /* cache head and tail of queue */ 1459 head = ch->ch_w_head & WQUEUEMASK; 1460 tail = ch->ch_w_tail & WQUEUEMASK; 1461 qlen = (head - tail) & WQUEUEMASK; 1462 1463 /* Find minimum of the FIFO space, versus queue length */ 1464 n = min(n, qlen); 1465 1466 while (n > 0) { 1467 s = ((head >= tail) ? head : WQUEUESIZE) - tail; 1468 s = min(s, n); 1469 1470 if (s <= 0) 1471 break; 1472 1473 /* 1474 * If RTS Toggle mode is on, turn on RTS now if not already set, 1475 * and make sure we get an event when the data transfer has completed. 1476 */ 1477 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { 1478 if (!(ch->ch_mostat & UART_MCR_RTS)) { 1479 ch->ch_mostat |= (UART_MCR_RTS); 1480 neo_assert_modem_signals(ch); 1481 } 1482 ch->ch_tun.un_flags |= (UN_EMPTY); 1483 } 1484 1485 /* 1486 * If DTR Toggle mode is on, turn on DTR now if not already set, 1487 * and make sure we get an event when the data transfer has completed. 1488 */ 1489 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { 1490 if (!(ch->ch_mostat & UART_MCR_DTR)) { 1491 ch->ch_mostat |= (UART_MCR_DTR); 1492 neo_assert_modem_signals(ch); 1493 } 1494 ch->ch_tun.un_flags |= (UN_EMPTY); 1495 } 1496 1497 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s); 1498 1499 /* Add and flip queue if needed */ 1500 tail = (tail + s) & WQUEUEMASK; 1501 n -= s; 1502 ch->ch_txcount += s; 1503 len_written += s; 1504 } 1505 1506 /* Update the final tail */ 1507 ch->ch_w_tail = tail & WQUEUEMASK; 1508 1509 if (len_written > 0) { 1510 neo_pci_posting_flush(ch->ch_bd); 1511 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1512 } 1513 1514exit_unlock: 1515 spin_unlock_irqrestore(&ch->ch_lock, flags); 1516} 1517 1518static void neo_parse_modem(struct channel_t *ch, unsigned char signals) 1519{ 1520 unsigned char msignals = signals; 1521 1522 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1523 return; 1524 1525 /* 1526 * Do altpin switching. Altpin switches DCD and DSR. 1527 * This prolly breaks DSRPACE, so we should be more clever here. 1528 */ 1529 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) { 1530 unsigned char mswap = msignals; 1531 1532 if (mswap & UART_MSR_DDCD) { 1533 msignals &= ~UART_MSR_DDCD; 1534 msignals |= UART_MSR_DDSR; 1535 } 1536 if (mswap & UART_MSR_DDSR) { 1537 msignals &= ~UART_MSR_DDSR; 1538 msignals |= UART_MSR_DDCD; 1539 } 1540 if (mswap & UART_MSR_DCD) { 1541 msignals &= ~UART_MSR_DCD; 1542 msignals |= UART_MSR_DSR; 1543 } 1544 if (mswap & UART_MSR_DSR) { 1545 msignals &= ~UART_MSR_DSR; 1546 msignals |= UART_MSR_DCD; 1547 } 1548 } 1549 1550 /* Scrub off lower bits. They signify delta's, which I don't care about */ 1551 msignals &= 0xf0; 1552 1553 if (msignals & UART_MSR_DCD) 1554 ch->ch_mistat |= UART_MSR_DCD; 1555 else 1556 ch->ch_mistat &= ~UART_MSR_DCD; 1557 1558 if (msignals & UART_MSR_DSR) 1559 ch->ch_mistat |= UART_MSR_DSR; 1560 else 1561 ch->ch_mistat &= ~UART_MSR_DSR; 1562 1563 if (msignals & UART_MSR_RI) 1564 ch->ch_mistat |= UART_MSR_RI; 1565 else 1566 ch->ch_mistat &= ~UART_MSR_RI; 1567 1568 if (msignals & UART_MSR_CTS) 1569 ch->ch_mistat |= UART_MSR_CTS; 1570 else 1571 ch->ch_mistat &= ~UART_MSR_CTS; 1572} 1573 1574/* Make the UART raise any of the output signals we want up */ 1575static void neo_assert_modem_signals(struct channel_t *ch) 1576{ 1577 unsigned char out; 1578 1579 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1580 return; 1581 1582 out = ch->ch_mostat; 1583 1584 if (ch->ch_flags & CH_LOOPBACK) 1585 out |= UART_MCR_LOOP; 1586 1587 writeb(out, &ch->ch_neo_uart->mcr); 1588 neo_pci_posting_flush(ch->ch_bd); 1589 1590 /* Give time for the UART to actually raise/drop the signals */ 1591 udelay(10); 1592} 1593 1594static void neo_send_start_character(struct channel_t *ch) 1595{ 1596 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1597 return; 1598 1599 if (ch->ch_startc != _POSIX_VDISABLE) { 1600 ch->ch_xon_sends++; 1601 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1602 neo_pci_posting_flush(ch->ch_bd); 1603 udelay(10); 1604 } 1605} 1606 1607static void neo_send_stop_character(struct channel_t *ch) 1608{ 1609 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1610 return; 1611 1612 if (ch->ch_stopc != _POSIX_VDISABLE) { 1613 ch->ch_xoff_sends++; 1614 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1615 neo_pci_posting_flush(ch->ch_bd); 1616 udelay(10); 1617 } 1618} 1619 1620/* 1621 * neo_uart_init 1622 */ 1623static void neo_uart_init(struct channel_t *ch) 1624{ 1625 writeb(0, &ch->ch_neo_uart->ier); 1626 writeb(0, &ch->ch_neo_uart->efr); 1627 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1628 1629 /* Clear out UART and FIFO */ 1630 readb(&ch->ch_neo_uart->txrx); 1631 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1632 readb(&ch->ch_neo_uart->lsr); 1633 readb(&ch->ch_neo_uart->msr); 1634 1635 ch->ch_flags |= CH_FIFO_ENABLED; 1636 1637 /* Assert any signals we want up */ 1638 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1639 neo_pci_posting_flush(ch->ch_bd); 1640} 1641 1642/* 1643 * Make the UART completely turn off. 1644 */ 1645static void neo_uart_off(struct channel_t *ch) 1646{ 1647 /* Turn off UART enhanced bits */ 1648 writeb(0, &ch->ch_neo_uart->efr); 1649 1650 /* Stop all interrupts from occurring. */ 1651 writeb(0, &ch->ch_neo_uart->ier); 1652 neo_pci_posting_flush(ch->ch_bd); 1653} 1654 1655static uint neo_get_uart_bytes_left(struct channel_t *ch) 1656{ 1657 unsigned char left = 0; 1658 unsigned char lsr = readb(&ch->ch_neo_uart->lsr); 1659 1660 /* We must cache the LSR as some of the bits get reset once read... */ 1661 ch->ch_cached_lsr |= lsr; 1662 1663 /* Determine whether the Transmitter is empty or not */ 1664 if (!(lsr & UART_LSR_TEMT)) { 1665 if (ch->ch_flags & CH_TX_FIFO_EMPTY) 1666 tasklet_schedule(&ch->ch_bd->helper_tasklet); 1667 left = 1; 1668 } else { 1669 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1670 left = 0; 1671 } 1672 1673 return left; 1674} 1675 1676/* Channel lock MUST be held by the calling function! */ 1677static void neo_send_break(struct channel_t *ch, int msecs) 1678{ 1679 /* 1680 * If we receive a time of 0, this means turn off the break. 1681 */ 1682 if (msecs == 0) { 1683 if (ch->ch_flags & CH_BREAK_SENDING) { 1684 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 1685 1686 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1687 neo_pci_posting_flush(ch->ch_bd); 1688 ch->ch_flags &= ~(CH_BREAK_SENDING); 1689 ch->ch_stop_sending_break = 0; 1690 } 1691 return; 1692 } 1693 1694 /* 1695 * Set the time we should stop sending the break. 1696 * If we are already sending a break, toss away the existing 1697 * time to stop, and use this new value instead. 1698 */ 1699 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs); 1700 1701 /* Tell the UART to start sending the break */ 1702 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1703 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 1704 1705 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1706 neo_pci_posting_flush(ch->ch_bd); 1707 ch->ch_flags |= (CH_BREAK_SENDING); 1708 } 1709} 1710 1711/* 1712 * neo_send_immediate_char. 1713 * 1714 * Sends a specific character as soon as possible to the UART, 1715 * jumping over any bytes that might be in the write queue. 1716 * 1717 * The channel lock MUST be held by the calling function. 1718 */ 1719static void neo_send_immediate_char(struct channel_t *ch, unsigned char c) 1720{ 1721 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1722 return; 1723 1724 writeb(c, &ch->ch_neo_uart->txrx); 1725 neo_pci_posting_flush(ch->ch_bd); 1726} 1727 1728static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address) 1729{ 1730 unsigned int enable; 1731 unsigned int bits; 1732 unsigned int databit; 1733 unsigned int val; 1734 1735 /* enable chip select */ 1736 writeb(NEO_EECS, base + NEO_EEREG); 1737 /* READ */ 1738 enable = (address | 0x180); 1739 1740 for (bits = 9; bits--; ) { 1741 databit = (enable & (1 << bits)) ? NEO_EEDI : 0; 1742 /* Set read address */ 1743 writeb(databit | NEO_EECS, base + NEO_EEREG); 1744 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG); 1745 } 1746 1747 val = 0; 1748 1749 for (bits = 17; bits--; ) { 1750 /* clock to EEPROM */ 1751 writeb(NEO_EECS, base + NEO_EEREG); 1752 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG); 1753 val <<= 1; 1754 /* read EEPROM */ 1755 if (readb(base + NEO_EEREG) & NEO_EEDO) 1756 val |= 1; 1757 } 1758 1759 /* clock falling edge */ 1760 writeb(NEO_EECS, base + NEO_EEREG); 1761 1762 /* drop chip select */ 1763 writeb(0x00, base + NEO_EEREG); 1764 1765 return val; 1766} 1767 1768static void neo_vpd(struct dgnc_board *brd) 1769{ 1770 unsigned int i = 0; 1771 unsigned int a; 1772 1773 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 1774 return; 1775 1776 if (!brd->re_map_membase) 1777 return; 1778 1779 /* Store the VPD into our buffer */ 1780 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) { 1781 a = neo_read_eeprom(brd->re_map_membase, i); 1782 brd->vpd[i*2] = a & 0xff; 1783 brd->vpd[(i*2)+1] = (a >> 8) & 0xff; 1784 } 1785 1786 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */ 1787 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/ 1788 || (brd->vpd[0x7F] != 0x78)) { /* small resource end tag */ 1789 1790 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE); 1791 } else { 1792 /* Search for the serial number */ 1793 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++) 1794 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N') 1795 strncpy(brd->serial_num, &brd->vpd[i + 3], 9); 1796 } 1797} 1798