1/* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * Author: Addy Ke <addy.ke@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/clk.h> 19#include <linux/err.h> 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/platform_device.h> 23#include <linux/slab.h> 24#include <linux/spi/spi.h> 25#include <linux/scatterlist.h> 26#include <linux/of.h> 27#include <linux/pm_runtime.h> 28#include <linux/io.h> 29#include <linux/dmaengine.h> 30 31#define DRIVER_NAME "rockchip-spi" 32 33/* SPI register offsets */ 34#define ROCKCHIP_SPI_CTRLR0 0x0000 35#define ROCKCHIP_SPI_CTRLR1 0x0004 36#define ROCKCHIP_SPI_SSIENR 0x0008 37#define ROCKCHIP_SPI_SER 0x000c 38#define ROCKCHIP_SPI_BAUDR 0x0010 39#define ROCKCHIP_SPI_TXFTLR 0x0014 40#define ROCKCHIP_SPI_RXFTLR 0x0018 41#define ROCKCHIP_SPI_TXFLR 0x001c 42#define ROCKCHIP_SPI_RXFLR 0x0020 43#define ROCKCHIP_SPI_SR 0x0024 44#define ROCKCHIP_SPI_IPR 0x0028 45#define ROCKCHIP_SPI_IMR 0x002c 46#define ROCKCHIP_SPI_ISR 0x0030 47#define ROCKCHIP_SPI_RISR 0x0034 48#define ROCKCHIP_SPI_ICR 0x0038 49#define ROCKCHIP_SPI_DMACR 0x003c 50#define ROCKCHIP_SPI_DMATDLR 0x0040 51#define ROCKCHIP_SPI_DMARDLR 0x0044 52#define ROCKCHIP_SPI_TXDR 0x0400 53#define ROCKCHIP_SPI_RXDR 0x0800 54 55/* Bit fields in CTRLR0 */ 56#define CR0_DFS_OFFSET 0 57 58#define CR0_CFS_OFFSET 2 59 60#define CR0_SCPH_OFFSET 6 61 62#define CR0_SCPOL_OFFSET 7 63 64#define CR0_CSM_OFFSET 8 65#define CR0_CSM_KEEP 0x0 66/* ss_n be high for half sclk_out cycles */ 67#define CR0_CSM_HALF 0X1 68/* ss_n be high for one sclk_out cycle */ 69#define CR0_CSM_ONE 0x2 70 71/* ss_n to sclk_out delay */ 72#define CR0_SSD_OFFSET 10 73/* 74 * The period between ss_n active and 75 * sclk_out active is half sclk_out cycles 76 */ 77#define CR0_SSD_HALF 0x0 78/* 79 * The period between ss_n active and 80 * sclk_out active is one sclk_out cycle 81 */ 82#define CR0_SSD_ONE 0x1 83 84#define CR0_EM_OFFSET 11 85#define CR0_EM_LITTLE 0x0 86#define CR0_EM_BIG 0x1 87 88#define CR0_FBM_OFFSET 12 89#define CR0_FBM_MSB 0x0 90#define CR0_FBM_LSB 0x1 91 92#define CR0_BHT_OFFSET 13 93#define CR0_BHT_16BIT 0x0 94#define CR0_BHT_8BIT 0x1 95 96#define CR0_RSD_OFFSET 14 97 98#define CR0_FRF_OFFSET 16 99#define CR0_FRF_SPI 0x0 100#define CR0_FRF_SSP 0x1 101#define CR0_FRF_MICROWIRE 0x2 102 103#define CR0_XFM_OFFSET 18 104#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 105#define CR0_XFM_TR 0x0 106#define CR0_XFM_TO 0x1 107#define CR0_XFM_RO 0x2 108 109#define CR0_OPM_OFFSET 20 110#define CR0_OPM_MASTER 0x0 111#define CR0_OPM_SLAVE 0x1 112 113#define CR0_MTM_OFFSET 0x21 114 115/* Bit fields in SER, 2bit */ 116#define SER_MASK 0x3 117 118/* Bit fields in SR, 5bit */ 119#define SR_MASK 0x1f 120#define SR_BUSY (1 << 0) 121#define SR_TF_FULL (1 << 1) 122#define SR_TF_EMPTY (1 << 2) 123#define SR_RF_EMPTY (1 << 3) 124#define SR_RF_FULL (1 << 4) 125 126/* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 127#define INT_MASK 0x1f 128#define INT_TF_EMPTY (1 << 0) 129#define INT_TF_OVERFLOW (1 << 1) 130#define INT_RF_UNDERFLOW (1 << 2) 131#define INT_RF_OVERFLOW (1 << 3) 132#define INT_RF_FULL (1 << 4) 133 134/* Bit fields in ICR, 4bit */ 135#define ICR_MASK 0x0f 136#define ICR_ALL (1 << 0) 137#define ICR_RF_UNDERFLOW (1 << 1) 138#define ICR_RF_OVERFLOW (1 << 2) 139#define ICR_TF_OVERFLOW (1 << 3) 140 141/* Bit fields in DMACR */ 142#define RF_DMA_EN (1 << 0) 143#define TF_DMA_EN (1 << 1) 144 145#define RXBUSY (1 << 0) 146#define TXBUSY (1 << 1) 147 148/* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 149#define MAX_SCLK_OUT 50000000 150 151enum rockchip_ssi_type { 152 SSI_MOTO_SPI = 0, 153 SSI_TI_SSP, 154 SSI_NS_MICROWIRE, 155}; 156 157struct rockchip_spi_dma_data { 158 struct dma_chan *ch; 159 enum dma_transfer_direction direction; 160 dma_addr_t addr; 161}; 162 163struct rockchip_spi { 164 struct device *dev; 165 struct spi_master *master; 166 167 struct clk *spiclk; 168 struct clk *apb_pclk; 169 170 void __iomem *regs; 171 /*depth of the FIFO buffer */ 172 u32 fifo_len; 173 /* max bus freq supported */ 174 u32 max_freq; 175 /* supported slave numbers */ 176 enum rockchip_ssi_type type; 177 178 u16 mode; 179 u8 tmode; 180 u8 bpw; 181 u8 n_bytes; 182 u8 rsd_nsecs; 183 unsigned len; 184 u32 speed; 185 186 const void *tx; 187 const void *tx_end; 188 void *rx; 189 void *rx_end; 190 191 u32 state; 192 /* protect state */ 193 spinlock_t lock; 194 195 struct completion xfer_completion; 196 197 u32 use_dma; 198 struct sg_table tx_sg; 199 struct sg_table rx_sg; 200 struct rockchip_spi_dma_data dma_rx; 201 struct rockchip_spi_dma_data dma_tx; 202}; 203 204static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) 205{ 206 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); 207} 208 209static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) 210{ 211 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); 212} 213 214static inline void flush_fifo(struct rockchip_spi *rs) 215{ 216 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) 217 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 218} 219 220static inline void wait_for_idle(struct rockchip_spi *rs) 221{ 222 unsigned long timeout = jiffies + msecs_to_jiffies(5); 223 224 do { 225 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 226 return; 227 } while (!time_after(jiffies, timeout)); 228 229 dev_warn(rs->dev, "spi controller is in busy state!\n"); 230} 231 232static u32 get_fifo_len(struct rockchip_spi *rs) 233{ 234 u32 fifo; 235 236 for (fifo = 2; fifo < 32; fifo++) { 237 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); 238 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) 239 break; 240 } 241 242 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); 243 244 return (fifo == 31) ? 0 : fifo; 245} 246 247static inline u32 tx_max(struct rockchip_spi *rs) 248{ 249 u32 tx_left, tx_room; 250 251 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; 252 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 253 254 return min(tx_left, tx_room); 255} 256 257static inline u32 rx_max(struct rockchip_spi *rs) 258{ 259 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; 260 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 261 262 return min(rx_left, rx_room); 263} 264 265static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 266{ 267 u32 ser; 268 struct spi_master *master = spi->master; 269 struct rockchip_spi *rs = spi_master_get_devdata(master); 270 271 pm_runtime_get_sync(rs->dev); 272 273 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; 274 275 /* 276 * drivers/spi/spi.c: 277 * static void spi_set_cs(struct spi_device *spi, bool enable) 278 * { 279 * if (spi->mode & SPI_CS_HIGH) 280 * enable = !enable; 281 * 282 * if (spi->cs_gpio >= 0) 283 * gpio_set_value(spi->cs_gpio, !enable); 284 * else if (spi->master->set_cs) 285 * spi->master->set_cs(spi, !enable); 286 * } 287 * 288 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) 289 */ 290 if (!enable) 291 ser |= 1 << spi->chip_select; 292 else 293 ser &= ~(1 << spi->chip_select); 294 295 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); 296 297 pm_runtime_put_sync(rs->dev); 298} 299 300static int rockchip_spi_prepare_message(struct spi_master *master, 301 struct spi_message *msg) 302{ 303 struct rockchip_spi *rs = spi_master_get_devdata(master); 304 struct spi_device *spi = msg->spi; 305 306 rs->mode = spi->mode; 307 308 return 0; 309} 310 311static void rockchip_spi_handle_err(struct spi_master *master, 312 struct spi_message *msg) 313{ 314 unsigned long flags; 315 struct rockchip_spi *rs = spi_master_get_devdata(master); 316 317 spin_lock_irqsave(&rs->lock, flags); 318 319 /* 320 * For DMA mode, we need terminate DMA channel and flush 321 * fifo for the next transfer if DMA thansfer timeout. 322 * handle_err() was called by core if transfer failed. 323 * Maybe it is reasonable for error handling here. 324 */ 325 if (rs->use_dma) { 326 if (rs->state & RXBUSY) { 327 dmaengine_terminate_all(rs->dma_rx.ch); 328 flush_fifo(rs); 329 } 330 331 if (rs->state & TXBUSY) 332 dmaengine_terminate_all(rs->dma_tx.ch); 333 } 334 335 spin_unlock_irqrestore(&rs->lock, flags); 336} 337 338static int rockchip_spi_unprepare_message(struct spi_master *master, 339 struct spi_message *msg) 340{ 341 struct rockchip_spi *rs = spi_master_get_devdata(master); 342 343 spi_enable_chip(rs, 0); 344 345 return 0; 346} 347 348static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 349{ 350 u32 max = tx_max(rs); 351 u32 txw = 0; 352 353 while (max--) { 354 if (rs->n_bytes == 1) 355 txw = *(u8 *)(rs->tx); 356 else 357 txw = *(u16 *)(rs->tx); 358 359 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 360 rs->tx += rs->n_bytes; 361 } 362} 363 364static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 365{ 366 u32 max = rx_max(rs); 367 u32 rxw; 368 369 while (max--) { 370 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 371 if (rs->n_bytes == 1) 372 *(u8 *)(rs->rx) = (u8)rxw; 373 else 374 *(u16 *)(rs->rx) = (u16)rxw; 375 rs->rx += rs->n_bytes; 376 } 377} 378 379static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) 380{ 381 int remain = 0; 382 383 do { 384 if (rs->tx) { 385 remain = rs->tx_end - rs->tx; 386 rockchip_spi_pio_writer(rs); 387 } 388 389 if (rs->rx) { 390 remain = rs->rx_end - rs->rx; 391 rockchip_spi_pio_reader(rs); 392 } 393 394 cpu_relax(); 395 } while (remain); 396 397 /* If tx, wait until the FIFO data completely. */ 398 if (rs->tx) 399 wait_for_idle(rs); 400 401 spi_enable_chip(rs, 0); 402 403 return 0; 404} 405 406static void rockchip_spi_dma_rxcb(void *data) 407{ 408 unsigned long flags; 409 struct rockchip_spi *rs = data; 410 411 spin_lock_irqsave(&rs->lock, flags); 412 413 rs->state &= ~RXBUSY; 414 if (!(rs->state & TXBUSY)) { 415 spi_enable_chip(rs, 0); 416 spi_finalize_current_transfer(rs->master); 417 } 418 419 spin_unlock_irqrestore(&rs->lock, flags); 420} 421 422static void rockchip_spi_dma_txcb(void *data) 423{ 424 unsigned long flags; 425 struct rockchip_spi *rs = data; 426 427 /* Wait until the FIFO data completely. */ 428 wait_for_idle(rs); 429 430 spin_lock_irqsave(&rs->lock, flags); 431 432 rs->state &= ~TXBUSY; 433 if (!(rs->state & RXBUSY)) { 434 spi_enable_chip(rs, 0); 435 spi_finalize_current_transfer(rs->master); 436 } 437 438 spin_unlock_irqrestore(&rs->lock, flags); 439} 440 441static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) 442{ 443 unsigned long flags; 444 struct dma_slave_config rxconf, txconf; 445 struct dma_async_tx_descriptor *rxdesc, *txdesc; 446 447 spin_lock_irqsave(&rs->lock, flags); 448 rs->state &= ~RXBUSY; 449 rs->state &= ~TXBUSY; 450 spin_unlock_irqrestore(&rs->lock, flags); 451 452 rxdesc = NULL; 453 if (rs->rx) { 454 rxconf.direction = rs->dma_rx.direction; 455 rxconf.src_addr = rs->dma_rx.addr; 456 rxconf.src_addr_width = rs->n_bytes; 457 rxconf.src_maxburst = rs->n_bytes; 458 dmaengine_slave_config(rs->dma_rx.ch, &rxconf); 459 460 rxdesc = dmaengine_prep_slave_sg( 461 rs->dma_rx.ch, 462 rs->rx_sg.sgl, rs->rx_sg.nents, 463 rs->dma_rx.direction, DMA_PREP_INTERRUPT); 464 465 rxdesc->callback = rockchip_spi_dma_rxcb; 466 rxdesc->callback_param = rs; 467 } 468 469 txdesc = NULL; 470 if (rs->tx) { 471 txconf.direction = rs->dma_tx.direction; 472 txconf.dst_addr = rs->dma_tx.addr; 473 txconf.dst_addr_width = rs->n_bytes; 474 txconf.dst_maxburst = rs->n_bytes; 475 dmaengine_slave_config(rs->dma_tx.ch, &txconf); 476 477 txdesc = dmaengine_prep_slave_sg( 478 rs->dma_tx.ch, 479 rs->tx_sg.sgl, rs->tx_sg.nents, 480 rs->dma_tx.direction, DMA_PREP_INTERRUPT); 481 482 txdesc->callback = rockchip_spi_dma_txcb; 483 txdesc->callback_param = rs; 484 } 485 486 /* rx must be started before tx due to spi instinct */ 487 if (rxdesc) { 488 spin_lock_irqsave(&rs->lock, flags); 489 rs->state |= RXBUSY; 490 spin_unlock_irqrestore(&rs->lock, flags); 491 dmaengine_submit(rxdesc); 492 dma_async_issue_pending(rs->dma_rx.ch); 493 } 494 495 if (txdesc) { 496 spin_lock_irqsave(&rs->lock, flags); 497 rs->state |= TXBUSY; 498 spin_unlock_irqrestore(&rs->lock, flags); 499 dmaengine_submit(txdesc); 500 dma_async_issue_pending(rs->dma_tx.ch); 501 } 502} 503 504static void rockchip_spi_config(struct rockchip_spi *rs) 505{ 506 u32 div = 0; 507 u32 dmacr = 0; 508 int rsd = 0; 509 510 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) 511 | (CR0_SSD_ONE << CR0_SSD_OFFSET); 512 513 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); 514 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); 515 cr0 |= (rs->tmode << CR0_XFM_OFFSET); 516 cr0 |= (rs->type << CR0_FRF_OFFSET); 517 518 if (rs->use_dma) { 519 if (rs->tx) 520 dmacr |= TF_DMA_EN; 521 if (rs->rx) 522 dmacr |= RF_DMA_EN; 523 } 524 525 if (WARN_ON(rs->speed > MAX_SCLK_OUT)) 526 rs->speed = MAX_SCLK_OUT; 527 528 /* the minimum divsor is 2 */ 529 if (rs->max_freq < 2 * rs->speed) { 530 clk_set_rate(rs->spiclk, 2 * rs->speed); 531 rs->max_freq = clk_get_rate(rs->spiclk); 532 } 533 534 /* div doesn't support odd number */ 535 div = DIV_ROUND_UP(rs->max_freq, rs->speed); 536 div = (div + 1) & 0xfffe; 537 538 /* Rx sample delay is expressed in parent clock cycles (max 3) */ 539 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), 540 1000000000 >> 8); 541 if (!rsd && rs->rsd_nsecs) { 542 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", 543 rs->max_freq, rs->rsd_nsecs); 544 } else if (rsd > 3) { 545 rsd = 3; 546 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", 547 rs->max_freq, rs->rsd_nsecs, 548 rsd * 1000000000U / rs->max_freq); 549 } 550 cr0 |= rsd << CR0_RSD_OFFSET; 551 552 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 553 554 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); 555 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); 556 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 557 558 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); 559 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); 560 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 561 562 spi_set_clk(rs, div); 563 564 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); 565} 566 567static int rockchip_spi_transfer_one( 568 struct spi_master *master, 569 struct spi_device *spi, 570 struct spi_transfer *xfer) 571{ 572 int ret = 1; 573 struct rockchip_spi *rs = spi_master_get_devdata(master); 574 575 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 576 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 577 578 if (!xfer->tx_buf && !xfer->rx_buf) { 579 dev_err(rs->dev, "No buffer for transfer\n"); 580 return -EINVAL; 581 } 582 583 rs->speed = xfer->speed_hz; 584 rs->bpw = xfer->bits_per_word; 585 rs->n_bytes = rs->bpw >> 3; 586 587 rs->tx = xfer->tx_buf; 588 rs->tx_end = rs->tx + xfer->len; 589 rs->rx = xfer->rx_buf; 590 rs->rx_end = rs->rx + xfer->len; 591 rs->len = xfer->len; 592 593 rs->tx_sg = xfer->tx_sg; 594 rs->rx_sg = xfer->rx_sg; 595 596 if (rs->tx && rs->rx) 597 rs->tmode = CR0_XFM_TR; 598 else if (rs->tx) 599 rs->tmode = CR0_XFM_TO; 600 else if (rs->rx) 601 rs->tmode = CR0_XFM_RO; 602 603 /* we need prepare dma before spi was enabled */ 604 if (master->can_dma && master->can_dma(master, spi, xfer)) 605 rs->use_dma = 1; 606 else 607 rs->use_dma = 0; 608 609 rockchip_spi_config(rs); 610 611 if (rs->use_dma) { 612 if (rs->tmode == CR0_XFM_RO) { 613 /* rx: dma must be prepared first */ 614 rockchip_spi_prepare_dma(rs); 615 spi_enable_chip(rs, 1); 616 } else { 617 /* tx or tr: spi must be enabled first */ 618 spi_enable_chip(rs, 1); 619 rockchip_spi_prepare_dma(rs); 620 } 621 } else { 622 spi_enable_chip(rs, 1); 623 ret = rockchip_spi_pio_transfer(rs); 624 } 625 626 return ret; 627} 628 629static bool rockchip_spi_can_dma(struct spi_master *master, 630 struct spi_device *spi, 631 struct spi_transfer *xfer) 632{ 633 struct rockchip_spi *rs = spi_master_get_devdata(master); 634 635 return (xfer->len > rs->fifo_len); 636} 637 638static int rockchip_spi_probe(struct platform_device *pdev) 639{ 640 int ret = 0; 641 struct rockchip_spi *rs; 642 struct spi_master *master; 643 struct resource *mem; 644 u32 rsd_nsecs; 645 646 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); 647 if (!master) 648 return -ENOMEM; 649 650 platform_set_drvdata(pdev, master); 651 652 rs = spi_master_get_devdata(master); 653 654 /* Get basic io resource and map it */ 655 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 656 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 657 if (IS_ERR(rs->regs)) { 658 ret = PTR_ERR(rs->regs); 659 goto err_ioremap_resource; 660 } 661 662 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 663 if (IS_ERR(rs->apb_pclk)) { 664 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 665 ret = PTR_ERR(rs->apb_pclk); 666 goto err_ioremap_resource; 667 } 668 669 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 670 if (IS_ERR(rs->spiclk)) { 671 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 672 ret = PTR_ERR(rs->spiclk); 673 goto err_ioremap_resource; 674 } 675 676 ret = clk_prepare_enable(rs->apb_pclk); 677 if (ret) { 678 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 679 goto err_ioremap_resource; 680 } 681 682 ret = clk_prepare_enable(rs->spiclk); 683 if (ret) { 684 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 685 goto err_spiclk_enable; 686 } 687 688 spi_enable_chip(rs, 0); 689 690 rs->type = SSI_MOTO_SPI; 691 rs->master = master; 692 rs->dev = &pdev->dev; 693 rs->max_freq = clk_get_rate(rs->spiclk); 694 695 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 696 &rsd_nsecs)) 697 rs->rsd_nsecs = rsd_nsecs; 698 699 rs->fifo_len = get_fifo_len(rs); 700 if (!rs->fifo_len) { 701 dev_err(&pdev->dev, "Failed to get fifo length\n"); 702 ret = -EINVAL; 703 goto err_get_fifo_len; 704 } 705 706 spin_lock_init(&rs->lock); 707 708 pm_runtime_set_active(&pdev->dev); 709 pm_runtime_enable(&pdev->dev); 710 711 master->auto_runtime_pm = true; 712 master->bus_num = pdev->id; 713 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; 714 master->num_chipselect = 2; 715 master->dev.of_node = pdev->dev.of_node; 716 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); 717 718 master->set_cs = rockchip_spi_set_cs; 719 master->prepare_message = rockchip_spi_prepare_message; 720 master->unprepare_message = rockchip_spi_unprepare_message; 721 master->transfer_one = rockchip_spi_transfer_one; 722 master->handle_err = rockchip_spi_handle_err; 723 724 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); 725 if (!rs->dma_tx.ch) 726 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 727 728 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); 729 if (!rs->dma_rx.ch) { 730 if (rs->dma_tx.ch) { 731 dma_release_channel(rs->dma_tx.ch); 732 rs->dma_tx.ch = NULL; 733 } 734 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 735 } 736 737 if (rs->dma_tx.ch && rs->dma_rx.ch) { 738 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); 739 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); 740 rs->dma_tx.direction = DMA_MEM_TO_DEV; 741 rs->dma_rx.direction = DMA_DEV_TO_MEM; 742 743 master->can_dma = rockchip_spi_can_dma; 744 master->dma_tx = rs->dma_tx.ch; 745 master->dma_rx = rs->dma_rx.ch; 746 } 747 748 ret = devm_spi_register_master(&pdev->dev, master); 749 if (ret) { 750 dev_err(&pdev->dev, "Failed to register master\n"); 751 goto err_register_master; 752 } 753 754 return 0; 755 756err_register_master: 757 if (rs->dma_tx.ch) 758 dma_release_channel(rs->dma_tx.ch); 759 if (rs->dma_rx.ch) 760 dma_release_channel(rs->dma_rx.ch); 761err_get_fifo_len: 762 clk_disable_unprepare(rs->spiclk); 763err_spiclk_enable: 764 clk_disable_unprepare(rs->apb_pclk); 765err_ioremap_resource: 766 spi_master_put(master); 767 768 return ret; 769} 770 771static int rockchip_spi_remove(struct platform_device *pdev) 772{ 773 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 774 struct rockchip_spi *rs = spi_master_get_devdata(master); 775 776 pm_runtime_disable(&pdev->dev); 777 778 clk_disable_unprepare(rs->spiclk); 779 clk_disable_unprepare(rs->apb_pclk); 780 781 if (rs->dma_tx.ch) 782 dma_release_channel(rs->dma_tx.ch); 783 if (rs->dma_rx.ch) 784 dma_release_channel(rs->dma_rx.ch); 785 786 return 0; 787} 788 789#ifdef CONFIG_PM_SLEEP 790static int rockchip_spi_suspend(struct device *dev) 791{ 792 int ret = 0; 793 struct spi_master *master = dev_get_drvdata(dev); 794 struct rockchip_spi *rs = spi_master_get_devdata(master); 795 796 ret = spi_master_suspend(rs->master); 797 if (ret) 798 return ret; 799 800 if (!pm_runtime_suspended(dev)) { 801 clk_disable_unprepare(rs->spiclk); 802 clk_disable_unprepare(rs->apb_pclk); 803 } 804 805 return ret; 806} 807 808static int rockchip_spi_resume(struct device *dev) 809{ 810 int ret = 0; 811 struct spi_master *master = dev_get_drvdata(dev); 812 struct rockchip_spi *rs = spi_master_get_devdata(master); 813 814 if (!pm_runtime_suspended(dev)) { 815 ret = clk_prepare_enable(rs->apb_pclk); 816 if (ret < 0) 817 return ret; 818 819 ret = clk_prepare_enable(rs->spiclk); 820 if (ret < 0) { 821 clk_disable_unprepare(rs->apb_pclk); 822 return ret; 823 } 824 } 825 826 ret = spi_master_resume(rs->master); 827 if (ret < 0) { 828 clk_disable_unprepare(rs->spiclk); 829 clk_disable_unprepare(rs->apb_pclk); 830 } 831 832 return ret; 833} 834#endif /* CONFIG_PM_SLEEP */ 835 836#ifdef CONFIG_PM 837static int rockchip_spi_runtime_suspend(struct device *dev) 838{ 839 struct spi_master *master = dev_get_drvdata(dev); 840 struct rockchip_spi *rs = spi_master_get_devdata(master); 841 842 clk_disable_unprepare(rs->spiclk); 843 clk_disable_unprepare(rs->apb_pclk); 844 845 return 0; 846} 847 848static int rockchip_spi_runtime_resume(struct device *dev) 849{ 850 int ret; 851 struct spi_master *master = dev_get_drvdata(dev); 852 struct rockchip_spi *rs = spi_master_get_devdata(master); 853 854 ret = clk_prepare_enable(rs->apb_pclk); 855 if (ret) 856 return ret; 857 858 ret = clk_prepare_enable(rs->spiclk); 859 if (ret) 860 clk_disable_unprepare(rs->apb_pclk); 861 862 return ret; 863} 864#endif /* CONFIG_PM */ 865 866static const struct dev_pm_ops rockchip_spi_pm = { 867 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 868 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 869 rockchip_spi_runtime_resume, NULL) 870}; 871 872static const struct of_device_id rockchip_spi_dt_match[] = { 873 { .compatible = "rockchip,rk3066-spi", }, 874 { .compatible = "rockchip,rk3188-spi", }, 875 { .compatible = "rockchip,rk3288-spi", }, 876 { }, 877}; 878MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 879 880static struct platform_driver rockchip_spi_driver = { 881 .driver = { 882 .name = DRIVER_NAME, 883 .pm = &rockchip_spi_pm, 884 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 885 }, 886 .probe = rockchip_spi_probe, 887 .remove = rockchip_spi_remove, 888}; 889 890module_platform_driver(rockchip_spi_driver); 891 892MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 893MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 894MODULE_LICENSE("GPL v2"); 895