1/*****************************************************************************/ 2/* ips.h -- driver for the Adaptec / IBM ServeRAID controller */ 3/* */ 4/* Written By: Keith Mitchell, IBM Corporation */ 5/* Jack Hammer, Adaptec, Inc. */ 6/* David Jeffery, Adaptec, Inc. */ 7/* */ 8/* Copyright (C) 1999 IBM Corporation */ 9/* Copyright (C) 2003 Adaptec, Inc. */ 10/* */ 11/* This program is free software; you can redistribute it and/or modify */ 12/* it under the terms of the GNU General Public License as published by */ 13/* the Free Software Foundation; either version 2 of the License, or */ 14/* (at your option) any later version. */ 15/* */ 16/* This program is distributed in the hope that it will be useful, */ 17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19/* GNU General Public License for more details. */ 20/* */ 21/* NO WARRANTY */ 22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26/* solely responsible for determining the appropriateness of using and */ 27/* distributing the Program and assumes all risks associated with its */ 28/* exercise of rights under this Agreement, including but not limited to */ 29/* the risks and costs of program errors, damage to or loss of data, */ 30/* programs or equipment, and unavailability or interruption of operations. */ 31/* */ 32/* DISCLAIMER OF LIABILITY */ 33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40/* */ 41/* You should have received a copy of the GNU General Public License */ 42/* along with this program; if not, write to the Free Software */ 43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44/* */ 45/* Bugs/Comments/Suggestions should be mailed to: */ 46/* ipslinux@adaptec.com */ 47/* */ 48/*****************************************************************************/ 49 50#ifndef _IPS_H_ 51 #define _IPS_H_ 52 53#include <linux/nmi.h> 54 #include <asm/uaccess.h> 55 #include <asm/io.h> 56 57 /* 58 * Some handy macros 59 */ 60 #define IPS_HA(x) ((ips_ha_t *) x->hostdata) 61 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs) 62 #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \ 63 (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \ 64 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0) 65 #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \ 66 (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \ 67 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0) 68 #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS) 69 #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO) 70 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \ 71 (IPS_IS_TROMBONE(ha) && \ 72 (ips_force_i2o))) ? 1 : 0) 73 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \ 74 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \ 75 (ips_force_memio))) ? 1 : 0) 76 77 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) 78 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG) 79 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \ 80 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST)) 81 82 #define IPS_PRINTK(level, pcidev, format, arg...) \ 83 dev_printk(level , &((pcidev)->dev) , format , ## arg) 84 85 #define MDELAY(n) \ 86 do { \ 87 mdelay(n); \ 88 touch_nmi_watchdog(); \ 89 } while (0) 90 91 #ifndef min 92 #define min(x,y) ((x) < (y) ? x : y) 93 #endif 94 95 #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */ 96 #define __iomem 97 #endif 98 99 #define pci_dma_hi32(a) ((a >> 16) >> 16) 100 #define pci_dma_lo32(a) (a & 0xffffffff) 101 102 #if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G) 103 #define IPS_ENABLE_DMA64 (1) 104 #else 105 #define IPS_ENABLE_DMA64 (0) 106 #endif 107 108 /* 109 * Adapter address map equates 110 */ 111 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */ 112 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */ 113 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */ 114 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */ 115 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */ 116 #define IPS_REG_SQER 0x28 /* Status Q End Reg */ 117 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */ 118 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */ 119 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */ 120 #define IPS_REG_CBSP 0x07 /* CBSP register */ 121 #define IPS_REG_FLAP 0x18 /* Flash address port */ 122 #define IPS_REG_FLDP 0x1C /* Flash data port */ 123 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */ 124 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */ 125 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */ 126 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */ 127 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */ 128 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */ 129 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */ 130 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */ 131 132 /* 133 * Adapter register bit equates 134 */ 135 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */ 136 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */ 137 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */ 138 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */ 139 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */ 140 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */ 141 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */ 142 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */ 143 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */ 144 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */ 145 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */ 146 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */ 147 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/ 148 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/ 149 150 /* 151 * Adapter Command ID Equates 152 */ 153 #define IPS_CMD_GET_LD_INFO 0x19 154 #define IPS_CMD_GET_SUBSYS 0x40 155 #define IPS_CMD_READ_CONF 0x38 156 #define IPS_CMD_RW_NVRAM_PAGE 0xBC 157 #define IPS_CMD_READ 0x02 158 #define IPS_CMD_WRITE 0x03 159 #define IPS_CMD_FFDC 0xD7 160 #define IPS_CMD_ENQUIRY 0x05 161 #define IPS_CMD_FLUSH 0x0A 162 #define IPS_CMD_READ_SG 0x82 163 #define IPS_CMD_WRITE_SG 0x83 164 #define IPS_CMD_DCDB 0x04 165 #define IPS_CMD_DCDB_SG 0x84 166 #define IPS_CMD_EXTENDED_DCDB 0x95 167 #define IPS_CMD_EXTENDED_DCDB_SG 0x96 168 #define IPS_CMD_CONFIG_SYNC 0x58 169 #define IPS_CMD_ERROR_TABLE 0x17 170 #define IPS_CMD_DOWNLOAD 0x20 171 #define IPS_CMD_RW_BIOSFW 0x22 172 #define IPS_CMD_GET_VERSION_INFO 0xC6 173 #define IPS_CMD_RESET_CHANNEL 0x1A 174 175 /* 176 * Adapter Equates 177 */ 178 #define IPS_CSL 0xFF 179 #define IPS_POCL 0x30 180 #define IPS_NORM_STATE 0x00 181 #define IPS_MAX_ADAPTER_TYPES 3 182 #define IPS_MAX_ADAPTERS 16 183 #define IPS_MAX_IOCTL 1 184 #define IPS_MAX_IOCTL_QUEUE 8 185 #define IPS_MAX_QUEUE 128 186 #define IPS_BLKSIZE 512 187 #define IPS_MAX_SG 17 188 #define IPS_MAX_LD 8 189 #define IPS_MAX_CHANNELS 4 190 #define IPS_MAX_TARGETS 15 191 #define IPS_MAX_CHUNKS 16 192 #define IPS_MAX_CMDS 128 193 #define IPS_MAX_XFER 0x10000 194 #define IPS_NVRAM_P5_SIG 0xFFDDBB99 195 #define IPS_MAX_POST_BYTES 0x02 196 #define IPS_MAX_CONFIG_BYTES 0x02 197 #define IPS_GOOD_POST_STATUS 0x80 198 #define IPS_SEM_TIMEOUT 2000 199 #define IPS_IOCTL_COMMAND 0x0D 200 #define IPS_INTR_ON 0 201 #define IPS_INTR_IORL 1 202 #define IPS_FFDC 99 203 #define IPS_ADAPTER_ID 0xF 204 #define IPS_VENDORID_IBM 0x1014 205 #define IPS_VENDORID_ADAPTEC 0x9005 206 #define IPS_DEVICEID_COPPERHEAD 0x002E 207 #define IPS_DEVICEID_MORPHEUS 0x01BD 208 #define IPS_DEVICEID_MARCO 0x0250 209 #define IPS_SUBDEVICEID_4M 0x01BE 210 #define IPS_SUBDEVICEID_4L 0x01BF 211 #define IPS_SUBDEVICEID_4MX 0x0208 212 #define IPS_SUBDEVICEID_4LX 0x020E 213 #define IPS_SUBDEVICEID_5I2 0x0259 214 #define IPS_SUBDEVICEID_5I1 0x0258 215 #define IPS_SUBDEVICEID_6M 0x0279 216 #define IPS_SUBDEVICEID_6I 0x028C 217 #define IPS_SUBDEVICEID_7k 0x028E 218 #define IPS_SUBDEVICEID_7M 0x028F 219 #define IPS_IOCTL_SIZE 8192 220 #define IPS_STATUS_SIZE 4 221 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE 222 #define IPS_IMAGE_SIZE 500 * 1024 223 #define IPS_MEMMAP_SIZE 128 224 #define IPS_ONE_MSEC 1 225 #define IPS_ONE_SEC 1000 226 227 /* 228 * Geometry Settings 229 */ 230 #define IPS_COMP_HEADS 128 231 #define IPS_COMP_SECTORS 32 232 #define IPS_NORM_HEADS 254 233 #define IPS_NORM_SECTORS 63 234 235 /* 236 * Adapter Basic Status Codes 237 */ 238 #define IPS_BASIC_STATUS_MASK 0xFF 239 #define IPS_GSC_STATUS_MASK 0x0F 240 #define IPS_CMD_SUCCESS 0x00 241 #define IPS_CMD_RECOVERED_ERROR 0x01 242 #define IPS_INVAL_OPCO 0x03 243 #define IPS_INVAL_CMD_BLK 0x04 244 #define IPS_INVAL_PARM_BLK 0x05 245 #define IPS_BUSY 0x08 246 #define IPS_CMD_CMPLT_WERROR 0x0C 247 #define IPS_LD_ERROR 0x0D 248 #define IPS_CMD_TIMEOUT 0x0E 249 #define IPS_PHYS_DRV_ERROR 0x0F 250 251 /* 252 * Adapter Extended Status Equates 253 */ 254 #define IPS_ERR_SEL_TO 0xF0 255 #define IPS_ERR_OU_RUN 0xF2 256 #define IPS_ERR_HOST_RESET 0xF7 257 #define IPS_ERR_DEV_RESET 0xF8 258 #define IPS_ERR_RECOVERY 0xFC 259 #define IPS_ERR_CKCOND 0xFF 260 261 /* 262 * Operating System Defines 263 */ 264 #define IPS_OS_WINDOWS_NT 0x01 265 #define IPS_OS_NETWARE 0x02 266 #define IPS_OS_OPENSERVER 0x03 267 #define IPS_OS_UNIXWARE 0x04 268 #define IPS_OS_SOLARIS 0x05 269 #define IPS_OS_OS2 0x06 270 #define IPS_OS_LINUX 0x07 271 #define IPS_OS_FREEBSD 0x08 272 273 /* 274 * Adapter Revision ID's 275 */ 276 #define IPS_REVID_SERVERAID 0x02 277 #define IPS_REVID_NAVAJO 0x03 278 #define IPS_REVID_SERVERAID2 0x04 279 #define IPS_REVID_CLARINETP1 0x05 280 #define IPS_REVID_CLARINETP2 0x07 281 #define IPS_REVID_CLARINETP3 0x0D 282 #define IPS_REVID_TROMBONE32 0x0F 283 #define IPS_REVID_TROMBONE64 0x10 284 285 /* 286 * NVRAM Page 5 Adapter Defines 287 */ 288 #define IPS_ADTYPE_SERVERAID 0x01 289 #define IPS_ADTYPE_SERVERAID2 0x02 290 #define IPS_ADTYPE_NAVAJO 0x03 291 #define IPS_ADTYPE_KIOWA 0x04 292 #define IPS_ADTYPE_SERVERAID3 0x05 293 #define IPS_ADTYPE_SERVERAID3L 0x06 294 #define IPS_ADTYPE_SERVERAID4H 0x07 295 #define IPS_ADTYPE_SERVERAID4M 0x08 296 #define IPS_ADTYPE_SERVERAID4L 0x09 297 #define IPS_ADTYPE_SERVERAID4MX 0x0A 298 #define IPS_ADTYPE_SERVERAID4LX 0x0B 299 #define IPS_ADTYPE_SERVERAID5I2 0x0C 300 #define IPS_ADTYPE_SERVERAID5I1 0x0D 301 #define IPS_ADTYPE_SERVERAID6M 0x0E 302 #define IPS_ADTYPE_SERVERAID6I 0x0F 303 #define IPS_ADTYPE_SERVERAID7t 0x10 304 #define IPS_ADTYPE_SERVERAID7k 0x11 305 #define IPS_ADTYPE_SERVERAID7M 0x12 306 307 /* 308 * Adapter Command/Status Packet Definitions 309 */ 310 #define IPS_SUCCESS 0x01 /* Successfully completed */ 311 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */ 312 #define IPS_FAILURE 0x04 /* Completed with Error */ 313 314 /* 315 * Logical Drive Equates 316 */ 317 #define IPS_LD_OFFLINE 0x02 318 #define IPS_LD_OKAY 0x03 319 #define IPS_LD_FREE 0x00 320 #define IPS_LD_SYS 0x06 321 #define IPS_LD_CRS 0x24 322 323 /* 324 * DCDB Table Equates 325 */ 326 #define IPS_NO_DISCONNECT 0x00 327 #define IPS_DISCONNECT_ALLOWED 0x80 328 #define IPS_NO_AUTO_REQSEN 0x40 329 #define IPS_DATA_NONE 0x00 330 #define IPS_DATA_UNK 0x00 331 #define IPS_DATA_IN 0x01 332 #define IPS_DATA_OUT 0x02 333 #define IPS_TRANSFER64K 0x08 334 #define IPS_NOTIMEOUT 0x00 335 #define IPS_TIMEOUT10 0x10 336 #define IPS_TIMEOUT60 0x20 337 #define IPS_TIMEOUT20M 0x30 338 339 /* 340 * SCSI Inquiry Data Flags 341 */ 342 #define IPS_SCSI_INQ_TYPE_DASD 0x00 343 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03 344 #define IPS_SCSI_INQ_LU_CONNECTED 0x00 345 #define IPS_SCSI_INQ_RD_REV2 0x02 346 #define IPS_SCSI_INQ_REV2 0x02 347 #define IPS_SCSI_INQ_REV3 0x03 348 #define IPS_SCSI_INQ_Address16 0x01 349 #define IPS_SCSI_INQ_Address32 0x02 350 #define IPS_SCSI_INQ_MedChanger 0x08 351 #define IPS_SCSI_INQ_MultiPort 0x10 352 #define IPS_SCSI_INQ_EncServ 0x40 353 #define IPS_SCSI_INQ_SoftReset 0x01 354 #define IPS_SCSI_INQ_CmdQue 0x02 355 #define IPS_SCSI_INQ_Linked 0x08 356 #define IPS_SCSI_INQ_Sync 0x10 357 #define IPS_SCSI_INQ_WBus16 0x20 358 #define IPS_SCSI_INQ_WBus32 0x40 359 #define IPS_SCSI_INQ_RelAdr 0x80 360 361 /* 362 * SCSI Request Sense Data Flags 363 */ 364 #define IPS_SCSI_REQSEN_VALID 0x80 365 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70 366 #define IPS_SCSI_REQSEN_NO_SENSE 0x00 367 368 /* 369 * SCSI Mode Page Equates 370 */ 371 #define IPS_SCSI_MP3_SoftSector 0x01 372 #define IPS_SCSI_MP3_HardSector 0x02 373 #define IPS_SCSI_MP3_Removeable 0x04 374 #define IPS_SCSI_MP3_AllocateSurface 0x08 375 376 /* 377 * HA Flags 378 */ 379 380 #define IPS_HA_ENH_SG 0x1 381 382 /* 383 * SCB Flags 384 */ 385 #define IPS_SCB_MAP_SG 0x00008 386 #define IPS_SCB_MAP_SINGLE 0X00010 387 388 /* 389 * Passthru stuff 390 */ 391 #define IPS_COPPUSRCMD (('C'<<8) | 65) 392 #define IPS_COPPIOCCMD (('C'<<8) | 66) 393 #define IPS_NUMCTRLS (('C'<<8) | 68) 394 #define IPS_CTRLINFO (('C'<<8) | 69) 395 396 /* flashing defines */ 397 #define IPS_FW_IMAGE 0x00 398 #define IPS_BIOS_IMAGE 0x01 399 #define IPS_WRITE_FW 0x01 400 #define IPS_WRITE_BIOS 0x02 401 #define IPS_ERASE_BIOS 0x03 402 #define IPS_BIOS_HEADER 0xC0 403 404 /* time oriented stuff */ 405 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0) 406 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400) 407 408 #define IPS_SECS_MIN 60 409 #define IPS_SECS_HOUR 3600 410 #define IPS_SECS_8HOURS 28800 411 #define IPS_SECS_DAY 86400 412 #define IPS_DAYS_NORMAL_YEAR 365 413 #define IPS_DAYS_LEAP_YEAR 366 414 #define IPS_EPOCH_YEAR 1970 415 416 /* 417 * Scsi_Host Template 418 */ 419 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 420 sector_t capacity, int geom[]); 421 static int ips_slave_configure(struct scsi_device *SDptr); 422 423/* 424 * Raid Command Formats 425 */ 426typedef struct { 427 uint8_t op_code; 428 uint8_t command_id; 429 uint8_t log_drv; 430 uint8_t sg_count; 431 uint32_t lba; 432 uint32_t sg_addr; 433 uint16_t sector_count; 434 uint8_t segment_4G; 435 uint8_t enhanced_sg; 436 uint32_t ccsar; 437 uint32_t cccr; 438} IPS_IO_CMD, *PIPS_IO_CMD; 439 440typedef struct { 441 uint8_t op_code; 442 uint8_t command_id; 443 uint16_t reserved; 444 uint32_t reserved2; 445 uint32_t buffer_addr; 446 uint32_t reserved3; 447 uint32_t ccsar; 448 uint32_t cccr; 449} IPS_LD_CMD, *PIPS_LD_CMD; 450 451typedef struct { 452 uint8_t op_code; 453 uint8_t command_id; 454 uint8_t reserved; 455 uint8_t reserved2; 456 uint32_t reserved3; 457 uint32_t buffer_addr; 458 uint32_t reserved4; 459} IPS_IOCTL_CMD, *PIPS_IOCTL_CMD; 460 461typedef struct { 462 uint8_t op_code; 463 uint8_t command_id; 464 uint8_t channel; 465 uint8_t reserved3; 466 uint8_t reserved4; 467 uint8_t reserved5; 468 uint8_t reserved6; 469 uint8_t reserved7; 470 uint8_t reserved8; 471 uint8_t reserved9; 472 uint8_t reserved10; 473 uint8_t reserved11; 474 uint8_t reserved12; 475 uint8_t reserved13; 476 uint8_t reserved14; 477 uint8_t adapter_flag; 478} IPS_RESET_CMD, *PIPS_RESET_CMD; 479 480typedef struct { 481 uint8_t op_code; 482 uint8_t command_id; 483 uint16_t reserved; 484 uint32_t reserved2; 485 uint32_t dcdb_address; 486 uint16_t reserved3; 487 uint8_t segment_4G; 488 uint8_t enhanced_sg; 489 uint32_t ccsar; 490 uint32_t cccr; 491} IPS_DCDB_CMD, *PIPS_DCDB_CMD; 492 493typedef struct { 494 uint8_t op_code; 495 uint8_t command_id; 496 uint8_t channel; 497 uint8_t source_target; 498 uint32_t reserved; 499 uint32_t reserved2; 500 uint32_t reserved3; 501 uint32_t ccsar; 502 uint32_t cccr; 503} IPS_CS_CMD, *PIPS_CS_CMD; 504 505typedef struct { 506 uint8_t op_code; 507 uint8_t command_id; 508 uint8_t log_drv; 509 uint8_t control; 510 uint32_t reserved; 511 uint32_t reserved2; 512 uint32_t reserved3; 513 uint32_t ccsar; 514 uint32_t cccr; 515} IPS_US_CMD, *PIPS_US_CMD; 516 517typedef struct { 518 uint8_t op_code; 519 uint8_t command_id; 520 uint8_t reserved; 521 uint8_t state; 522 uint32_t reserved2; 523 uint32_t reserved3; 524 uint32_t reserved4; 525 uint32_t ccsar; 526 uint32_t cccr; 527} IPS_FC_CMD, *PIPS_FC_CMD; 528 529typedef struct { 530 uint8_t op_code; 531 uint8_t command_id; 532 uint8_t reserved; 533 uint8_t desc; 534 uint32_t reserved2; 535 uint32_t buffer_addr; 536 uint32_t reserved3; 537 uint32_t ccsar; 538 uint32_t cccr; 539} IPS_STATUS_CMD, *PIPS_STATUS_CMD; 540 541typedef struct { 542 uint8_t op_code; 543 uint8_t command_id; 544 uint8_t page; 545 uint8_t write; 546 uint32_t reserved; 547 uint32_t buffer_addr; 548 uint32_t reserved2; 549 uint32_t ccsar; 550 uint32_t cccr; 551} IPS_NVRAM_CMD, *PIPS_NVRAM_CMD; 552 553typedef struct 554{ 555 uint8_t op_code; 556 uint8_t command_id; 557 uint16_t reserved; 558 uint32_t count; 559 uint32_t buffer_addr; 560 uint32_t reserved2; 561} IPS_VERSION_INFO, *PIPS_VERSION_INFO; 562 563typedef struct { 564 uint8_t op_code; 565 uint8_t command_id; 566 uint8_t reset_count; 567 uint8_t reset_type; 568 uint8_t second; 569 uint8_t minute; 570 uint8_t hour; 571 uint8_t day; 572 uint8_t reserved1[4]; 573 uint8_t month; 574 uint8_t yearH; 575 uint8_t yearL; 576 uint8_t reserved2; 577} IPS_FFDC_CMD, *PIPS_FFDC_CMD; 578 579typedef struct { 580 uint8_t op_code; 581 uint8_t command_id; 582 uint8_t type; 583 uint8_t direction; 584 uint32_t count; 585 uint32_t buffer_addr; 586 uint8_t total_packets; 587 uint8_t packet_num; 588 uint16_t reserved; 589} IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD; 590 591typedef struct { 592 uint8_t op_code; 593 uint8_t command_id; 594 uint8_t type; 595 uint8_t direction; 596 uint32_t count; 597 uint32_t buffer_addr; 598 uint32_t offset; 599} IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD; 600 601typedef union { 602 IPS_IO_CMD basic_io; 603 IPS_LD_CMD logical_info; 604 IPS_IOCTL_CMD ioctl_info; 605 IPS_DCDB_CMD dcdb; 606 IPS_CS_CMD config_sync; 607 IPS_US_CMD unlock_stripe; 608 IPS_FC_CMD flush_cache; 609 IPS_STATUS_CMD status; 610 IPS_NVRAM_CMD nvram; 611 IPS_FFDC_CMD ffdc; 612 IPS_FLASHFW_CMD flashfw; 613 IPS_FLASHBIOS_CMD flashbios; 614 IPS_VERSION_INFO version_info; 615 IPS_RESET_CMD reset; 616} IPS_HOST_COMMAND, *PIPS_HOST_COMMAND; 617 618typedef struct { 619 uint8_t logical_id; 620 uint8_t reserved; 621 uint8_t raid_level; 622 uint8_t state; 623 uint32_t sector_count; 624} IPS_DRIVE_INFO, *PIPS_DRIVE_INFO; 625 626typedef struct { 627 uint8_t no_of_log_drive; 628 uint8_t reserved[3]; 629 IPS_DRIVE_INFO drive_info[IPS_MAX_LD]; 630} IPS_LD_INFO, *PIPS_LD_INFO; 631 632typedef struct { 633 uint8_t device_address; 634 uint8_t cmd_attribute; 635 uint16_t transfer_length; 636 uint32_t buffer_pointer; 637 uint8_t cdb_length; 638 uint8_t sense_length; 639 uint8_t sg_count; 640 uint8_t reserved; 641 uint8_t scsi_cdb[12]; 642 uint8_t sense_info[64]; 643 uint8_t scsi_status; 644 uint8_t reserved2[3]; 645} IPS_DCDB_TABLE, *PIPS_DCDB_TABLE; 646 647typedef struct { 648 uint8_t device_address; 649 uint8_t cmd_attribute; 650 uint8_t cdb_length; 651 uint8_t reserved_for_LUN; 652 uint32_t transfer_length; 653 uint32_t buffer_pointer; 654 uint16_t sg_count; 655 uint8_t sense_length; 656 uint8_t scsi_status; 657 uint32_t reserved; 658 uint8_t scsi_cdb[16]; 659 uint8_t sense_info[56]; 660} IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE; 661 662typedef union { 663 struct { 664 volatile uint8_t reserved; 665 volatile uint8_t command_id; 666 volatile uint8_t basic_status; 667 volatile uint8_t extended_status; 668 } fields; 669 670 volatile uint32_t value; 671} IPS_STATUS, *PIPS_STATUS; 672 673typedef struct { 674 IPS_STATUS status[IPS_MAX_CMDS + 1]; 675 volatile PIPS_STATUS p_status_start; 676 volatile PIPS_STATUS p_status_end; 677 volatile PIPS_STATUS p_status_tail; 678 volatile uint32_t hw_status_start; 679 volatile uint32_t hw_status_tail; 680} IPS_ADAPTER, *PIPS_ADAPTER; 681 682typedef struct { 683 uint8_t ucLogDriveCount; 684 uint8_t ucMiscFlag; 685 uint8_t ucSLTFlag; 686 uint8_t ucBSTFlag; 687 uint8_t ucPwrChgCnt; 688 uint8_t ucWrongAdrCnt; 689 uint8_t ucUnidentCnt; 690 uint8_t ucNVramDevChgCnt; 691 uint8_t CodeBlkVersion[8]; 692 uint8_t BootBlkVersion[8]; 693 uint32_t ulDriveSize[IPS_MAX_LD]; 694 uint8_t ucConcurrentCmdCount; 695 uint8_t ucMaxPhysicalDevices; 696 uint16_t usFlashRepgmCount; 697 uint8_t ucDefunctDiskCount; 698 uint8_t ucRebuildFlag; 699 uint8_t ucOfflineLogDrvCount; 700 uint8_t ucCriticalDrvCount; 701 uint16_t usConfigUpdateCount; 702 uint8_t ucBlkFlag; 703 uint8_t reserved; 704 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)]; 705} IPS_ENQ, *PIPS_ENQ; 706 707typedef struct { 708 uint8_t ucInitiator; 709 uint8_t ucParameters; 710 uint8_t ucMiscFlag; 711 uint8_t ucState; 712 uint32_t ulBlockCount; 713 uint8_t ucDeviceId[28]; 714} IPS_DEVSTATE, *PIPS_DEVSTATE; 715 716typedef struct { 717 uint8_t ucChn; 718 uint8_t ucTgt; 719 uint16_t ucReserved; 720 uint32_t ulStartSect; 721 uint32_t ulNoOfSects; 722} IPS_CHUNK, *PIPS_CHUNK; 723 724typedef struct { 725 uint16_t ucUserField; 726 uint8_t ucState; 727 uint8_t ucRaidCacheParam; 728 uint8_t ucNoOfChunkUnits; 729 uint8_t ucStripeSize; 730 uint8_t ucParams; 731 uint8_t ucReserved; 732 uint32_t ulLogDrvSize; 733 IPS_CHUNK chunk[IPS_MAX_CHUNKS]; 734} IPS_LD, *PIPS_LD; 735 736typedef struct { 737 uint8_t board_disc[8]; 738 uint8_t processor[8]; 739 uint8_t ucNoChanType; 740 uint8_t ucNoHostIntType; 741 uint8_t ucCompression; 742 uint8_t ucNvramType; 743 uint32_t ulNvramSize; 744} IPS_HARDWARE, *PIPS_HARDWARE; 745 746typedef struct { 747 uint8_t ucLogDriveCount; 748 uint8_t ucDateD; 749 uint8_t ucDateM; 750 uint8_t ucDateY; 751 uint8_t init_id[4]; 752 uint8_t host_id[12]; 753 uint8_t time_sign[8]; 754 uint32_t UserOpt; 755 uint16_t user_field; 756 uint8_t ucRebuildRate; 757 uint8_t ucReserve; 758 IPS_HARDWARE hardware_disc; 759 IPS_LD logical_drive[IPS_MAX_LD]; 760 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1]; 761 uint8_t reserved[512]; 762} IPS_CONF, *PIPS_CONF; 763 764typedef struct { 765 uint32_t signature; 766 uint8_t reserved1; 767 uint8_t adapter_slot; 768 uint16_t adapter_type; 769 uint8_t ctrl_bios[8]; 770 uint8_t versioning; /* 1 = Versioning Supported, else 0 */ 771 uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */ 772 uint8_t reserved2; 773 uint8_t operating_system; 774 uint8_t driver_high[4]; 775 uint8_t driver_low[4]; 776 uint8_t BiosCompatibilityID[8]; 777 uint8_t ReservedForOS2[8]; 778 uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */ 779 uint8_t bios_low[4]; 780 uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */ 781 uint8_t Filler[60]; 782} IPS_NVRAM_P5, *PIPS_NVRAM_P5; 783 784/*--------------------------------------------------------------------------*/ 785/* Data returned from a GetVersion Command */ 786/*--------------------------------------------------------------------------*/ 787 788 /* SubSystem Parameter[4] */ 789#define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */ 790 791typedef struct 792{ 793 uint32_t revision; 794 uint8_t bootBlkVersion[32]; 795 uint8_t bootBlkAttributes[4]; 796 uint8_t codeBlkVersion[32]; 797 uint8_t biosVersion[32]; 798 uint8_t biosAttributes[4]; 799 uint8_t compatibilityId[32]; 800 uint8_t reserved[4]; 801} IPS_VERSION_DATA; 802 803 804typedef struct _IPS_SUBSYS { 805 uint32_t param[128]; 806} IPS_SUBSYS, *PIPS_SUBSYS; 807 808/** 809 ** SCSI Structures 810 **/ 811 812/* 813 * Inquiry Data Format 814 */ 815typedef struct { 816 uint8_t DeviceType; 817 uint8_t DeviceTypeQualifier; 818 uint8_t Version; 819 uint8_t ResponseDataFormat; 820 uint8_t AdditionalLength; 821 uint8_t Reserved; 822 uint8_t Flags[2]; 823 uint8_t VendorId[8]; 824 uint8_t ProductId[16]; 825 uint8_t ProductRevisionLevel[4]; 826 uint8_t Reserved2; /* Provides NULL terminator to name */ 827} IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA; 828 829/* 830 * Read Capacity Data Format 831 */ 832typedef struct { 833 uint32_t lba; 834 uint32_t len; 835} IPS_SCSI_CAPACITY; 836 837/* 838 * Request Sense Data Format 839 */ 840typedef struct { 841 uint8_t ResponseCode; 842 uint8_t SegmentNumber; 843 uint8_t Flags; 844 uint8_t Information[4]; 845 uint8_t AdditionalLength; 846 uint8_t CommandSpecific[4]; 847 uint8_t AdditionalSenseCode; 848 uint8_t AdditionalSenseCodeQual; 849 uint8_t FRUCode; 850 uint8_t SenseKeySpecific[3]; 851} IPS_SCSI_REQSEN; 852 853/* 854 * Sense Data Format - Page 3 855 */ 856typedef struct { 857 uint8_t PageCode; 858 uint8_t PageLength; 859 uint16_t TracksPerZone; 860 uint16_t AltSectorsPerZone; 861 uint16_t AltTracksPerZone; 862 uint16_t AltTracksPerVolume; 863 uint16_t SectorsPerTrack; 864 uint16_t BytesPerSector; 865 uint16_t Interleave; 866 uint16_t TrackSkew; 867 uint16_t CylinderSkew; 868 uint8_t flags; 869 uint8_t reserved[3]; 870} IPS_SCSI_MODE_PAGE3; 871 872/* 873 * Sense Data Format - Page 4 874 */ 875typedef struct { 876 uint8_t PageCode; 877 uint8_t PageLength; 878 uint16_t CylindersHigh; 879 uint8_t CylindersLow; 880 uint8_t Heads; 881 uint16_t WritePrecompHigh; 882 uint8_t WritePrecompLow; 883 uint16_t ReducedWriteCurrentHigh; 884 uint8_t ReducedWriteCurrentLow; 885 uint16_t StepRate; 886 uint16_t LandingZoneHigh; 887 uint8_t LandingZoneLow; 888 uint8_t flags; 889 uint8_t RotationalOffset; 890 uint8_t Reserved; 891 uint16_t MediumRotationRate; 892 uint8_t Reserved2[2]; 893} IPS_SCSI_MODE_PAGE4; 894 895/* 896 * Sense Data Format - Page 8 897 */ 898typedef struct { 899 uint8_t PageCode; 900 uint8_t PageLength; 901 uint8_t flags; 902 uint8_t RetentPrio; 903 uint16_t DisPrefetchLen; 904 uint16_t MinPrefetchLen; 905 uint16_t MaxPrefetchLen; 906 uint16_t MaxPrefetchCeiling; 907} IPS_SCSI_MODE_PAGE8; 908 909/* 910 * Sense Data Format - Block Descriptor (DASD) 911 */ 912typedef struct { 913 uint32_t NumberOfBlocks; 914 uint8_t DensityCode; 915 uint16_t BlockLengthHigh; 916 uint8_t BlockLengthLow; 917} IPS_SCSI_MODE_PAGE_BLKDESC; 918 919/* 920 * Sense Data Format - Mode Page Header 921 */ 922typedef struct { 923 uint8_t DataLength; 924 uint8_t MediumType; 925 uint8_t Reserved; 926 uint8_t BlockDescLength; 927} IPS_SCSI_MODE_PAGE_HEADER; 928 929typedef struct { 930 IPS_SCSI_MODE_PAGE_HEADER hdr; 931 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc; 932 933 union { 934 IPS_SCSI_MODE_PAGE3 pg3; 935 IPS_SCSI_MODE_PAGE4 pg4; 936 IPS_SCSI_MODE_PAGE8 pg8; 937 } pdata; 938} IPS_SCSI_MODE_PAGE_DATA; 939 940/* 941 * Scatter Gather list format 942 */ 943typedef struct ips_sglist { 944 uint32_t address; 945 uint32_t length; 946} IPS_STD_SG_LIST; 947 948typedef struct ips_enh_sglist { 949 uint32_t address_lo; 950 uint32_t address_hi; 951 uint32_t length; 952 uint32_t reserved; 953} IPS_ENH_SG_LIST; 954 955typedef union { 956 void *list; 957 IPS_STD_SG_LIST *std_list; 958 IPS_ENH_SG_LIST *enh_list; 959} IPS_SG_LIST; 960 961typedef struct { 962 char *option_name; 963 int *option_flag; 964 int option_value; 965} IPS_OPTION; 966 967/* 968 * Status Info 969 */ 970typedef struct ips_stat { 971 uint32_t residue_len; 972 void *scb_addr; 973 uint8_t padding[12 - sizeof(void *)]; 974} ips_stat_t; 975 976/* 977 * SCB Queue Format 978 */ 979typedef struct ips_scb_queue { 980 struct ips_scb *head; 981 struct ips_scb *tail; 982 int count; 983} ips_scb_queue_t; 984 985/* 986 * Wait queue_format 987 */ 988typedef struct ips_wait_queue { 989 struct scsi_cmnd *head; 990 struct scsi_cmnd *tail; 991 int count; 992} ips_wait_queue_t; 993 994typedef struct ips_copp_wait_item { 995 struct scsi_cmnd *scsi_cmd; 996 struct ips_copp_wait_item *next; 997} ips_copp_wait_item_t; 998 999typedef struct ips_copp_queue { 1000 struct ips_copp_wait_item *head; 1001 struct ips_copp_wait_item *tail; 1002 int count; 1003} ips_copp_queue_t; 1004 1005/* forward decl for host structure */ 1006struct ips_ha; 1007 1008typedef struct { 1009 int (*reset)(struct ips_ha *); 1010 int (*issue)(struct ips_ha *, struct ips_scb *); 1011 int (*isinit)(struct ips_ha *); 1012 int (*isintr)(struct ips_ha *); 1013 int (*init)(struct ips_ha *); 1014 int (*erasebios)(struct ips_ha *); 1015 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t); 1016 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t); 1017 void (*statinit)(struct ips_ha *); 1018 int (*intr)(struct ips_ha *); 1019 void (*enableint)(struct ips_ha *); 1020 uint32_t (*statupd)(struct ips_ha *); 1021} ips_hw_func_t; 1022 1023typedef struct ips_ha { 1024 uint8_t ha_id[IPS_MAX_CHANNELS+1]; 1025 uint32_t dcdb_active[IPS_MAX_CHANNELS]; 1026 uint32_t io_addr; /* Base I/O address */ 1027 uint8_t ntargets; /* Number of targets */ 1028 uint8_t nbus; /* Number of buses */ 1029 uint8_t nlun; /* Number of Luns */ 1030 uint16_t ad_type; /* Adapter type */ 1031 uint16_t host_num; /* Adapter number */ 1032 uint32_t max_xfer; /* Maximum Xfer size */ 1033 uint32_t max_cmds; /* Max concurrent commands */ 1034 uint32_t num_ioctl; /* Number of Ioctls */ 1035 ips_stat_t sp; /* Status packer pointer */ 1036 struct ips_scb *scbs; /* Array of all CCBS */ 1037 struct ips_scb *scb_freelist; /* SCB free list */ 1038 ips_wait_queue_t scb_waitlist; /* Pending SCB list */ 1039 ips_copp_queue_t copp_waitlist; /* Pending PT list */ 1040 ips_scb_queue_t scb_activelist; /* Active SCB list */ 1041 IPS_IO_CMD *dummy; /* dummy command */ 1042 IPS_ADAPTER *adapt; /* Adapter status area */ 1043 IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */ 1044 dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */ 1045 IPS_ENQ *enq; /* Adapter Enquiry data */ 1046 IPS_CONF *conf; /* Adapter config data */ 1047 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */ 1048 IPS_SUBSYS *subsys; /* Subsystem parameters */ 1049 char *ioctl_data; /* IOCTL data area */ 1050 uint32_t ioctl_datasize; /* IOCTL data size */ 1051 uint32_t cmd_in_progress; /* Current command in progress*/ 1052 int flags; /* */ 1053 uint8_t waitflag; /* are we waiting for cmd */ 1054 uint8_t active; 1055 int ioctl_reset; /* IOCTL Requested Reset Flag */ 1056 uint16_t reset_count; /* number of resets */ 1057 time_t last_ffdc; /* last time we sent ffdc info*/ 1058 uint8_t slot_num; /* PCI Slot Number */ 1059 int ioctl_len; /* size of ioctl buffer */ 1060 dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/ 1061 uint8_t bios_version[8]; /* BIOS Revision */ 1062 uint32_t mem_addr; /* Memory mapped address */ 1063 uint32_t io_len; /* Size of IO Address */ 1064 uint32_t mem_len; /* Size of memory address */ 1065 char __iomem *mem_ptr; /* Memory mapped Ptr */ 1066 char __iomem *ioremap_ptr;/* ioremapped memory pointer */ 1067 ips_hw_func_t func; /* hw function pointers */ 1068 struct pci_dev *pcidev; /* PCI device handle */ 1069 char *flash_data; /* Save Area for flash data */ 1070 int flash_len; /* length of flash buffer */ 1071 u32 flash_datasize; /* Save Area for flash data size */ 1072 dma_addr_t flash_busaddr; /* dma address of flash buffer*/ 1073 dma_addr_t enq_busaddr; /* dma address of enq struct */ 1074 uint8_t requires_esl; /* Requires an EraseStripeLock */ 1075} ips_ha_t; 1076 1077typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *); 1078 1079/* 1080 * SCB Format 1081 */ 1082typedef struct ips_scb { 1083 IPS_HOST_COMMAND cmd; 1084 IPS_DCDB_TABLE dcdb; 1085 uint8_t target_id; 1086 uint8_t bus; 1087 uint8_t lun; 1088 uint8_t cdb[12]; 1089 uint32_t scb_busaddr; 1090 uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility 1091 uint32_t timeout; 1092 uint8_t basic_status; 1093 uint8_t extended_status; 1094 uint8_t breakup; 1095 uint8_t sg_break; 1096 uint32_t data_len; 1097 uint32_t sg_len; 1098 uint32_t flags; 1099 uint32_t op_code; 1100 IPS_SG_LIST sg_list; 1101 struct scsi_cmnd *scsi_cmd; 1102 struct ips_scb *q_next; 1103 ips_scb_callback callback; 1104 uint32_t sg_busaddr; 1105 int sg_count; 1106 dma_addr_t data_busaddr; 1107} ips_scb_t; 1108 1109typedef struct ips_scb_pt { 1110 IPS_HOST_COMMAND cmd; 1111 IPS_DCDB_TABLE dcdb; 1112 uint8_t target_id; 1113 uint8_t bus; 1114 uint8_t lun; 1115 uint8_t cdb[12]; 1116 uint32_t scb_busaddr; 1117 uint32_t data_busaddr; 1118 uint32_t timeout; 1119 uint8_t basic_status; 1120 uint8_t extended_status; 1121 uint16_t breakup; 1122 uint32_t data_len; 1123 uint32_t sg_len; 1124 uint32_t flags; 1125 uint32_t op_code; 1126 IPS_SG_LIST *sg_list; 1127 struct scsi_cmnd *scsi_cmd; 1128 struct ips_scb *q_next; 1129 ips_scb_callback callback; 1130} ips_scb_pt_t; 1131 1132/* 1133 * Passthru Command Format 1134 */ 1135typedef struct { 1136 uint8_t CoppID[4]; 1137 uint32_t CoppCmd; 1138 uint32_t PtBuffer; 1139 uint8_t *CmdBuffer; 1140 uint32_t CmdBSize; 1141 ips_scb_pt_t CoppCP; 1142 uint32_t TimeOut; 1143 uint8_t BasicStatus; 1144 uint8_t ExtendedStatus; 1145 uint8_t AdapterType; 1146 uint8_t reserved; 1147} ips_passthru_t; 1148 1149#endif 1150 1151/* The Version Information below gets created by SED during the build process. */ 1152/* Do not modify the next line; it's what SED is looking for to do the insert. */ 1153/* Version Info */ 1154/************************************************************************* 1155* 1156* VERSION.H -- version numbers and copyright notices in various formats 1157* 1158*************************************************************************/ 1159 1160#define IPS_VER_MAJOR 7 1161#define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR) 1162#define IPS_VER_MINOR 12 1163#define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR) 1164#define IPS_VER_BUILD 05 1165#define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD) 1166#define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \ 1167 IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING 1168#define IPS_RELEASE_ID 0x00020000 1169#define IPS_BUILD_IDENT 761 1170#define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved." 1171#define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved." 1172#define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved." 1173#define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002." 1174 1175/* Version numbers for various adapters */ 1176#define IPS_VER_SERVERAID1 "2.25.01" 1177#define IPS_VER_SERVERAID2 "2.88.13" 1178#define IPS_VER_NAVAJO "2.88.13" 1179#define IPS_VER_SERVERAID3 "6.10.24" 1180#define IPS_VER_SERVERAID4H "7.12.02" 1181#define IPS_VER_SERVERAID4MLx "7.12.02" 1182#define IPS_VER_SARASOTA "7.12.02" 1183#define IPS_VER_MARCO "7.12.02" 1184#define IPS_VER_SEBRING "7.12.02" 1185#define IPS_VER_KEYWEST "7.12.02" 1186 1187/* Compatibility IDs for various adapters */ 1188#define IPS_COMPAT_UNKNOWN "" 1189#define IPS_COMPAT_CURRENT "KW710" 1190#define IPS_COMPAT_SERVERAID1 "2.25.01" 1191#define IPS_COMPAT_SERVERAID2 "2.88.13" 1192#define IPS_COMPAT_NAVAJO "2.88.13" 1193#define IPS_COMPAT_KIOWA "2.88.13" 1194#define IPS_COMPAT_SERVERAID3H "SB610" 1195#define IPS_COMPAT_SERVERAID3L "SB610" 1196#define IPS_COMPAT_SERVERAID4H "KW710" 1197#define IPS_COMPAT_SERVERAID4M "KW710" 1198#define IPS_COMPAT_SERVERAID4L "KW710" 1199#define IPS_COMPAT_SERVERAID4Mx "KW710" 1200#define IPS_COMPAT_SERVERAID4Lx "KW710" 1201#define IPS_COMPAT_SARASOTA "KW710" 1202#define IPS_COMPAT_MARCO "KW710" 1203#define IPS_COMPAT_SEBRING "KW710" 1204#define IPS_COMPAT_TAMPA "KW710" 1205#define IPS_COMPAT_KEYWEST "KW710" 1206#define IPS_COMPAT_BIOS "KW710" 1207 1208#define IPS_COMPAT_MAX_ADAPTER_TYPE 18 1209#define IPS_COMPAT_ID_LENGTH 8 1210 1211#define IPS_DEFINE_COMPAT_TABLE(tablename) \ 1212 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \ 1213 IPS_COMPAT_UNKNOWN, \ 1214 IPS_COMPAT_SERVERAID1, \ 1215 IPS_COMPAT_SERVERAID2, \ 1216 IPS_COMPAT_NAVAJO, \ 1217 IPS_COMPAT_KIOWA, \ 1218 IPS_COMPAT_SERVERAID3H, \ 1219 IPS_COMPAT_SERVERAID3L, \ 1220 IPS_COMPAT_SERVERAID4H, \ 1221 IPS_COMPAT_SERVERAID4M, \ 1222 IPS_COMPAT_SERVERAID4L, \ 1223 IPS_COMPAT_SERVERAID4Mx, \ 1224 IPS_COMPAT_SERVERAID4Lx, \ 1225 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \ 1226 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \ 1227 IPS_COMPAT_MARCO, \ 1228 IPS_COMPAT_SEBRING, \ 1229 IPS_COMPAT_TAMPA, \ 1230 IPS_COMPAT_KEYWEST \ 1231 } 1232 1233 1234/* 1235 * Overrides for Emacs so that we almost follow Linus's tabbing style. 1236 * Emacs will notice this stuff at the end of the file and automatically 1237 * adjust the settings for this buffer only. This must remain at the end 1238 * of the file. 1239 * --------------------------------------------------------------------------- 1240 * Local variables: 1241 * c-indent-level: 2 1242 * c-brace-imaginary-offset: 0 1243 * c-brace-offset: -2 1244 * c-argdecl-indent: 2 1245 * c-label-offset: -2 1246 * c-continued-statement-offset: 2 1247 * c-continued-brace-offset: 0 1248 * indent-tabs-mode: nil 1249 * tab-width: 8 1250 * End: 1251 */ 1252