1/* 2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited 3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_platform.h> 13#include <linux/platform_device.h> 14#include <dt-bindings/reset/stih407-resets.h> 15#include "reset-syscfg.h" 16 17/* STiH407 Peripheral powerdown definitions. */ 18static const char stih407_core[] = "st,stih407-core-syscfg"; 19static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg"; 20static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; 21 22#define STIH407_PDN_0(_bit) \ 23 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) 24#define STIH407_PDN_1(_bit) \ 25 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) 26#define STIH407_PDN_ETH(_bit, _stat) \ 27 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) 28 29/* Powerdown requests control 0 */ 30#define SYSCFG_5000 0x0 31#define SYSSTAT_5500 0x7d0 32/* Powerdown requests control 1 (High Speed Links) */ 33#define SYSCFG_5001 0x4 34#define SYSSTAT_5501 0x7d4 35 36/* Ethernet powerdown/status/reset */ 37#define SYSCFG_4032 0x80 38#define SYSSTAT_4520 0x820 39#define SYSCFG_4002 0x8 40 41static const struct syscfg_reset_channel_data stih407_powerdowns[] = { 42 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), 43 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), 44 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), 45 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), 46 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), 47 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), 48 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), 49 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), 50 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), 51 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), 52}; 53 54/* Reset Generator control 0/1 */ 55#define SYSCFG_5131 0x20c 56#define SYSCFG_5132 0x210 57 58#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ 59 60#define STIH407_SRST_CORE(_reg, _bit) \ 61 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) 62 63#define STIH407_SRST_SBC(_reg, _bit) \ 64 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) 65 66#define STIH407_SRST_LPM(_reg, _bit) \ 67 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) 68 69static const struct syscfg_reset_channel_data stih407_softresets[] = { 70 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), 71 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), 72 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), 73 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), 74 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), 75 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), 76 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), 77 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), 78 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), 79 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), 80 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), 81 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), 82 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), 83 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), 84 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), 85 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), 86 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), 87 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), 88 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), 89 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), 90 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), 91 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), 92 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), 93 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), 94 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), 95 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), 96 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), 97 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), 98 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), 99}; 100 101/* PicoPHY reset/control */ 102#define SYSCFG_5061 0x0f4 103 104static const struct syscfg_reset_channel_data stih407_picophyresets[] = { 105 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), 106 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), 107 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), 108}; 109 110static const struct syscfg_reset_controller_data stih407_powerdown_controller = { 111 .wait_for_ack = true, 112 .nr_channels = ARRAY_SIZE(stih407_powerdowns), 113 .channels = stih407_powerdowns, 114}; 115 116static const struct syscfg_reset_controller_data stih407_softreset_controller = { 117 .wait_for_ack = false, 118 .active_low = true, 119 .nr_channels = ARRAY_SIZE(stih407_softresets), 120 .channels = stih407_softresets, 121}; 122 123static const struct syscfg_reset_controller_data stih407_picophyreset_controller = { 124 .wait_for_ack = false, 125 .nr_channels = ARRAY_SIZE(stih407_picophyresets), 126 .channels = stih407_picophyresets, 127}; 128 129static const struct of_device_id stih407_reset_match[] = { 130 { 131 .compatible = "st,stih407-powerdown", 132 .data = &stih407_powerdown_controller, 133 }, 134 { 135 .compatible = "st,stih407-softreset", 136 .data = &stih407_softreset_controller, 137 }, 138 { 139 .compatible = "st,stih407-picophyreset", 140 .data = &stih407_picophyreset_controller, 141 }, 142 { /* sentinel */ }, 143}; 144 145static struct platform_driver stih407_reset_driver = { 146 .probe = syscfg_reset_probe, 147 .driver = { 148 .name = "reset-stih407", 149 .of_match_table = stih407_reset_match, 150 }, 151}; 152 153static int __init stih407_reset_init(void) 154{ 155 return platform_driver_register(&stih407_reset_driver); 156} 157 158arch_initcall(stih407_reset_init); 159