1/* 2 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * Register definitions taken from original Realtek rtl8723au driver 14 */ 15 16#include <asm/byteorder.h> 17 18#define RTL8XXXU_DEBUG_REG_WRITE 0x01 19#define RTL8XXXU_DEBUG_REG_READ 0x02 20#define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 21#define RTL8XXXU_DEBUG_RFREG_READ 0x08 22#define RTL8XXXU_DEBUG_CHANNEL 0x10 23#define RTL8XXXU_DEBUG_TX 0x20 24#define RTL8XXXU_DEBUG_TX_DUMP 0x40 25#define RTL8XXXU_DEBUG_RX 0x80 26#define RTL8XXXU_DEBUG_RX_DUMP 0x100 27#define RTL8XXXU_DEBUG_USB 0x200 28#define RTL8XXXU_DEBUG_KEY 0x400 29#define RTL8XXXU_DEBUG_H2C 0x800 30#define RTL8XXXU_DEBUG_ACTION 0x1000 31#define RTL8XXXU_DEBUG_EFUSE 0x2000 32 33#define RTW_USB_CONTROL_MSG_TIMEOUT 500 34#define RTL8XXXU_MAX_REG_POLL 500 35#define USB_INTR_CONTENT_LENGTH 56 36 37#define RTL8XXXU_OUT_ENDPOINTS 3 38 39#define REALTEK_USB_READ 0xc0 40#define REALTEK_USB_WRITE 0x40 41#define REALTEK_USB_CMD_REQ 0x05 42#define REALTEK_USB_CMD_IDX 0x00 43 44#define TX_TOTAL_PAGE_NUM 0xf8 45/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 46#define TX_PAGE_NUM_PUBQ 0xe7 47#define TX_PAGE_NUM_HI_PQ 0x0c 48#define TX_PAGE_NUM_LO_PQ 0x02 49#define TX_PAGE_NUM_NORM_PQ 0x02 50 51#define RTL_FW_PAGE_SIZE 4096 52#define RTL8XXXU_FIRMWARE_POLL_MAX 1000 53 54#define RTL8723A_CHANNEL_GROUPS 3 55#define RTL8723A_MAX_RF_PATHS 2 56#define RF6052_MAX_TX_PWR 0x3f 57 58#define EFUSE_MAP_LEN_8723A 256 59#define EFUSE_MAX_SECTION_8723A 32 60#define EFUSE_REAL_CONTENT_LEN_8723A 512 61#define EFUSE_BT_MAP_LEN_8723A 1024 62#define EFUSE_MAX_WORD_UNIT 4 63 64struct rtl8xxxu_rx_desc { 65#ifdef __LITTLE_ENDIAN 66 u32 pktlen:14; 67 u32 crc32:1; 68 u32 icverr:1; 69 u32 drvinfo_sz:4; 70 u32 security:3; 71 u32 qos:1; 72 u32 shift:2; 73 u32 phy_stats:1; 74 u32 swdec:1; 75 u32 ls:1; 76 u32 fs:1; 77 u32 eor:1; 78 u32 own:1; 79 80 u32 macid:5; 81 u32 tid:4; 82 u32 hwrsvd:4; 83 u32 amsdu:1; 84 u32 paggr:1; 85 u32 faggr:1; 86 u32 a1fit:4; 87 u32 a2fit:4; 88 u32 pam:1; 89 u32 pwr:1; 90 u32 md:1; 91 u32 mf:1; 92 u32 type:2; 93 u32 mc:1; 94 u32 bc:1; 95 96 u32 seq:12; 97 u32 frag:4; 98 u32 nextpktlen:14; 99 u32 nextind:1; 100 u32 reserved0:1; 101 102 u32 rxmcs:6; 103 u32 rxht:1; 104 u32 gf:1; 105 u32 splcp:1; 106 u32 bw:1; 107 u32 htc:1; 108 u32 eosp:1; 109 u32 bssidfit:2; 110 u32 reserved1:16; 111 u32 unicastwake:1; 112 u32 magicwake:1; 113 114 u32 pattern0match:1; 115 u32 pattern1match:1; 116 u32 pattern2match:1; 117 u32 pattern3match:1; 118 u32 pattern4match:1; 119 u32 pattern5match:1; 120 u32 pattern6match:1; 121 u32 pattern7match:1; 122 u32 pattern8match:1; 123 u32 pattern9match:1; 124 u32 patternamatch:1; 125 u32 patternbmatch:1; 126 u32 patterncmatch:1; 127 u32 reserved2:19; 128#else 129 u32 own:1; 130 u32 eor:1; 131 u32 fs:1; 132 u32 ls:1; 133 u32 swdec:1; 134 u32 phy_stats:1; 135 u32 shift:2; 136 u32 qos:1; 137 u32 security:3; 138 u32 drvinfo_sz:4; 139 u32 icverr:1; 140 u32 crc32:1; 141 u32 pktlen:14; 142 143 u32 bc:1; 144 u32 mc:1; 145 u32 type:2; 146 u32 mf:1; 147 u32 md:1; 148 u32 pwr:1; 149 u32 pam:1; 150 u32 a2fit:4; 151 u32 a1fit:4; 152 u32 faggr:1; 153 u32 paggr:1; 154 u32 amsdu:1; 155 u32 hwrsvd:4; 156 u32 tid:4; 157 u32 macid:5; 158 159 u32 reserved0:1; 160 u32 nextind:1; 161 u32 nextpktlen:14; 162 u32 frag:4; 163 u32 seq:12; 164 165 u32 magicwake:1; 166 u32 unicastwake:1; 167 u32 reserved1:16; 168 u32 bssidfit:2; 169 u32 eosp:1; 170 u32 htc:1; 171 u32 bw:1; 172 u32 splcp:1; 173 u32 gf:1; 174 u32 rxht:1; 175 u32 rxmcs:6; 176 177 u32 reserved2:19; 178 u32 patterncmatch:1; 179 u32 patternbmatch:1; 180 u32 patternamatch:1; 181 u32 pattern9match:1; 182 u32 pattern8match:1; 183 u32 pattern7match:1; 184 u32 pattern6match:1; 185 u32 pattern5match:1; 186 u32 pattern4match:1; 187 u32 pattern3match:1; 188 u32 pattern2match:1; 189 u32 pattern1match:1; 190 u32 pattern0match:1; 191#endif 192 __le32 tsfl; 193#if 0 194 u32 bassn:12; 195 u32 bavld:1; 196 u32 reserved3:19; 197#endif 198}; 199 200struct rtl8xxxu_tx_desc { 201 __le16 pkt_size; 202 u8 pkt_offset; 203 u8 txdw0; 204 __le32 txdw1; 205 __le32 txdw2; 206 __le32 txdw3; 207 __le32 txdw4; 208 __le32 txdw5; 209 __le32 txdw6; 210 __le16 csum; 211 __le16 txdw7; 212}; 213 214/* CCK Rates, TxHT = 0 */ 215#define DESC_RATE_1M 0x00 216#define DESC_RATE_2M 0x01 217#define DESC_RATE_5_5M 0x02 218#define DESC_RATE_11M 0x03 219 220/* OFDM Rates, TxHT = 0 */ 221#define DESC_RATE_6M 0x04 222#define DESC_RATE_9M 0x05 223#define DESC_RATE_12M 0x06 224#define DESC_RATE_18M 0x07 225#define DESC_RATE_24M 0x08 226#define DESC_RATE_36M 0x09 227#define DESC_RATE_48M 0x0a 228#define DESC_RATE_54M 0x0b 229 230/* MCS Rates, TxHT = 1 */ 231#define DESC_RATE_MCS0 0x0c 232#define DESC_RATE_MCS1 0x0d 233#define DESC_RATE_MCS2 0x0e 234#define DESC_RATE_MCS3 0x0f 235#define DESC_RATE_MCS4 0x10 236#define DESC_RATE_MCS5 0x11 237#define DESC_RATE_MCS6 0x12 238#define DESC_RATE_MCS7 0x13 239#define DESC_RATE_MCS8 0x14 240#define DESC_RATE_MCS9 0x15 241#define DESC_RATE_MCS10 0x16 242#define DESC_RATE_MCS11 0x17 243#define DESC_RATE_MCS12 0x18 244#define DESC_RATE_MCS13 0x19 245#define DESC_RATE_MCS14 0x1a 246#define DESC_RATE_MCS15 0x1b 247#define DESC_RATE_MCS15_SG 0x1c 248#define DESC_RATE_MCS32 0x20 249 250#define TXDESC_OFFSET_SZ 0 251#define TXDESC_OFFSET_SHT 16 252#if 0 253#define TXDESC_BMC BIT(24) 254#define TXDESC_LSG BIT(26) 255#define TXDESC_FSG BIT(27) 256#define TXDESC_OWN BIT(31) 257#else 258#define TXDESC_BROADMULTICAST BIT(0) 259#define TXDESC_LAST_SEGMENT BIT(2) 260#define TXDESC_FIRST_SEGMENT BIT(3) 261#define TXDESC_OWN BIT(7) 262#endif 263 264/* Word 1 */ 265#define TXDESC_PKT_OFFSET_SZ 0 266#define TXDESC_AGG_ENABLE BIT(5) 267#define TXDESC_BK BIT(6) 268#define TXDESC_QUEUE_SHIFT 8 269#define TXDESC_QUEUE_MASK 0x1f00 270#define TXDESC_QUEUE_BK 0x2 271#define TXDESC_QUEUE_BE 0x0 272#define TXDESC_QUEUE_VI 0x5 273#define TXDESC_QUEUE_VO 0x7 274#define TXDESC_QUEUE_BEACON 0x10 275#define TXDESC_QUEUE_HIGH 0x11 276#define TXDESC_QUEUE_MGNT 0x12 277#define TXDESC_QUEUE_CMD 0x13 278#define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 279 280#define DESC_RATE_ID_SHIFT 16 281#define DESC_RATE_ID_MASK 0xf 282#define TXDESC_NAVUSEHDR BIT(20) 283#define TXDESC_SEC_RC4 0x00400000 284#define TXDESC_SEC_AES 0x00c00000 285#define TXDESC_PKT_OFFSET_SHIFT 26 286#define TXDESC_AGG_EN BIT(29) 287#define TXDESC_HWPC BIT(31) 288 289/* Word 2 */ 290#define TXDESC_ACK_REPORT BIT(19) 291#define TXDESC_AMPDU_DENSITY_SHIFT 20 292 293/* Word 3 */ 294#define TXDESC_SEQ_SHIFT 16 295#define TXDESC_SEQ_MASK 0x0fff0000 296 297/* Word 4 */ 298#define TXDESC_QOS BIT(6) 299#define TXDESC_HW_SEQ_ENABLE BIT(7) 300#define TXDESC_USE_DRIVER_RATE BIT(8) 301#define TXDESC_DISABLE_DATA_FB BIT(10) 302#define TXDESC_CTS_SELF_ENABLE BIT(11) 303#define TXDESC_RTS_CTS_ENABLE BIT(12) 304#define TXDESC_HW_RTS_ENABLE BIT(13) 305#define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 306#define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 307#define TXDESC_SHORT_PREAMBLE BIT(24) 308#define TXDESC_DATA_BW BIT(25) 309#define TXDESC_RTS_DATA_BW BIT(27) 310#define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 311#define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 312 313/* Word 5 */ 314#define TXDESC_RTS_RATE_SHIFT 0 315#define TXDESC_RTS_RATE_MASK 0x3f 316#define TXDESC_SHORT_GI BIT(6) 317#define TXDESC_CCX_TAG BIT(7) 318#define TXDESC_RETRY_LIMIT_ENABLE BIT(17) 319#define TXDESC_RETRY_LIMIT_SHIFT 18 320#define TXDESC_RETRY_LIMIT_MASK 0x00fc0000 321 322/* Word 6 */ 323#define TXDESC_MAX_AGG_SHIFT 11 324 325struct phy_rx_agc_info { 326#ifdef __LITTLE_ENDIAN 327 u8 gain:7, trsw:1; 328#else 329 u8 trsw:1, gain:7; 330#endif 331}; 332 333struct rtl8723au_phy_stats { 334 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 335 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 336 u8 cck_sig_qual_ofdm_pwdb_all; 337 u8 cck_agc_rpt_ofdm_cfosho_a; 338 u8 cck_rpt_b_ofdm_cfosho_b; 339 u8 reserved_1; 340 u8 noise_power_db_msb; 341 u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 342 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 343 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 344 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 345 u8 noise_power_db_lsb; 346 u8 reserved_2[3]; 347 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 348 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 349 s8 sig_evm; 350 u8 reserved_3; 351 352#ifdef __LITTLE_ENDIAN 353 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 354 u8 sgi_en:1; 355 u8 rxsc:2; 356 u8 idle_long:1; 357 u8 r_ant_train_en:1; 358 u8 antenna_select_b:1; 359 u8 antenna_select:1; 360#else /* _BIG_ENDIAN_ */ 361 u8 antenna_select:1; 362 u8 antenna_select_b:1; 363 u8 r_ant_train_en:1; 364 u8 idle_long:1; 365 u8 rxsc:2; 366 u8 sgi_en:1; 367 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 368#endif 369}; 370 371/* 372 * Regs to backup 373 */ 374#define RTL8XXXU_ADDA_REGS 16 375#define RTL8XXXU_MAC_REGS 4 376#define RTL8XXXU_BB_REGS 9 377 378struct rtl8xxxu_firmware_header { 379 __le16 signature; /* 92C0: test chip; 92C, 380 88C0: test chip; 381 88C1: MP A-cut; 382 92C1: MP A-cut */ 383 u8 category; /* AP/NIC and USB/PCI */ 384 u8 function; 385 386 __le16 major_version; /* FW Version */ 387 u8 minor_version; /* FW Subversion, default 0x00 */ 388 u8 reserved1; 389 390 u8 month; /* Release time Month field */ 391 u8 date; /* Release time Date field */ 392 u8 hour; /* Release time Hour field */ 393 u8 minute; /* Release time Minute field */ 394 395 __le16 ramcodesize; /* Size of RAM code */ 396 u16 reserved2; 397 398 __le32 svn_idx; /* SVN entry index */ 399 u32 reserved3; 400 401 u32 reserved4; 402 u32 reserved5; 403 404 u8 data[0]; 405}; 406 407/* 408 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 409 */ 410struct rtl8723au_idx { 411#ifdef __LITTLE_ENDIAN 412 int a:4; 413 int b:4; 414#else 415 int b:4; 416 int a:4; 417#endif 418} __attribute__((packed)); 419 420struct rtl8723au_efuse { 421 __le16 rtl_id; 422 u8 res0[0xe]; 423 u8 cck_tx_power_index_A[3]; /* 0x10 */ 424 u8 cck_tx_power_index_B[3]; 425 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 426 u8 ht40_1s_tx_power_index_B[3]; 427 /* 428 * The following entries are half-bytes split as: 429 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 430 */ 431 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 432 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 433 struct rtl8723au_idx ht40_max_power_offset[3]; 434 struct rtl8723au_idx ht20_max_power_offset[3]; 435 u8 channel_plan; /* 0x28 */ 436 u8 tssi_a; 437 u8 thermal_meter; 438 u8 rf_regulatory; 439 u8 rf_option_2; 440 u8 rf_option_3; 441 u8 rf_option_4; 442 u8 res7; 443 u8 version /* 0x30 */; 444 u8 customer_id_major; 445 u8 customer_id_minor; 446 u8 xtal_k; 447 u8 chipset; /* 0x34 */ 448 u8 res8[0x82]; 449 u8 vid; /* 0xb7 */ 450 u8 res9; 451 u8 pid; /* 0xb9 */ 452 u8 res10[0x0c]; 453 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 454 u8 res11[2]; 455 u8 vendor_name[7]; 456 u8 res12[2]; 457 u8 device_name[0x29]; /* 0xd7 */ 458}; 459 460struct rtl8192cu_efuse { 461 __le16 rtl_id; 462 __le16 hpon; 463 u8 res0[2]; 464 __le16 clk; 465 __le16 testr; 466 __le16 vid; 467 __le16 did; 468 __le16 svid; 469 __le16 smid; /* 0x10 */ 470 u8 res1[4]; 471 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 472 u8 res2[2]; 473 u8 vendor_name[7]; 474 u8 res3[3]; 475 u8 device_name[0x14]; /* 0x28 */ 476 u8 res4[0x1e]; /* 0x3c */ 477 u8 cck_tx_power_index_A[3]; /* 0x5a */ 478 u8 cck_tx_power_index_B[3]; 479 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 480 u8 ht40_1s_tx_power_index_B[3]; 481 /* 482 * The following entries are half-bytes split as: 483 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 484 */ 485 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 486 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 487 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 488 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 489 struct rtl8723au_idx ht20_max_power_offset[3]; 490 u8 channel_plan; /* 0x75 */ 491 u8 tssi_a; 492 u8 tssi_b; 493 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 494 u8 rf_regulatory; 495 u8 rf_option_2; 496 u8 rf_option_3; 497 u8 rf_option_4; 498 u8 res5[1]; /* 0x7d */ 499 u8 version; 500 u8 customer_id; 501}; 502 503struct rtl8xxxu_reg8val { 504 u16 reg; 505 u8 val; 506}; 507 508struct rtl8xxxu_reg32val { 509 u16 reg; 510 u32 val; 511}; 512 513struct rtl8xxxu_rfregval { 514 u8 reg; 515 u32 val; 516}; 517 518enum rtl8xxxu_rfpath { 519 RF_A = 0, 520 RF_B = 1, 521}; 522 523struct rtl8xxxu_rfregs { 524 u16 hssiparm1; 525 u16 hssiparm2; 526 u16 lssiparm; 527 u16 hspiread; 528 u16 lssiread; 529 u16 rf_sw_ctrl; 530}; 531 532#define H2C_MAX_MBOX 4 533#define H2C_EXT BIT(7) 534#define H2C_SET_POWER_MODE 1 535#define H2C_JOIN_BSS_REPORT 2 536#define H2C_JOIN_BSS_DISCONNECT 0 537#define H2C_JOIN_BSS_CONNECT 1 538#define H2C_SET_RSSI 5 539#define H2C_SET_RATE_MASK (6 | H2C_EXT) 540 541struct h2c_cmd { 542 union { 543 struct { 544 u8 cmd; 545 u8 data[5]; 546 } __packed cmd; 547 struct { 548 __le32 data; 549 __le16 ext; 550 } __packed raw; 551 struct { 552 u8 cmd; 553 u8 data; 554 u8 pad[4]; 555 } __packed joinbss; 556 struct { 557 u8 cmd; 558 __le16 mask_hi; 559 u8 arg; 560 __le16 mask_lo; 561 } __packed ramask; 562 }; 563}; 564 565struct rtl8xxxu_fileops; 566 567struct rtl8xxxu_priv { 568 struct ieee80211_hw *hw; 569 struct usb_device *udev; 570 struct rtl8xxxu_fileops *fops; 571 572 spinlock_t tx_urb_lock; 573 struct list_head tx_urb_free_list; 574 int tx_urb_free_count; 575 bool tx_stopped; 576 577 spinlock_t rx_urb_lock; 578 struct list_head rx_urb_pending_list; 579 int rx_urb_pending_count; 580 bool shutdown; 581 struct work_struct rx_urb_wq; 582 583 u8 mac_addr[ETH_ALEN]; 584 char chip_name[8]; 585 u8 cck_tx_power_index_A[3]; /* 0x10 */ 586 u8 cck_tx_power_index_B[3]; 587 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 588 u8 ht40_1s_tx_power_index_B[3]; 589 /* 590 * The following entries are half-bytes split as: 591 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 592 */ 593 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 594 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 595 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 596 struct rtl8723au_idx ht40_max_power_offset[3]; 597 struct rtl8723au_idx ht20_max_power_offset[3]; 598 u32 chip_cut:4; 599 u32 rom_rev:4; 600 u32 has_wifi:1; 601 u32 has_bluetooth:1; 602 u32 enable_bluetooth:1; 603 u32 has_gps:1; 604 u32 hi_pa:1; 605 u32 vendor_umc:1; 606 u32 has_polarity_ctrl:1; 607 u32 has_eeprom:1; 608 u32 boot_eeprom:1; 609 u32 ep_tx_high_queue:1; 610 u32 ep_tx_normal_queue:1; 611 u32 ep_tx_low_queue:1; 612 u32 path_a_hi_power:1; 613 u32 path_a_rf_paths:4; 614 unsigned int pipe_interrupt; 615 unsigned int pipe_in; 616 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 617 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 618 u8 path_a_ig_value; 619 u8 ep_tx_count; 620 u8 rf_paths; 621 u8 rx_paths; 622 u8 tx_paths; 623 u32 rf_mode_ag[2]; 624 u32 rege94; 625 u32 rege9c; 626 u32 regeb4; 627 u32 regebc; 628 int next_mbox; 629 int nr_out_eps; 630 631 struct mutex h2c_mutex; 632 633 struct usb_anchor rx_anchor; 634 struct usb_anchor tx_anchor; 635 struct usb_anchor int_anchor; 636 struct rtl8xxxu_firmware_header *fw_data; 637 size_t fw_size; 638 struct mutex usb_buf_mutex; 639 union { 640 __le32 val32; 641 __le16 val16; 642 u8 val8; 643 } usb_buf; 644 union { 645 u8 raw[EFUSE_MAP_LEN_8723A]; 646 struct rtl8723au_efuse efuse8723; 647 struct rtl8192cu_efuse efuse8192; 648 } efuse_wifi; 649 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 650 u32 mac_backup[RTL8XXXU_MAC_REGS]; 651 u32 bb_backup[RTL8XXXU_BB_REGS]; 652 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 653 u32 rtlchip; 654 u8 pi_enabled:1; 655 u8 iqk_initialized:1; 656 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 657}; 658 659struct rtl8xxxu_rx_urb { 660 struct urb urb; 661 struct ieee80211_hw *hw; 662 struct list_head list; 663}; 664 665struct rtl8xxxu_tx_urb { 666 struct urb urb; 667 struct ieee80211_hw *hw; 668 struct list_head list; 669}; 670 671struct rtl8xxxu_fileops { 672 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 673 int (*load_firmware) (struct rtl8xxxu_priv *priv); 674 int (*power_on) (struct rtl8xxxu_priv *priv); 675 int writeN_block_size; 676}; 677