1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef BRCMFMAC_SDIO_H 18#define BRCMFMAC_SDIO_H 19 20#include <linux/skbuff.h> 21#include <linux/firmware.h> 22#include "firmware.h" 23 24#define SDIO_FUNC_0 0 25#define SDIO_FUNC_1 1 26#define SDIO_FUNC_2 2 27 28#define SDIOD_FBR_SIZE 0x100 29 30/* io_en */ 31#define SDIO_FUNC_ENABLE_1 0x02 32#define SDIO_FUNC_ENABLE_2 0x04 33 34/* io_rdys */ 35#define SDIO_FUNC_READY_1 0x02 36#define SDIO_FUNC_READY_2 0x04 37 38/* intr_status */ 39#define INTR_STATUS_FUNC1 0x2 40#define INTR_STATUS_FUNC2 0x4 41 42/* Maximum number of I/O funcs */ 43#define SDIOD_MAX_IOFUNCS 7 44 45/* mask of register map */ 46#define REG_F0_REG_MASK 0x7FF 47#define REG_F1_MISC_MASK 0x1FFFF 48 49/* as of sdiod rev 0, supports 3 functions */ 50#define SBSDIO_NUM_FUNCTION 3 51 52/* function 0 vendor specific CCCR registers */ 53#define SDIO_CCCR_BRCM_CARDCAP 0xf0 54#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 55#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 56#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 57#define SDIO_CCCR_BRCM_CARDCTRL 0xf1 58#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02 59#define SDIO_CCCR_BRCM_SEPINT 0xf2 60 61#define SDIO_SEPINT_MASK 0x01 62#define SDIO_SEPINT_OE 0x02 63#define SDIO_SEPINT_ACT_HI 0x04 64 65/* function 1 miscellaneous registers */ 66 67/* sprom command and status */ 68#define SBSDIO_SPROM_CS 0x10000 69/* sprom info register */ 70#define SBSDIO_SPROM_INFO 0x10001 71/* sprom indirect access data byte 0 */ 72#define SBSDIO_SPROM_DATA_LOW 0x10002 73/* sprom indirect access data byte 1 */ 74#define SBSDIO_SPROM_DATA_HIGH 0x10003 75/* sprom indirect access addr byte 0 */ 76#define SBSDIO_SPROM_ADDR_LOW 0x10004 77/* gpio select */ 78#define SBSDIO_GPIO_SELECT 0x10005 79/* gpio output */ 80#define SBSDIO_GPIO_OUT 0x10006 81/* gpio enable */ 82#define SBSDIO_GPIO_EN 0x10007 83/* rev < 7, watermark for sdio device */ 84#define SBSDIO_WATERMARK 0x10008 85/* control busy signal generation */ 86#define SBSDIO_DEVICE_CTL 0x10009 87 88/* SB Address Window Low (b15) */ 89#define SBSDIO_FUNC1_SBADDRLOW 0x1000A 90/* SB Address Window Mid (b23:b16) */ 91#define SBSDIO_FUNC1_SBADDRMID 0x1000B 92/* SB Address Window High (b31:b24) */ 93#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C 94/* Frame Control (frame term/abort) */ 95#define SBSDIO_FUNC1_FRAMECTRL 0x1000D 96/* ChipClockCSR (ALP/HT ctl/status) */ 97#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E 98/* SdioPullUp (on cmd, d0-d2) */ 99#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F 100/* Write Frame Byte Count Low */ 101#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 102/* Write Frame Byte Count High */ 103#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A 104/* Read Frame Byte Count Low */ 105#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B 106/* Read Frame Byte Count High */ 107#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C 108/* MesBusyCtl (rev 11) */ 109#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D 110/* Sdio Core Rev 12 */ 111#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 112#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 113#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 114#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 115#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 116#define SBSDIO_FUNC1_SLEEPCSR 0x1001F 117#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 118#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 119#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 120#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 121#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 122 123#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 124#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ 125 126/* function 1 OCP space */ 127 128/* sb offset addr is <= 15 bits, 32k */ 129#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 130#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 131/* with b15, maps to 32-bit SB access */ 132#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 133 134/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ 135 136#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ 137#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ 138#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ 139/* Address bits from SBADDR regs */ 140#define SBSDIO_SBWINDOW_MASK 0xffff8000 141 142#define SDIOH_READ 0 /* Read request */ 143#define SDIOH_WRITE 1 /* Write request */ 144 145#define SDIOH_DATA_FIX 0 /* Fixed addressing */ 146#define SDIOH_DATA_INC 1 /* Incremental addressing */ 147 148/* internal return code */ 149#define SUCCESS 0 150#define ERROR 1 151 152/* Packet alignment for most efficient SDIO (can change based on platform) */ 153#define BRCMF_SDALIGN (1 << 6) 154 155/* watchdog polling interval in ms */ 156#define BRCMF_WD_POLL_MS 10 157 158/** 159 * enum brcmf_sdiod_state - the state of the bus. 160 * 161 * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. 162 * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. 163 * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. 164 */ 165enum brcmf_sdiod_state { 166 BRCMF_SDIOD_DOWN, 167 BRCMF_SDIOD_DATA, 168 BRCMF_SDIOD_NOMEDIUM 169}; 170 171struct brcmf_sdreg { 172 int func; 173 int offset; 174 int value; 175}; 176 177struct brcmf_sdio; 178struct brcmf_sdiod_freezer; 179 180struct brcmf_sdio_dev { 181 struct sdio_func *func[SDIO_MAX_FUNCS]; 182 u8 num_funcs; /* Supported funcs on client */ 183 u32 sbwad; /* Save backplane window address */ 184 struct brcmf_sdio *bus; 185 struct device *dev; 186 struct brcmf_bus *bus_if; 187 struct brcmfmac_sdio_platform_data *pdata; 188 bool oob_irq_requested; 189 bool irq_en; /* irq enable flags */ 190 spinlock_t irq_en_lock; 191 bool irq_wake; /* irq wake enable flags */ 192 bool sg_support; 193 uint max_request_size; 194 ushort max_segment_count; 195 uint max_segment_size; 196 uint txglomsz; 197 struct sg_table sgtable; 198 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN]; 199 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN]; 200 bool wowl_enabled; 201 enum brcmf_sdiod_state state; 202 struct brcmf_sdiod_freezer *freezer; 203}; 204 205/* sdio core registers */ 206struct sdpcmd_regs { 207 u32 corecontrol; /* 0x00, rev8 */ 208 u32 corestatus; /* rev8 */ 209 u32 PAD[1]; 210 u32 biststatus; /* rev8 */ 211 212 /* PCMCIA access */ 213 u16 pcmciamesportaladdr; /* 0x010, rev8 */ 214 u16 PAD[1]; 215 u16 pcmciamesportalmask; /* rev8 */ 216 u16 PAD[1]; 217 u16 pcmciawrframebc; /* rev8 */ 218 u16 PAD[1]; 219 u16 pcmciaunderflowtimer; /* rev8 */ 220 u16 PAD[1]; 221 222 /* interrupt */ 223 u32 intstatus; /* 0x020, rev8 */ 224 u32 hostintmask; /* rev8 */ 225 u32 intmask; /* rev8 */ 226 u32 sbintstatus; /* rev8 */ 227 u32 sbintmask; /* rev8 */ 228 u32 funcintmask; /* rev4 */ 229 u32 PAD[2]; 230 u32 tosbmailbox; /* 0x040, rev8 */ 231 u32 tohostmailbox; /* rev8 */ 232 u32 tosbmailboxdata; /* rev8 */ 233 u32 tohostmailboxdata; /* rev8 */ 234 235 /* synchronized access to registers in SDIO clock domain */ 236 u32 sdioaccess; /* 0x050, rev8 */ 237 u32 PAD[3]; 238 239 /* PCMCIA frame control */ 240 u8 pcmciaframectrl; /* 0x060, rev8 */ 241 u8 PAD[3]; 242 u8 pcmciawatermark; /* rev8 */ 243 u8 PAD[155]; 244 245 /* interrupt batching control */ 246 u32 intrcvlazy; /* 0x100, rev8 */ 247 u32 PAD[3]; 248 249 /* counters */ 250 u32 cmd52rd; /* 0x110, rev8 */ 251 u32 cmd52wr; /* rev8 */ 252 u32 cmd53rd; /* rev8 */ 253 u32 cmd53wr; /* rev8 */ 254 u32 abort; /* rev8 */ 255 u32 datacrcerror; /* rev8 */ 256 u32 rdoutofsync; /* rev8 */ 257 u32 wroutofsync; /* rev8 */ 258 u32 writebusy; /* rev8 */ 259 u32 readwait; /* rev8 */ 260 u32 readterm; /* rev8 */ 261 u32 writeterm; /* rev8 */ 262 u32 PAD[40]; 263 u32 clockctlstatus; /* rev8 */ 264 u32 PAD[7]; 265 266 u32 PAD[128]; /* DMA engines */ 267 268 /* SDIO/PCMCIA CIS region */ 269 char cis[512]; /* 0x400-0x5ff, rev6 */ 270 271 /* PCMCIA function control registers */ 272 char pcmciafcr[256]; /* 0x600-6ff, rev6 */ 273 u16 PAD[55]; 274 275 /* PCMCIA backplane access */ 276 u16 backplanecsr; /* 0x76E, rev6 */ 277 u16 backplaneaddr0; /* rev6 */ 278 u16 backplaneaddr1; /* rev6 */ 279 u16 backplaneaddr2; /* rev6 */ 280 u16 backplaneaddr3; /* rev6 */ 281 u16 backplanedata0; /* rev6 */ 282 u16 backplanedata1; /* rev6 */ 283 u16 backplanedata2; /* rev6 */ 284 u16 backplanedata3; /* rev6 */ 285 u16 PAD[31]; 286 287 /* sprom "size" & "blank" info */ 288 u16 spromstatus; /* 0x7BE, rev2 */ 289 u32 PAD[464]; 290 291 u16 PAD[0x80]; 292}; 293 294/* Register/deregister interrupt handler. */ 295int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev); 296int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev); 297 298/* sdio device register access interface */ 299u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); 300u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); 301void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data, 302 int *ret); 303void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data, 304 int *ret); 305 306/* Buffer transfer to/from device (client) core via cmd53. 307 * fn: function number 308 * flags: backplane width, address increment, sync/async 309 * buf: pointer to memory data buffer 310 * nbytes: number of bytes to transfer to/from buf 311 * pkt: pointer to packet associated with buf (if any) 312 * complete: callback function for command completion (async only) 313 * handle: handle for completion callback (first arg in callback) 314 * Returns 0 or error code. 315 * NOTE: Async operation is not currently supported. 316 */ 317int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev, 318 struct sk_buff_head *pktq); 319int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 320 321int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt); 322int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 323int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev, 324 struct sk_buff_head *pktq, uint totlen); 325 326/* Flags bits */ 327 328/* Four-byte target (backplane) width (vs. two-byte) */ 329#define SDIO_REQ_4BYTE 0x1 330/* Fixed address (FIFO) (vs. incrementing address) */ 331#define SDIO_REQ_FIXED 0x2 332 333/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). 334 * rw: read or write (0/1) 335 * addr: direct SDIO address 336 * buf: pointer to memory data buffer 337 * nbytes: number of bytes to transfer to/from buf 338 * Returns 0 or error code. 339 */ 340int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address, 341 u8 *data, uint size); 342 343/* Issue an abort to the specified function */ 344int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn); 345void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev, 346 enum brcmf_sdiod_state state); 347#ifdef CONFIG_PM_SLEEP 348bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev); 349void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev); 350void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev); 351void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev); 352#else 353static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev) 354{ 355 return false; 356} 357static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev) 358{ 359} 360static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev) 361{ 362} 363static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev) 364{ 365} 366#endif /* CONFIG_PM_SLEEP */ 367 368struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev); 369void brcmf_sdio_remove(struct brcmf_sdio *bus); 370void brcmf_sdio_isr(struct brcmf_sdio *bus); 371 372void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick); 373void brcmf_sdio_wowl_config(struct device *dev, bool enabled); 374int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep); 375void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus); 376 377#endif /* BRCMFMAC_SDIO_H */ 378