1/*
2
3  Broadcom B43legacy wireless driver
4
5  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6		     Stefano Brivio <stefano.brivio@polimi.it>
7		     Michael Buesch <m@bues.ch>
8		     Danny van Dyk <kugelfang@gentoo.org>
9     Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11
12  Some parts of the code in this file are derived from the ipw2200
13  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  This program is free software; you can redistribute it and/or modify
16  it under the terms of the GNU General Public License as published by
17  the Free Software Foundation; either version 2 of the License, or
18  (at your option) any later version.
19
20  This program is distributed in the hope that it will be useful,
21  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  GNU General Public License for more details.
24
25  You should have received a copy of the GNU General Public License
26  along with this program; see the file COPYING.  If not, write to
27  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  Boston, MA 02110-1301, USA.
29
30*/
31
32#include <linux/delay.h>
33#include <linux/pci.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36#include <linux/types.h>
37
38#include "b43legacy.h"
39#include "phy.h"
40#include "main.h"
41#include "radio.h"
42#include "ilt.h"
43
44
45static const s8 b43legacy_tssi2dbm_b_table[] = {
46	0x4D, 0x4C, 0x4B, 0x4A,
47	0x4A, 0x49, 0x48, 0x47,
48	0x47, 0x46, 0x45, 0x45,
49	0x44, 0x43, 0x42, 0x42,
50	0x41, 0x40, 0x3F, 0x3E,
51	0x3D, 0x3C, 0x3B, 0x3A,
52	0x39, 0x38, 0x37, 0x36,
53	0x35, 0x34, 0x32, 0x31,
54	0x30, 0x2F, 0x2D, 0x2C,
55	0x2B, 0x29, 0x28, 0x26,
56	0x25, 0x23, 0x21, 0x1F,
57	0x1D, 0x1A, 0x17, 0x14,
58	0x10, 0x0C, 0x06, 0x00,
59	  -7,   -7,   -7,   -7,
60	  -7,   -7,   -7,   -7,
61	  -7,   -7,   -7,   -7,
62};
63
64static const s8 b43legacy_tssi2dbm_g_table[] = {
65	 77,  77,  77,  76,
66	 76,  76,  75,  75,
67	 74,  74,  73,  73,
68	 73,  72,  72,  71,
69	 71,  70,  70,  69,
70	 68,  68,  67,  67,
71	 66,  65,  65,  64,
72	 63,  63,  62,  61,
73	 60,  59,  58,  57,
74	 56,  55,  54,  53,
75	 52,  50,  49,  47,
76	 45,  43,  40,  37,
77	 33,  28,  22,  14,
78	  5,  -7, -20, -20,
79	-20, -20, -20, -20,
80	-20, -20, -20, -20,
81};
82
83static void b43legacy_phy_initg(struct b43legacy_wldev *dev);
84
85
86static inline
87void b43legacy_voluntary_preempt(void)
88{
89	B43legacy_BUG_ON(!(!in_atomic() && !in_irq() &&
90			  !in_interrupt() && !irqs_disabled()));
91#ifndef CONFIG_PREEMPT
92	cond_resched();
93#endif /* CONFIG_PREEMPT */
94}
95
96/* Lock the PHY registers against concurrent access from the microcode.
97 * This lock is nonrecursive. */
98void b43legacy_phy_lock(struct b43legacy_wldev *dev)
99{
100#if B43legacy_DEBUG
101	B43legacy_WARN_ON(dev->phy.phy_locked);
102	dev->phy.phy_locked = 1;
103#endif
104
105	if (dev->dev->id.revision < 3) {
106		b43legacy_mac_suspend(dev);
107	} else {
108		if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP))
109			b43legacy_power_saving_ctl_bits(dev, -1, 1);
110	}
111}
112
113void b43legacy_phy_unlock(struct b43legacy_wldev *dev)
114{
115#if B43legacy_DEBUG
116	B43legacy_WARN_ON(!dev->phy.phy_locked);
117	dev->phy.phy_locked = 0;
118#endif
119
120	if (dev->dev->id.revision < 3) {
121		b43legacy_mac_enable(dev);
122	} else {
123		if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP))
124			b43legacy_power_saving_ctl_bits(dev, -1, -1);
125	}
126}
127
128u16 b43legacy_phy_read(struct b43legacy_wldev *dev, u16 offset)
129{
130	b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset);
131	return b43legacy_read16(dev, B43legacy_MMIO_PHY_DATA);
132}
133
134void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val)
135{
136	b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset);
137	mmiowb();
138	b43legacy_write16(dev, B43legacy_MMIO_PHY_DATA, val);
139}
140
141void b43legacy_phy_calibrate(struct b43legacy_wldev *dev)
142{
143	struct b43legacy_phy *phy = &dev->phy;
144
145	b43legacy_read32(dev, B43legacy_MMIO_MACCTL); /* Dummy read. */
146	if (phy->calibrated)
147		return;
148	if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) {
149		b43legacy_wireless_core_reset(dev, 0);
150		b43legacy_phy_initg(dev);
151		b43legacy_wireless_core_reset(dev, B43legacy_TMSLOW_GMODE);
152	}
153	phy->calibrated = 1;
154}
155
156/* initialize B PHY power control
157 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
158 */
159static void b43legacy_phy_init_pctl(struct b43legacy_wldev *dev)
160{
161	struct b43legacy_phy *phy = &dev->phy;
162	u16 saved_batt = 0;
163	u16 saved_ratt = 0;
164	u16 saved_txctl1 = 0;
165	int must_reset_txpower = 0;
166
167	B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B ||
168			  phy->type == B43legacy_PHYTYPE_G));
169	if (is_bcm_board_vendor(dev) &&
170	    (dev->dev->bus->boardinfo.type == 0x0416))
171		return;
172
173	b43legacy_phy_write(dev, 0x0028, 0x8018);
174	b43legacy_write16(dev, 0x03E6, b43legacy_read16(dev, 0x03E6) & 0xFFDF);
175
176	if (phy->type == B43legacy_PHYTYPE_G) {
177		if (!phy->gmode)
178			return;
179		b43legacy_phy_write(dev, 0x047A, 0xC111);
180	}
181	if (phy->savedpctlreg != 0xFFFF)
182		return;
183#ifdef CONFIG_B43LEGACY_DEBUG
184	if (phy->manual_txpower_control)
185		return;
186#endif
187
188	if (phy->type == B43legacy_PHYTYPE_B &&
189	    phy->rev >= 2 &&
190	    phy->radio_ver == 0x2050)
191		b43legacy_radio_write16(dev, 0x0076,
192					b43legacy_radio_read16(dev, 0x0076)
193					| 0x0084);
194	else {
195		saved_batt = phy->bbatt;
196		saved_ratt = phy->rfatt;
197		saved_txctl1 = phy->txctl1;
198		if ((phy->radio_rev >= 6) && (phy->radio_rev <= 8)
199		    && /*FIXME: incomplete specs for 5 < revision < 9 */ 0)
200			b43legacy_radio_set_txpower_bg(dev, 0xB, 0x1F, 0);
201		else
202			b43legacy_radio_set_txpower_bg(dev, 0xB, 9, 0);
203		must_reset_txpower = 1;
204	}
205	b43legacy_dummy_transmission(dev);
206
207	phy->savedpctlreg = b43legacy_phy_read(dev, B43legacy_PHY_G_PCTL);
208
209	if (must_reset_txpower)
210		b43legacy_radio_set_txpower_bg(dev, saved_batt, saved_ratt,
211					       saved_txctl1);
212	else
213		b43legacy_radio_write16(dev, 0x0076, b43legacy_radio_read16(dev,
214					0x0076) & 0xFF7B);
215	b43legacy_radio_clear_tssi(dev);
216}
217
218static void b43legacy_phy_agcsetup(struct b43legacy_wldev *dev)
219{
220	struct b43legacy_phy *phy = &dev->phy;
221	u16 offset = 0x0000;
222
223	if (phy->rev == 1)
224		offset = 0x4C00;
225
226	b43legacy_ilt_write(dev, offset, 0x00FE);
227	b43legacy_ilt_write(dev, offset + 1, 0x000D);
228	b43legacy_ilt_write(dev, offset + 2, 0x0013);
229	b43legacy_ilt_write(dev, offset + 3, 0x0019);
230
231	if (phy->rev == 1) {
232		b43legacy_ilt_write(dev, 0x1800, 0x2710);
233		b43legacy_ilt_write(dev, 0x1801, 0x9B83);
234		b43legacy_ilt_write(dev, 0x1802, 0x9B83);
235		b43legacy_ilt_write(dev, 0x1803, 0x0F8D);
236		b43legacy_phy_write(dev, 0x0455, 0x0004);
237	}
238
239	b43legacy_phy_write(dev, 0x04A5, (b43legacy_phy_read(dev, 0x04A5)
240					  & 0x00FF) | 0x5700);
241	b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A)
242					  & 0xFF80) | 0x000F);
243	b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A)
244					  & 0xC07F) | 0x2B80);
245	b43legacy_phy_write(dev, 0x048C, (b43legacy_phy_read(dev, 0x048C)
246					  & 0xF0FF) | 0x0300);
247
248	b43legacy_radio_write16(dev, 0x007A,
249				b43legacy_radio_read16(dev, 0x007A)
250				| 0x0008);
251
252	b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0)
253			    & 0xFFF0) | 0x0008);
254	b43legacy_phy_write(dev, 0x04A1, (b43legacy_phy_read(dev, 0x04A1)
255			    & 0xF0FF) | 0x0600);
256	b43legacy_phy_write(dev, 0x04A2, (b43legacy_phy_read(dev, 0x04A2)
257			    & 0xF0FF) | 0x0700);
258	b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0)
259			    & 0xF0FF) | 0x0100);
260
261	if (phy->rev == 1)
262		b43legacy_phy_write(dev, 0x04A2,
263				    (b43legacy_phy_read(dev, 0x04A2)
264				    & 0xFFF0) | 0x0007);
265
266	b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488)
267			    & 0xFF00) | 0x001C);
268	b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488)
269			    & 0xC0FF) | 0x0200);
270	b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496)
271			    & 0xFF00) | 0x001C);
272	b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489)
273			    & 0xFF00) | 0x0020);
274	b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489)
275			    & 0xC0FF) | 0x0200);
276	b43legacy_phy_write(dev, 0x0482, (b43legacy_phy_read(dev, 0x0482)
277			    & 0xFF00) | 0x002E);
278	b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496)
279			    & 0x00FF) | 0x1A00);
280	b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481)
281			    & 0xFF00) | 0x0028);
282	b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481)
283			    & 0x00FF) | 0x2C00);
284
285	if (phy->rev == 1) {
286		b43legacy_phy_write(dev, 0x0430, 0x092B);
287		b43legacy_phy_write(dev, 0x041B,
288				    (b43legacy_phy_read(dev, 0x041B)
289				    & 0xFFE1) | 0x0002);
290	} else {
291		b43legacy_phy_write(dev, 0x041B,
292				    b43legacy_phy_read(dev, 0x041B) & 0xFFE1);
293		b43legacy_phy_write(dev, 0x041F, 0x287A);
294		b43legacy_phy_write(dev, 0x0420,
295				    (b43legacy_phy_read(dev, 0x0420)
296				    & 0xFFF0) | 0x0004);
297	}
298
299	if (phy->rev > 2) {
300		b43legacy_phy_write(dev, 0x0422, 0x287A);
301		b43legacy_phy_write(dev, 0x0420,
302				    (b43legacy_phy_read(dev, 0x0420)
303				    & 0x0FFF) | 0x3000);
304	}
305
306	b43legacy_phy_write(dev, 0x04A8, (b43legacy_phy_read(dev, 0x04A8)
307			    & 0x8080) | 0x7874);
308	b43legacy_phy_write(dev, 0x048E, 0x1C00);
309
310	if (phy->rev == 1) {
311		b43legacy_phy_write(dev, 0x04AB,
312				    (b43legacy_phy_read(dev, 0x04AB)
313				    & 0xF0FF) | 0x0600);
314		b43legacy_phy_write(dev, 0x048B, 0x005E);
315		b43legacy_phy_write(dev, 0x048C,
316				    (b43legacy_phy_read(dev, 0x048C) & 0xFF00)
317				    | 0x001E);
318		b43legacy_phy_write(dev, 0x048D, 0x0002);
319	}
320
321	b43legacy_ilt_write(dev, offset + 0x0800, 0);
322	b43legacy_ilt_write(dev, offset + 0x0801, 7);
323	b43legacy_ilt_write(dev, offset + 0x0802, 16);
324	b43legacy_ilt_write(dev, offset + 0x0803, 28);
325
326	if (phy->rev >= 6) {
327		b43legacy_phy_write(dev, 0x0426,
328				    (b43legacy_phy_read(dev, 0x0426) & 0xFFFC));
329		b43legacy_phy_write(dev, 0x0426,
330				    (b43legacy_phy_read(dev, 0x0426) & 0xEFFF));
331	}
332}
333
334static void b43legacy_phy_setupg(struct b43legacy_wldev *dev)
335{
336	struct b43legacy_phy *phy = &dev->phy;
337	u16 i;
338
339	B43legacy_BUG_ON(phy->type != B43legacy_PHYTYPE_G);
340	if (phy->rev == 1) {
341		b43legacy_phy_write(dev, 0x0406, 0x4F19);
342		b43legacy_phy_write(dev, B43legacy_PHY_G_CRS,
343				    (b43legacy_phy_read(dev,
344				    B43legacy_PHY_G_CRS) & 0xFC3F) | 0x0340);
345		b43legacy_phy_write(dev, 0x042C, 0x005A);
346		b43legacy_phy_write(dev, 0x0427, 0x001A);
347
348		for (i = 0; i < B43legacy_ILT_FINEFREQG_SIZE; i++)
349			b43legacy_ilt_write(dev, 0x5800 + i,
350					    b43legacy_ilt_finefreqg[i]);
351		for (i = 0; i < B43legacy_ILT_NOISEG1_SIZE; i++)
352			b43legacy_ilt_write(dev, 0x1800 + i,
353					    b43legacy_ilt_noiseg1[i]);
354		for (i = 0; i < B43legacy_ILT_ROTOR_SIZE; i++)
355			b43legacy_ilt_write32(dev, 0x2000 + i,
356					      b43legacy_ilt_rotor[i]);
357	} else {
358		/* nrssi values are signed 6-bit values. Why 0x7654 here? */
359		b43legacy_nrssi_hw_write(dev, 0xBA98, (s16)0x7654);
360
361		if (phy->rev == 2) {
362			b43legacy_phy_write(dev, 0x04C0, 0x1861);
363			b43legacy_phy_write(dev, 0x04C1, 0x0271);
364		} else if (phy->rev > 2) {
365			b43legacy_phy_write(dev, 0x04C0, 0x0098);
366			b43legacy_phy_write(dev, 0x04C1, 0x0070);
367			b43legacy_phy_write(dev, 0x04C9, 0x0080);
368		}
369		b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev,
370				    0x042B) | 0x800);
371
372		for (i = 0; i < 64; i++)
373			b43legacy_ilt_write(dev, 0x4000 + i, i);
374		for (i = 0; i < B43legacy_ILT_NOISEG2_SIZE; i++)
375			b43legacy_ilt_write(dev, 0x1800 + i,
376					    b43legacy_ilt_noiseg2[i]);
377	}
378
379	if (phy->rev <= 2)
380		for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
381			b43legacy_ilt_write(dev, 0x1400 + i,
382					    b43legacy_ilt_noisescaleg1[i]);
383	else if ((phy->rev >= 7) && (b43legacy_phy_read(dev, 0x0449) & 0x0200))
384		for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
385			b43legacy_ilt_write(dev, 0x1400 + i,
386					    b43legacy_ilt_noisescaleg3[i]);
387	else
388		for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
389			b43legacy_ilt_write(dev, 0x1400 + i,
390					    b43legacy_ilt_noisescaleg2[i]);
391
392	if (phy->rev == 2)
393		for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++)
394			b43legacy_ilt_write(dev, 0x5000 + i,
395					    b43legacy_ilt_sigmasqr1[i]);
396	else if ((phy->rev > 2) && (phy->rev <= 8))
397		for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++)
398			b43legacy_ilt_write(dev, 0x5000 + i,
399					    b43legacy_ilt_sigmasqr2[i]);
400
401	if (phy->rev == 1) {
402		for (i = 0; i < B43legacy_ILT_RETARD_SIZE; i++)
403			b43legacy_ilt_write32(dev, 0x2400 + i,
404					      b43legacy_ilt_retard[i]);
405		for (i = 4; i < 20; i++)
406			b43legacy_ilt_write(dev, 0x5400 + i, 0x0020);
407		b43legacy_phy_agcsetup(dev);
408
409		if (is_bcm_board_vendor(dev) &&
410		    (dev->dev->bus->boardinfo.type == 0x0416) &&
411		    (dev->dev->bus->sprom.board_rev == 0x0017))
412			return;
413
414		b43legacy_ilt_write(dev, 0x5001, 0x0002);
415		b43legacy_ilt_write(dev, 0x5002, 0x0001);
416	} else {
417		for (i = 0; i <= 0x20; i++)
418			b43legacy_ilt_write(dev, 0x1000 + i, 0x0820);
419		b43legacy_phy_agcsetup(dev);
420		b43legacy_phy_read(dev, 0x0400); /* dummy read */
421		b43legacy_phy_write(dev, 0x0403, 0x1000);
422		b43legacy_ilt_write(dev, 0x3C02, 0x000F);
423		b43legacy_ilt_write(dev, 0x3C03, 0x0014);
424
425		if (is_bcm_board_vendor(dev) &&
426		    (dev->dev->bus->boardinfo.type == 0x0416) &&
427		    (dev->dev->bus->sprom.board_rev == 0x0017))
428			return;
429
430		b43legacy_ilt_write(dev, 0x0401, 0x0002);
431		b43legacy_ilt_write(dev, 0x0402, 0x0001);
432	}
433}
434
435/* Initialize the APHY portion of a GPHY. */
436static void b43legacy_phy_inita(struct b43legacy_wldev *dev)
437{
438
439	might_sleep();
440
441	b43legacy_phy_setupg(dev);
442	if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL)
443		b43legacy_phy_write(dev, 0x046E, 0x03CF);
444}
445
446static void b43legacy_phy_initb2(struct b43legacy_wldev *dev)
447{
448	struct b43legacy_phy *phy = &dev->phy;
449	u16 offset;
450	int val;
451
452	b43legacy_write16(dev, 0x03EC, 0x3F22);
453	b43legacy_phy_write(dev, 0x0020, 0x301C);
454	b43legacy_phy_write(dev, 0x0026, 0x0000);
455	b43legacy_phy_write(dev, 0x0030, 0x00C6);
456	b43legacy_phy_write(dev, 0x0088, 0x3E00);
457	val = 0x3C3D;
458	for (offset = 0x0089; offset < 0x00A7; offset++) {
459		b43legacy_phy_write(dev, offset, val);
460		val -= 0x0202;
461	}
462	b43legacy_phy_write(dev, 0x03E4, 0x3000);
463	b43legacy_radio_selectchannel(dev, phy->channel, 0);
464	if (phy->radio_ver != 0x2050) {
465		b43legacy_radio_write16(dev, 0x0075, 0x0080);
466		b43legacy_radio_write16(dev, 0x0079, 0x0081);
467	}
468	b43legacy_radio_write16(dev, 0x0050, 0x0020);
469	b43legacy_radio_write16(dev, 0x0050, 0x0023);
470	if (phy->radio_ver == 0x2050) {
471		b43legacy_radio_write16(dev, 0x0050, 0x0020);
472		b43legacy_radio_write16(dev, 0x005A, 0x0070);
473		b43legacy_radio_write16(dev, 0x005B, 0x007B);
474		b43legacy_radio_write16(dev, 0x005C, 0x00B0);
475		b43legacy_radio_write16(dev, 0x007A, 0x000F);
476		b43legacy_phy_write(dev, 0x0038, 0x0677);
477		b43legacy_radio_init2050(dev);
478	}
479	b43legacy_phy_write(dev, 0x0014, 0x0080);
480	b43legacy_phy_write(dev, 0x0032, 0x00CA);
481	b43legacy_phy_write(dev, 0x0032, 0x00CC);
482	b43legacy_phy_write(dev, 0x0035, 0x07C2);
483	b43legacy_phy_lo_b_measure(dev);
484	b43legacy_phy_write(dev, 0x0026, 0xCC00);
485	if (phy->radio_ver != 0x2050)
486		b43legacy_phy_write(dev, 0x0026, 0xCE00);
487	b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1000);
488	b43legacy_phy_write(dev, 0x002A, 0x88A3);
489	if (phy->radio_ver != 0x2050)
490		b43legacy_phy_write(dev, 0x002A, 0x88C2);
491	b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
492	b43legacy_phy_init_pctl(dev);
493}
494
495static void b43legacy_phy_initb4(struct b43legacy_wldev *dev)
496{
497	struct b43legacy_phy *phy = &dev->phy;
498	u16 offset;
499	u16 val;
500
501	b43legacy_write16(dev, 0x03EC, 0x3F22);
502	b43legacy_phy_write(dev, 0x0020, 0x301C);
503	b43legacy_phy_write(dev, 0x0026, 0x0000);
504	b43legacy_phy_write(dev, 0x0030, 0x00C6);
505	b43legacy_phy_write(dev, 0x0088, 0x3E00);
506	val = 0x3C3D;
507	for (offset = 0x0089; offset < 0x00A7; offset++) {
508		b43legacy_phy_write(dev, offset, val);
509		val -= 0x0202;
510	}
511	b43legacy_phy_write(dev, 0x03E4, 0x3000);
512	b43legacy_radio_selectchannel(dev, phy->channel, 0);
513	if (phy->radio_ver != 0x2050) {
514		b43legacy_radio_write16(dev, 0x0075, 0x0080);
515		b43legacy_radio_write16(dev, 0x0079, 0x0081);
516	}
517	b43legacy_radio_write16(dev, 0x0050, 0x0020);
518	b43legacy_radio_write16(dev, 0x0050, 0x0023);
519	if (phy->radio_ver == 0x2050) {
520		b43legacy_radio_write16(dev, 0x0050, 0x0020);
521		b43legacy_radio_write16(dev, 0x005A, 0x0070);
522		b43legacy_radio_write16(dev, 0x005B, 0x007B);
523		b43legacy_radio_write16(dev, 0x005C, 0x00B0);
524		b43legacy_radio_write16(dev, 0x007A, 0x000F);
525		b43legacy_phy_write(dev, 0x0038, 0x0677);
526		b43legacy_radio_init2050(dev);
527	}
528	b43legacy_phy_write(dev, 0x0014, 0x0080);
529	b43legacy_phy_write(dev, 0x0032, 0x00CA);
530	if (phy->radio_ver == 0x2050)
531		b43legacy_phy_write(dev, 0x0032, 0x00E0);
532	b43legacy_phy_write(dev, 0x0035, 0x07C2);
533
534	b43legacy_phy_lo_b_measure(dev);
535
536	b43legacy_phy_write(dev, 0x0026, 0xCC00);
537	if (phy->radio_ver == 0x2050)
538		b43legacy_phy_write(dev, 0x0026, 0xCE00);
539	b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1100);
540	b43legacy_phy_write(dev, 0x002A, 0x88A3);
541	if (phy->radio_ver == 0x2050)
542		b43legacy_phy_write(dev, 0x002A, 0x88C2);
543	b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
544	if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
545		b43legacy_calc_nrssi_slope(dev);
546		b43legacy_calc_nrssi_threshold(dev);
547	}
548	b43legacy_phy_init_pctl(dev);
549}
550
551static void b43legacy_phy_initb5(struct b43legacy_wldev *dev)
552{
553	struct b43legacy_phy *phy = &dev->phy;
554	u16 offset;
555	u16 value;
556	u8 old_channel;
557
558	if (phy->analog == 1)
559		b43legacy_radio_write16(dev, 0x007A,
560					b43legacy_radio_read16(dev, 0x007A)
561					| 0x0050);
562	if (!is_bcm_board_vendor(dev) &&
563	    (dev->dev->bus->boardinfo.type != 0x0416)) {
564		value = 0x2120;
565		for (offset = 0x00A8 ; offset < 0x00C7; offset++) {
566			b43legacy_phy_write(dev, offset, value);
567			value += 0x0202;
568		}
569	}
570	b43legacy_phy_write(dev, 0x0035,
571			    (b43legacy_phy_read(dev, 0x0035) & 0xF0FF)
572			    | 0x0700);
573	if (phy->radio_ver == 0x2050)
574		b43legacy_phy_write(dev, 0x0038, 0x0667);
575
576	if (phy->gmode) {
577		if (phy->radio_ver == 0x2050) {
578			b43legacy_radio_write16(dev, 0x007A,
579					b43legacy_radio_read16(dev, 0x007A)
580					| 0x0020);
581			b43legacy_radio_write16(dev, 0x0051,
582					b43legacy_radio_read16(dev, 0x0051)
583					| 0x0004);
584		}
585		b43legacy_write16(dev, B43legacy_MMIO_PHY_RADIO, 0x0000);
586
587		b43legacy_phy_write(dev, 0x0802, b43legacy_phy_read(dev, 0x0802)
588				    | 0x0100);
589		b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev, 0x042B)
590				    | 0x2000);
591
592		b43legacy_phy_write(dev, 0x001C, 0x186A);
593
594		b43legacy_phy_write(dev, 0x0013, (b43legacy_phy_read(dev,
595				    0x0013) & 0x00FF) | 0x1900);
596		b43legacy_phy_write(dev, 0x0035, (b43legacy_phy_read(dev,
597				    0x0035) & 0xFFC0) | 0x0064);
598		b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev,
599				    0x005D) & 0xFF80) | 0x000A);
600		b43legacy_phy_write(dev, 0x5B, 0x0000);
601		b43legacy_phy_write(dev, 0x5C, 0x0000);
602	}
603
604	if (dev->bad_frames_preempt)
605		b43legacy_phy_write(dev, B43legacy_PHY_RADIO_BITFIELD,
606				    b43legacy_phy_read(dev,
607				    B43legacy_PHY_RADIO_BITFIELD) | (1 << 12));
608
609	if (phy->analog == 1) {
610		b43legacy_phy_write(dev, 0x0026, 0xCE00);
611		b43legacy_phy_write(dev, 0x0021, 0x3763);
612		b43legacy_phy_write(dev, 0x0022, 0x1BC3);
613		b43legacy_phy_write(dev, 0x0023, 0x06F9);
614		b43legacy_phy_write(dev, 0x0024, 0x037E);
615	} else
616		b43legacy_phy_write(dev, 0x0026, 0xCC00);
617	b43legacy_phy_write(dev, 0x0030, 0x00C6);
618	b43legacy_write16(dev, 0x03EC, 0x3F22);
619
620	if (phy->analog == 1)
621		b43legacy_phy_write(dev, 0x0020, 0x3E1C);
622	else
623		b43legacy_phy_write(dev, 0x0020, 0x301C);
624
625	if (phy->analog == 0)
626		b43legacy_write16(dev, 0x03E4, 0x3000);
627
628	old_channel = (phy->channel == 0xFF) ? 1 : phy->channel;
629	/* Force to channel 7, even if not supported. */
630	b43legacy_radio_selectchannel(dev, 7, 0);
631
632	if (phy->radio_ver != 0x2050) {
633		b43legacy_radio_write16(dev, 0x0075, 0x0080);
634		b43legacy_radio_write16(dev, 0x0079, 0x0081);
635	}
636
637	b43legacy_radio_write16(dev, 0x0050, 0x0020);
638	b43legacy_radio_write16(dev, 0x0050, 0x0023);
639
640	if (phy->radio_ver == 0x2050) {
641		b43legacy_radio_write16(dev, 0x0050, 0x0020);
642		b43legacy_radio_write16(dev, 0x005A, 0x0070);
643	}
644
645	b43legacy_radio_write16(dev, 0x005B, 0x007B);
646	b43legacy_radio_write16(dev, 0x005C, 0x00B0);
647
648	b43legacy_radio_write16(dev, 0x007A, b43legacy_radio_read16(dev,
649				0x007A) | 0x0007);
650
651	b43legacy_radio_selectchannel(dev, old_channel, 0);
652
653	b43legacy_phy_write(dev, 0x0014, 0x0080);
654	b43legacy_phy_write(dev, 0x0032, 0x00CA);
655	b43legacy_phy_write(dev, 0x002A, 0x88A3);
656
657	b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
658
659	if (phy->radio_ver == 0x2050)
660		b43legacy_radio_write16(dev, 0x005D, 0x000D);
661
662	b43legacy_write16(dev, 0x03E4, (b43legacy_read16(dev, 0x03E4) &
663			  0xFFC0) | 0x0004);
664}
665
666static void b43legacy_phy_initb6(struct b43legacy_wldev *dev)
667{
668	struct b43legacy_phy *phy = &dev->phy;
669	u16 offset;
670	u16 val;
671	u8 old_channel;
672
673	b43legacy_phy_write(dev, 0x003E, 0x817A);
674	b43legacy_radio_write16(dev, 0x007A,
675				(b43legacy_radio_read16(dev, 0x007A) | 0x0058));
676	if (phy->radio_rev == 4 ||
677	     phy->radio_rev == 5) {
678		b43legacy_radio_write16(dev, 0x0051, 0x0037);
679		b43legacy_radio_write16(dev, 0x0052, 0x0070);
680		b43legacy_radio_write16(dev, 0x0053, 0x00B3);
681		b43legacy_radio_write16(dev, 0x0054, 0x009B);
682		b43legacy_radio_write16(dev, 0x005A, 0x0088);
683		b43legacy_radio_write16(dev, 0x005B, 0x0088);
684		b43legacy_radio_write16(dev, 0x005D, 0x0088);
685		b43legacy_radio_write16(dev, 0x005E, 0x0088);
686		b43legacy_radio_write16(dev, 0x007D, 0x0088);
687		b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
688				      B43legacy_UCODEFLAGS_OFFSET,
689				      (b43legacy_shm_read32(dev,
690				      B43legacy_SHM_SHARED,
691				      B43legacy_UCODEFLAGS_OFFSET)
692				      | 0x00000200));
693	}
694	if (phy->radio_rev == 8) {
695		b43legacy_radio_write16(dev, 0x0051, 0x0000);
696		b43legacy_radio_write16(dev, 0x0052, 0x0040);
697		b43legacy_radio_write16(dev, 0x0053, 0x00B7);
698		b43legacy_radio_write16(dev, 0x0054, 0x0098);
699		b43legacy_radio_write16(dev, 0x005A, 0x0088);
700		b43legacy_radio_write16(dev, 0x005B, 0x006B);
701		b43legacy_radio_write16(dev, 0x005C, 0x000F);
702		if (dev->dev->bus->sprom.boardflags_lo & 0x8000) {
703			b43legacy_radio_write16(dev, 0x005D, 0x00FA);
704			b43legacy_radio_write16(dev, 0x005E, 0x00D8);
705		} else {
706			b43legacy_radio_write16(dev, 0x005D, 0x00F5);
707			b43legacy_radio_write16(dev, 0x005E, 0x00B8);
708		}
709		b43legacy_radio_write16(dev, 0x0073, 0x0003);
710		b43legacy_radio_write16(dev, 0x007D, 0x00A8);
711		b43legacy_radio_write16(dev, 0x007C, 0x0001);
712		b43legacy_radio_write16(dev, 0x007E, 0x0008);
713	}
714	val = 0x1E1F;
715	for (offset = 0x0088; offset < 0x0098; offset++) {
716		b43legacy_phy_write(dev, offset, val);
717		val -= 0x0202;
718	}
719	val = 0x3E3F;
720	for (offset = 0x0098; offset < 0x00A8; offset++) {
721		b43legacy_phy_write(dev, offset, val);
722		val -= 0x0202;
723	}
724	val = 0x2120;
725	for (offset = 0x00A8; offset < 0x00C8; offset++) {
726		b43legacy_phy_write(dev, offset, (val & 0x3F3F));
727		val += 0x0202;
728	}
729	if (phy->type == B43legacy_PHYTYPE_G) {
730		b43legacy_radio_write16(dev, 0x007A,
731					b43legacy_radio_read16(dev, 0x007A) |
732					0x0020);
733		b43legacy_radio_write16(dev, 0x0051,
734					b43legacy_radio_read16(dev, 0x0051) |
735					0x0004);
736		b43legacy_phy_write(dev, 0x0802,
737				    b43legacy_phy_read(dev, 0x0802) | 0x0100);
738		b43legacy_phy_write(dev, 0x042B,
739				    b43legacy_phy_read(dev, 0x042B) | 0x2000);
740		b43legacy_phy_write(dev, 0x5B, 0x0000);
741		b43legacy_phy_write(dev, 0x5C, 0x0000);
742	}
743
744	old_channel = phy->channel;
745	if (old_channel >= 8)
746		b43legacy_radio_selectchannel(dev, 1, 0);
747	else
748		b43legacy_radio_selectchannel(dev, 13, 0);
749
750	b43legacy_radio_write16(dev, 0x0050, 0x0020);
751	b43legacy_radio_write16(dev, 0x0050, 0x0023);
752	udelay(40);
753	if (phy->radio_rev < 6 || phy->radio_rev == 8) {
754		b43legacy_radio_write16(dev, 0x007C,
755					(b43legacy_radio_read16(dev, 0x007C)
756					| 0x0002));
757		b43legacy_radio_write16(dev, 0x0050, 0x0020);
758	}
759	if (phy->radio_rev <= 2) {
760		b43legacy_radio_write16(dev, 0x0050, 0x0020);
761		b43legacy_radio_write16(dev, 0x005A, 0x0070);
762		b43legacy_radio_write16(dev, 0x005B, 0x007B);
763		b43legacy_radio_write16(dev, 0x005C, 0x00B0);
764	}
765	b43legacy_radio_write16(dev, 0x007A,
766				(b43legacy_radio_read16(dev,
767				0x007A) & 0x00F8) | 0x0007);
768
769	b43legacy_radio_selectchannel(dev, old_channel, 0);
770
771	b43legacy_phy_write(dev, 0x0014, 0x0200);
772	if (phy->radio_rev >= 6)
773		b43legacy_phy_write(dev, 0x002A, 0x88C2);
774	else
775		b43legacy_phy_write(dev, 0x002A, 0x8AC0);
776	b43legacy_phy_write(dev, 0x0038, 0x0668);
777	b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
778	if (phy->radio_rev == 4 || phy->radio_rev == 5)
779		b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev,
780				    0x005D) & 0xFF80) | 0x0003);
781	if (phy->radio_rev <= 2)
782		b43legacy_radio_write16(dev, 0x005D, 0x000D);
783
784	if (phy->analog == 4) {
785		b43legacy_write16(dev, 0x03E4, 0x0009);
786		b43legacy_phy_write(dev, 0x61, b43legacy_phy_read(dev, 0x61)
787				    & 0xFFF);
788	} else
789		b43legacy_phy_write(dev, 0x0002, (b43legacy_phy_read(dev,
790				    0x0002) & 0xFFC0) | 0x0004);
791	if (phy->type == B43legacy_PHYTYPE_G)
792		b43legacy_write16(dev, 0x03E6, 0x0);
793	if (phy->type == B43legacy_PHYTYPE_B) {
794		b43legacy_write16(dev, 0x03E6, 0x8140);
795		b43legacy_phy_write(dev, 0x0016, 0x0410);
796		b43legacy_phy_write(dev, 0x0017, 0x0820);
797		b43legacy_phy_write(dev, 0x0062, 0x0007);
798		b43legacy_radio_init2050(dev);
799		b43legacy_phy_lo_g_measure(dev);
800		if (dev->dev->bus->sprom.boardflags_lo &
801		    B43legacy_BFL_RSSI) {
802			b43legacy_calc_nrssi_slope(dev);
803			b43legacy_calc_nrssi_threshold(dev);
804		}
805		b43legacy_phy_init_pctl(dev);
806	}
807}
808
809static void b43legacy_calc_loopback_gain(struct b43legacy_wldev *dev)
810{
811	struct b43legacy_phy *phy = &dev->phy;
812	u16 backup_phy[15] = {0};
813	u16 backup_radio[3];
814	u16 backup_bband;
815	u16 i;
816	u16 loop1_cnt;
817	u16 loop1_done;
818	u16 loop1_omitted;
819	u16 loop2_done;
820
821	backup_phy[0] = b43legacy_phy_read(dev, 0x0429);
822	backup_phy[1] = b43legacy_phy_read(dev, 0x0001);
823	backup_phy[2] = b43legacy_phy_read(dev, 0x0811);
824	backup_phy[3] = b43legacy_phy_read(dev, 0x0812);
825	if (phy->rev != 1) {
826		backup_phy[4] = b43legacy_phy_read(dev, 0x0814);
827		backup_phy[5] = b43legacy_phy_read(dev, 0x0815);
828	}
829	backup_phy[6] = b43legacy_phy_read(dev, 0x005A);
830	backup_phy[7] = b43legacy_phy_read(dev, 0x0059);
831	backup_phy[8] = b43legacy_phy_read(dev, 0x0058);
832	backup_phy[9] = b43legacy_phy_read(dev, 0x000A);
833	backup_phy[10] = b43legacy_phy_read(dev, 0x0003);
834	backup_phy[11] = b43legacy_phy_read(dev, 0x080F);
835	backup_phy[12] = b43legacy_phy_read(dev, 0x0810);
836	backup_phy[13] = b43legacy_phy_read(dev, 0x002B);
837	backup_phy[14] = b43legacy_phy_read(dev, 0x0015);
838	b43legacy_phy_read(dev, 0x002D); /* dummy read */
839	backup_bband = phy->bbatt;
840	backup_radio[0] = b43legacy_radio_read16(dev, 0x0052);
841	backup_radio[1] = b43legacy_radio_read16(dev, 0x0043);
842	backup_radio[2] = b43legacy_radio_read16(dev, 0x007A);
843
844	b43legacy_phy_write(dev, 0x0429,
845			    b43legacy_phy_read(dev, 0x0429) & 0x3FFF);
846	b43legacy_phy_write(dev, 0x0001,
847			    b43legacy_phy_read(dev, 0x0001) & 0x8000);
848	b43legacy_phy_write(dev, 0x0811,
849			    b43legacy_phy_read(dev, 0x0811) | 0x0002);
850	b43legacy_phy_write(dev, 0x0812,
851			    b43legacy_phy_read(dev, 0x0812) & 0xFFFD);
852	b43legacy_phy_write(dev, 0x0811,
853			    b43legacy_phy_read(dev, 0x0811) | 0x0001);
854	b43legacy_phy_write(dev, 0x0812,
855			    b43legacy_phy_read(dev, 0x0812) & 0xFFFE);
856	if (phy->rev != 1) {
857		b43legacy_phy_write(dev, 0x0814,
858				    b43legacy_phy_read(dev, 0x0814) | 0x0001);
859		b43legacy_phy_write(dev, 0x0815,
860				    b43legacy_phy_read(dev, 0x0815) & 0xFFFE);
861		b43legacy_phy_write(dev, 0x0814,
862				    b43legacy_phy_read(dev, 0x0814) | 0x0002);
863		b43legacy_phy_write(dev, 0x0815,
864				    b43legacy_phy_read(dev, 0x0815) & 0xFFFD);
865	}
866	b43legacy_phy_write(dev, 0x0811, b43legacy_phy_read(dev, 0x0811) |
867			    0x000C);
868	b43legacy_phy_write(dev, 0x0812, b43legacy_phy_read(dev, 0x0812) |
869			    0x000C);
870
871	b43legacy_phy_write(dev, 0x0811, (b43legacy_phy_read(dev, 0x0811)
872			    & 0xFFCF) | 0x0030);
873	b43legacy_phy_write(dev, 0x0812, (b43legacy_phy_read(dev, 0x0812)
874			    & 0xFFCF) | 0x0010);
875
876	b43legacy_phy_write(dev, 0x005A, 0x0780);
877	b43legacy_phy_write(dev, 0x0059, 0xC810);
878	b43legacy_phy_write(dev, 0x0058, 0x000D);
879	if (phy->analog == 0)
880		b43legacy_phy_write(dev, 0x0003, 0x0122);
881	else
882		b43legacy_phy_write(dev, 0x000A,
883				    b43legacy_phy_read(dev, 0x000A)
884				    | 0x2000);
885	if (phy->rev != 1) {
886		b43legacy_phy_write(dev, 0x0814,
887				    b43legacy_phy_read(dev, 0x0814) | 0x0004);
888		b43legacy_phy_write(dev, 0x0815,
889				    b43legacy_phy_read(dev, 0x0815) & 0xFFFB);
890	}
891	b43legacy_phy_write(dev, 0x0003,
892			    (b43legacy_phy_read(dev, 0x0003)
893			     & 0xFF9F) | 0x0040);
894	if (phy->radio_ver == 0x2050 && phy->radio_rev == 2) {
895		b43legacy_radio_write16(dev, 0x0052, 0x0000);
896		b43legacy_radio_write16(dev, 0x0043,
897					(b43legacy_radio_read16(dev, 0x0043)
898					 & 0xFFF0) | 0x0009);
899		loop1_cnt = 9;
900	} else if (phy->radio_rev == 8) {
901		b43legacy_radio_write16(dev, 0x0043, 0x000F);
902		loop1_cnt = 15;
903	} else
904		loop1_cnt = 0;
905
906	b43legacy_phy_set_baseband_attenuation(dev, 11);
907
908	if (phy->rev >= 3)
909		b43legacy_phy_write(dev, 0x080F, 0xC020);
910	else
911		b43legacy_phy_write(dev, 0x080F, 0x8020);
912	b43legacy_phy_write(dev, 0x0810, 0x0000);
913
914	b43legacy_phy_write(dev, 0x002B,
915			    (b43legacy_phy_read(dev, 0x002B)
916			     & 0xFFC0) | 0x0001);
917	b43legacy_phy_write(dev, 0x002B,
918			    (b43legacy_phy_read(dev, 0x002B)
919			     & 0xC0FF) | 0x0800);
920	b43legacy_phy_write(dev, 0x0811,
921			    b43legacy_phy_read(dev, 0x0811) | 0x0100);
922	b43legacy_phy_write(dev, 0x0812,
923			    b43legacy_phy_read(dev, 0x0812) & 0xCFFF);
924	if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_EXTLNA) {
925		if (phy->rev >= 7) {
926			b43legacy_phy_write(dev, 0x0811,
927					    b43legacy_phy_read(dev, 0x0811)
928					    | 0x0800);
929			b43legacy_phy_write(dev, 0x0812,
930					    b43legacy_phy_read(dev, 0x0812)
931					    | 0x8000);
932		}
933	}
934	b43legacy_radio_write16(dev, 0x007A,
935				b43legacy_radio_read16(dev, 0x007A)
936				& 0x00F7);
937
938	for (i = 0; i < loop1_cnt; i++) {
939		b43legacy_radio_write16(dev, 0x0043, loop1_cnt);
940		b43legacy_phy_write(dev, 0x0812,
941				    (b43legacy_phy_read(dev, 0x0812)
942				     & 0xF0FF) | (i << 8));
943		b43legacy_phy_write(dev, 0x0015,
944				    (b43legacy_phy_read(dev, 0x0015)
945				     & 0x0FFF) | 0xA000);
946		b43legacy_phy_write(dev, 0x0015,
947				    (b43legacy_phy_read(dev, 0x0015)
948				     & 0x0FFF) | 0xF000);
949		udelay(20);
950		if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC)
951			break;
952	}
953	loop1_done = i;
954	loop1_omitted = loop1_cnt - loop1_done;
955
956	loop2_done = 0;
957	if (loop1_done >= 8) {
958		b43legacy_phy_write(dev, 0x0812,
959				    b43legacy_phy_read(dev, 0x0812)
960				    | 0x0030);
961		for (i = loop1_done - 8; i < 16; i++) {
962			b43legacy_phy_write(dev, 0x0812,
963					    (b43legacy_phy_read(dev, 0x0812)
964					     & 0xF0FF) | (i << 8));
965			b43legacy_phy_write(dev, 0x0015,
966					    (b43legacy_phy_read(dev, 0x0015)
967					     & 0x0FFF) | 0xA000);
968			b43legacy_phy_write(dev, 0x0015,
969					    (b43legacy_phy_read(dev, 0x0015)
970					     & 0x0FFF) | 0xF000);
971			udelay(20);
972			if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC)
973				break;
974		}
975	}
976
977	if (phy->rev != 1) {
978		b43legacy_phy_write(dev, 0x0814, backup_phy[4]);
979		b43legacy_phy_write(dev, 0x0815, backup_phy[5]);
980	}
981	b43legacy_phy_write(dev, 0x005A, backup_phy[6]);
982	b43legacy_phy_write(dev, 0x0059, backup_phy[7]);
983	b43legacy_phy_write(dev, 0x0058, backup_phy[8]);
984	b43legacy_phy_write(dev, 0x000A, backup_phy[9]);
985	b43legacy_phy_write(dev, 0x0003, backup_phy[10]);
986	b43legacy_phy_write(dev, 0x080F, backup_phy[11]);
987	b43legacy_phy_write(dev, 0x0810, backup_phy[12]);
988	b43legacy_phy_write(dev, 0x002B, backup_phy[13]);
989	b43legacy_phy_write(dev, 0x0015, backup_phy[14]);
990
991	b43legacy_phy_set_baseband_attenuation(dev, backup_bband);
992
993	b43legacy_radio_write16(dev, 0x0052, backup_radio[0]);
994	b43legacy_radio_write16(dev, 0x0043, backup_radio[1]);
995	b43legacy_radio_write16(dev, 0x007A, backup_radio[2]);
996
997	b43legacy_phy_write(dev, 0x0811, backup_phy[2] | 0x0003);
998	udelay(10);
999	b43legacy_phy_write(dev, 0x0811, backup_phy[2]);
1000	b43legacy_phy_write(dev, 0x0812, backup_phy[3]);
1001	b43legacy_phy_write(dev, 0x0429, backup_phy[0]);
1002	b43legacy_phy_write(dev, 0x0001, backup_phy[1]);
1003
1004	phy->loopback_gain[0] = ((loop1_done * 6) - (loop1_omitted * 4)) - 11;
1005	phy->loopback_gain[1] = (24 - (3 * loop2_done)) * 2;
1006}
1007
1008static void b43legacy_phy_initg(struct b43legacy_wldev *dev)
1009{
1010	struct b43legacy_phy *phy = &dev->phy;
1011	u16 tmp;
1012
1013	if (phy->rev == 1)
1014		b43legacy_phy_initb5(dev);
1015	else
1016		b43legacy_phy_initb6(dev);
1017	if (phy->rev >= 2 && phy->gmode)
1018		b43legacy_phy_inita(dev);
1019
1020	if (phy->rev >= 2) {
1021		b43legacy_phy_write(dev, 0x0814, 0x0000);
1022		b43legacy_phy_write(dev, 0x0815, 0x0000);
1023	}
1024	if (phy->rev == 2) {
1025		b43legacy_phy_write(dev, 0x0811, 0x0000);
1026		b43legacy_phy_write(dev, 0x0015, 0x00C0);
1027	}
1028	if (phy->rev > 5) {
1029		b43legacy_phy_write(dev, 0x0811, 0x0400);
1030		b43legacy_phy_write(dev, 0x0015, 0x00C0);
1031	}
1032	if (phy->gmode) {
1033		tmp = b43legacy_phy_read(dev, 0x0400) & 0xFF;
1034		if (tmp == 3) {
1035			b43legacy_phy_write(dev, 0x04C2, 0x1816);
1036			b43legacy_phy_write(dev, 0x04C3, 0x8606);
1037		}
1038		if (tmp == 4 || tmp == 5) {
1039			b43legacy_phy_write(dev, 0x04C2, 0x1816);
1040			b43legacy_phy_write(dev, 0x04C3, 0x8006);
1041			b43legacy_phy_write(dev, 0x04CC,
1042					    (b43legacy_phy_read(dev,
1043					     0x04CC) & 0x00FF) |
1044					     0x1F00);
1045		}
1046		if (phy->rev >= 2)
1047			b43legacy_phy_write(dev, 0x047E, 0x0078);
1048	}
1049	if (phy->radio_rev == 8) {
1050		b43legacy_phy_write(dev, 0x0801, b43legacy_phy_read(dev, 0x0801)
1051				    | 0x0080);
1052		b43legacy_phy_write(dev, 0x043E, b43legacy_phy_read(dev, 0x043E)
1053				    | 0x0004);
1054	}
1055	if (phy->rev >= 2 && phy->gmode)
1056		b43legacy_calc_loopback_gain(dev);
1057	if (phy->radio_rev != 8) {
1058		if (phy->initval == 0xFFFF)
1059			phy->initval = b43legacy_radio_init2050(dev);
1060		else
1061			b43legacy_radio_write16(dev, 0x0078, phy->initval);
1062	}
1063	if (phy->txctl2 == 0xFFFF)
1064		b43legacy_phy_lo_g_measure(dev);
1065	else {
1066		if (phy->radio_ver == 0x2050 && phy->radio_rev == 8)
1067			b43legacy_radio_write16(dev, 0x0052,
1068						(phy->txctl1 << 4) |
1069						phy->txctl2);
1070		else
1071			b43legacy_radio_write16(dev, 0x0052,
1072						(b43legacy_radio_read16(dev,
1073						 0x0052) & 0xFFF0) |
1074						 phy->txctl1);
1075		if (phy->rev >= 6)
1076			b43legacy_phy_write(dev, 0x0036,
1077					    (b43legacy_phy_read(dev, 0x0036)
1078					     & 0x0FFF) | (phy->txctl2 << 12));
1079		if (dev->dev->bus->sprom.boardflags_lo &
1080		    B43legacy_BFL_PACTRL)
1081			b43legacy_phy_write(dev, 0x002E, 0x8075);
1082		else
1083			b43legacy_phy_write(dev, 0x002E, 0x807F);
1084		if (phy->rev < 2)
1085			b43legacy_phy_write(dev, 0x002F, 0x0101);
1086		else
1087			b43legacy_phy_write(dev, 0x002F, 0x0202);
1088	}
1089	if (phy->gmode) {
1090		b43legacy_phy_lo_adjust(dev, 0);
1091		b43legacy_phy_write(dev, 0x080F, 0x8078);
1092	}
1093
1094	if (!(dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI)) {
1095		/* The specs state to update the NRSSI LT with
1096		 * the value 0x7FFFFFFF here. I think that is some weird
1097		 * compiler optimization in the original driver.
1098		 * Essentially, what we do here is resetting all NRSSI LT
1099		 * entries to -32 (see the clamp_val() in nrssi_hw_update())
1100		 */
1101		b43legacy_nrssi_hw_update(dev, 0xFFFF);
1102		b43legacy_calc_nrssi_threshold(dev);
1103	} else if (phy->gmode || phy->rev >= 2) {
1104		if (phy->nrssi[0] == -1000) {
1105			B43legacy_WARN_ON(phy->nrssi[1] != -1000);
1106			b43legacy_calc_nrssi_slope(dev);
1107		} else {
1108			B43legacy_WARN_ON(phy->nrssi[1] == -1000);
1109			b43legacy_calc_nrssi_threshold(dev);
1110		}
1111	}
1112	if (phy->radio_rev == 8)
1113		b43legacy_phy_write(dev, 0x0805, 0x3230);
1114	b43legacy_phy_init_pctl(dev);
1115	if (dev->dev->bus->chip_id == 0x4306
1116	    && dev->dev->bus->chip_package == 2) {
1117		b43legacy_phy_write(dev, 0x0429,
1118				    b43legacy_phy_read(dev, 0x0429) & 0xBFFF);
1119		b43legacy_phy_write(dev, 0x04C3,
1120				    b43legacy_phy_read(dev, 0x04C3) & 0x7FFF);
1121	}
1122}
1123
1124static u16 b43legacy_phy_lo_b_r15_loop(struct b43legacy_wldev *dev)
1125{
1126	int i;
1127	u16 ret = 0;
1128	unsigned long flags;
1129
1130	local_irq_save(flags);
1131	for (i = 0; i < 10; i++) {
1132		b43legacy_phy_write(dev, 0x0015, 0xAFA0);
1133		udelay(1);
1134		b43legacy_phy_write(dev, 0x0015, 0xEFA0);
1135		udelay(10);
1136		b43legacy_phy_write(dev, 0x0015, 0xFFA0);
1137		udelay(40);
1138		ret += b43legacy_phy_read(dev, 0x002C);
1139	}
1140	local_irq_restore(flags);
1141	b43legacy_voluntary_preempt();
1142
1143	return ret;
1144}
1145
1146void b43legacy_phy_lo_b_measure(struct b43legacy_wldev *dev)
1147{
1148	struct b43legacy_phy *phy = &dev->phy;
1149	u16 regstack[12] = { 0 };
1150	u16 mls;
1151	u16 fval;
1152	int i;
1153	int j;
1154
1155	regstack[0] = b43legacy_phy_read(dev, 0x0015);
1156	regstack[1] = b43legacy_radio_read16(dev, 0x0052) & 0xFFF0;
1157
1158	if (phy->radio_ver == 0x2053) {
1159		regstack[2] = b43legacy_phy_read(dev, 0x000A);
1160		regstack[3] = b43legacy_phy_read(dev, 0x002A);
1161		regstack[4] = b43legacy_phy_read(dev, 0x0035);
1162		regstack[5] = b43legacy_phy_read(dev, 0x0003);
1163		regstack[6] = b43legacy_phy_read(dev, 0x0001);
1164		regstack[7] = b43legacy_phy_read(dev, 0x0030);
1165
1166		regstack[8] = b43legacy_radio_read16(dev, 0x0043);
1167		regstack[9] = b43legacy_radio_read16(dev, 0x007A);
1168		regstack[10] = b43legacy_read16(dev, 0x03EC);
1169		regstack[11] = b43legacy_radio_read16(dev, 0x0052) & 0x00F0;
1170
1171		b43legacy_phy_write(dev, 0x0030, 0x00FF);
1172		b43legacy_write16(dev, 0x03EC, 0x3F3F);
1173		b43legacy_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
1174		b43legacy_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
1175	}
1176	b43legacy_phy_write(dev, 0x0015, 0xB000);
1177	b43legacy_phy_write(dev, 0x002B, 0x0004);
1178
1179	if (phy->radio_ver == 0x2053) {
1180		b43legacy_phy_write(dev, 0x002B, 0x0203);
1181		b43legacy_phy_write(dev, 0x002A, 0x08A3);
1182	}
1183
1184	phy->minlowsig[0] = 0xFFFF;
1185
1186	for (i = 0; i < 4; i++) {
1187		b43legacy_radio_write16(dev, 0x0052, regstack[1] | i);
1188		b43legacy_phy_lo_b_r15_loop(dev);
1189	}
1190	for (i = 0; i < 10; i++) {
1191		b43legacy_radio_write16(dev, 0x0052, regstack[1] | i);
1192		mls = b43legacy_phy_lo_b_r15_loop(dev) / 10;
1193		if (mls < phy->minlowsig[0]) {
1194			phy->minlowsig[0] = mls;
1195			phy->minlowsigpos[0] = i;
1196		}
1197	}
1198	b43legacy_radio_write16(dev, 0x0052, regstack[1]
1199				| phy->minlowsigpos[0]);
1200
1201	phy->minlowsig[1] = 0xFFFF;
1202
1203	for (i = -4; i < 5; i += 2) {
1204		for (j = -4; j < 5; j += 2) {
1205			if (j < 0)
1206				fval = (0x0100 * i) + j + 0x0100;
1207			else
1208				fval = (0x0100 * i) + j;
1209			b43legacy_phy_write(dev, 0x002F, fval);
1210			mls = b43legacy_phy_lo_b_r15_loop(dev) / 10;
1211			if (mls < phy->minlowsig[1]) {
1212				phy->minlowsig[1] = mls;
1213				phy->minlowsigpos[1] = fval;
1214			}
1215		}
1216	}
1217	phy->minlowsigpos[1] += 0x0101;
1218
1219	b43legacy_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
1220	if (phy->radio_ver == 0x2053) {
1221		b43legacy_phy_write(dev, 0x000A, regstack[2]);
1222		b43legacy_phy_write(dev, 0x002A, regstack[3]);
1223		b43legacy_phy_write(dev, 0x0035, regstack[4]);
1224		b43legacy_phy_write(dev, 0x0003, regstack[5]);
1225		b43legacy_phy_write(dev, 0x0001, regstack[6]);
1226		b43legacy_phy_write(dev, 0x0030, regstack[7]);
1227
1228		b43legacy_radio_write16(dev, 0x0043, regstack[8]);
1229		b43legacy_radio_write16(dev, 0x007A, regstack[9]);
1230
1231		b43legacy_radio_write16(dev, 0x0052,
1232					(b43legacy_radio_read16(dev, 0x0052)
1233					& 0x000F) | regstack[11]);
1234
1235		b43legacy_write16(dev, 0x03EC, regstack[10]);
1236	}
1237	b43legacy_phy_write(dev, 0x0015, regstack[0]);
1238}
1239
1240static inline
1241u16 b43legacy_phy_lo_g_deviation_subval(struct b43legacy_wldev *dev,
1242					u16 control)
1243{
1244	struct b43legacy_phy *phy = &dev->phy;
1245	u16 ret;
1246	unsigned long flags;
1247
1248	local_irq_save(flags);
1249	if (phy->gmode) {
1250		b43legacy_phy_write(dev, 0x15, 0xE300);
1251		control <<= 8;
1252		b43legacy_phy_write(dev, 0x0812, control | 0x00B0);
1253		udelay(5);
1254		b43legacy_phy_write(dev, 0x0812, control | 0x00B2);
1255		udelay(2);
1256		b43legacy_phy_write(dev, 0x0812, control | 0x00B3);
1257		udelay(4);
1258		b43legacy_phy_write(dev, 0x0015, 0xF300);
1259		udelay(8);
1260	} else {
1261		b43legacy_phy_write(dev, 0x0015, control | 0xEFA0);
1262		udelay(2);
1263		b43legacy_phy_write(dev, 0x0015, control | 0xEFE0);
1264		udelay(4);
1265		b43legacy_phy_write(dev, 0x0015, control | 0xFFE0);
1266		udelay(8);
1267	}
1268	ret = b43legacy_phy_read(dev, 0x002D);
1269	local_irq_restore(flags);
1270	b43legacy_voluntary_preempt();
1271
1272	return ret;
1273}
1274
1275static u32 b43legacy_phy_lo_g_singledeviation(struct b43legacy_wldev *dev,
1276					      u16 control)
1277{
1278	int i;
1279	u32 ret = 0;
1280
1281	for (i = 0; i < 8; i++)
1282		ret += b43legacy_phy_lo_g_deviation_subval(dev, control);
1283
1284	return ret;
1285}
1286
1287/* Write the LocalOscillator CONTROL */
1288static inline
1289void b43legacy_lo_write(struct b43legacy_wldev *dev,
1290			struct b43legacy_lopair *pair)
1291{
1292	u16 value;
1293
1294	value = (u8)(pair->low);
1295	value |= ((u8)(pair->high)) << 8;
1296
1297#ifdef CONFIG_B43LEGACY_DEBUG
1298	/* Sanity check. */
1299	if (pair->low < -8 || pair->low > 8 ||
1300	    pair->high < -8 || pair->high > 8) {
1301		b43legacydbg(dev->wl,
1302		       "WARNING: Writing invalid LOpair "
1303		       "(low: %d, high: %d)\n",
1304		       pair->low, pair->high);
1305		dump_stack();
1306	}
1307#endif
1308
1309	b43legacy_phy_write(dev, B43legacy_PHY_G_LO_CONTROL, value);
1310}
1311
1312static inline
1313struct b43legacy_lopair *b43legacy_find_lopair(struct b43legacy_wldev *dev,
1314					       u16 bbatt,
1315					       u16 rfatt,
1316					       u16 tx)
1317{
1318	static const u8 dict[10] = { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
1319	struct b43legacy_phy *phy = &dev->phy;
1320
1321	if (bbatt > 6)
1322		bbatt = 6;
1323	B43legacy_WARN_ON(rfatt >= 10);
1324
1325	if (tx == 3)
1326		return b43legacy_get_lopair(phy, rfatt, bbatt);
1327	return b43legacy_get_lopair(phy, dict[rfatt], bbatt);
1328}
1329
1330static inline
1331struct b43legacy_lopair *b43legacy_current_lopair(struct b43legacy_wldev *dev)
1332{
1333	struct b43legacy_phy *phy = &dev->phy;
1334
1335	return b43legacy_find_lopair(dev, phy->bbatt,
1336				     phy->rfatt, phy->txctl1);
1337}
1338
1339/* Adjust B/G LO */
1340void b43legacy_phy_lo_adjust(struct b43legacy_wldev *dev, int fixed)
1341{
1342	struct b43legacy_lopair *pair;
1343
1344	if (fixed) {
1345		/* Use fixed values. Only for initialization. */
1346		pair = b43legacy_find_lopair(dev, 2, 3, 0);
1347	} else
1348		pair = b43legacy_current_lopair(dev);
1349	b43legacy_lo_write(dev, pair);
1350}
1351
1352static void b43legacy_phy_lo_g_measure_txctl2(struct b43legacy_wldev *dev)
1353{
1354	struct b43legacy_phy *phy = &dev->phy;
1355	u16 txctl2 = 0;
1356	u16 i;
1357	u32 smallest;
1358	u32 tmp;
1359
1360	b43legacy_radio_write16(dev, 0x0052, 0x0000);
1361	udelay(10);
1362	smallest = b43legacy_phy_lo_g_singledeviation(dev, 0);
1363	for (i = 0; i < 16; i++) {
1364		b43legacy_radio_write16(dev, 0x0052, i);
1365		udelay(10);
1366		tmp = b43legacy_phy_lo_g_singledeviation(dev, 0);
1367		if (tmp < smallest) {
1368			smallest = tmp;
1369			txctl2 = i;
1370		}
1371	}
1372	phy->txctl2 = txctl2;
1373}
1374
1375static
1376void b43legacy_phy_lo_g_state(struct b43legacy_wldev *dev,
1377			      const struct b43legacy_lopair *in_pair,
1378			      struct b43legacy_lopair *out_pair,
1379			      u16 r27)
1380{
1381	static const struct b43legacy_lopair transitions[8] = {
1382		{ .high =  1,  .low =  1, },
1383		{ .high =  1,  .low =  0, },
1384		{ .high =  1,  .low = -1, },
1385		{ .high =  0,  .low = -1, },
1386		{ .high = -1,  .low = -1, },
1387		{ .high = -1,  .low =  0, },
1388		{ .high = -1,  .low =  1, },
1389		{ .high =  0,  .low =  1, },
1390	};
1391	struct b43legacy_lopair lowest_transition = {
1392		.high = in_pair->high,
1393		.low = in_pair->low,
1394	};
1395	struct b43legacy_lopair tmp_pair;
1396	struct b43legacy_lopair transition;
1397	int i = 12;
1398	int state = 0;
1399	int found_lower;
1400	int j;
1401	int begin;
1402	int end;
1403	u32 lowest_deviation;
1404	u32 tmp;
1405
1406	/* Note that in_pair and out_pair can point to the same pair.
1407	 * Be careful. */
1408
1409	b43legacy_lo_write(dev, &lowest_transition);
1410	lowest_deviation = b43legacy_phy_lo_g_singledeviation(dev, r27);
1411	do {
1412		found_lower = 0;
1413		B43legacy_WARN_ON(!(state >= 0 && state <= 8));
1414		if (state == 0) {
1415			begin = 1;
1416			end = 8;
1417		} else if (state % 2 == 0) {
1418			begin = state - 1;
1419			end = state + 1;
1420		} else {
1421			begin = state - 2;
1422			end = state + 2;
1423		}
1424		if (begin < 1)
1425			begin += 8;
1426		if (end > 8)
1427			end -= 8;
1428
1429		j = begin;
1430		tmp_pair.high = lowest_transition.high;
1431		tmp_pair.low = lowest_transition.low;
1432		while (1) {
1433			B43legacy_WARN_ON(!(j >= 1 && j <= 8));
1434			transition.high = tmp_pair.high +
1435					  transitions[j - 1].high;
1436			transition.low = tmp_pair.low + transitions[j - 1].low;
1437			if ((abs(transition.low) < 9)
1438			     && (abs(transition.high) < 9)) {
1439				b43legacy_lo_write(dev, &transition);
1440				tmp = b43legacy_phy_lo_g_singledeviation(dev,
1441								       r27);
1442				if (tmp < lowest_deviation) {
1443					lowest_deviation = tmp;
1444					state = j;
1445					found_lower = 1;
1446
1447					lowest_transition.high =
1448								transition.high;
1449					lowest_transition.low = transition.low;
1450				}
1451			}
1452			if (j == end)
1453				break;
1454			if (j == 8)
1455				j = 1;
1456			else
1457				j++;
1458		}
1459	} while (i-- && found_lower);
1460
1461	out_pair->high = lowest_transition.high;
1462	out_pair->low = lowest_transition.low;
1463}
1464
1465/* Set the baseband attenuation value on chip. */
1466void b43legacy_phy_set_baseband_attenuation(struct b43legacy_wldev *dev,
1467					    u16 bbatt)
1468{
1469	struct b43legacy_phy *phy = &dev->phy;
1470	u16 value;
1471
1472	if (phy->analog == 0) {
1473		value = (b43legacy_read16(dev, 0x03E6) & 0xFFF0);
1474		value |= (bbatt & 0x000F);
1475		b43legacy_write16(dev, 0x03E6, value);
1476		return;
1477	}
1478
1479	if (phy->analog > 1) {
1480		value = b43legacy_phy_read(dev, 0x0060) & 0xFFC3;
1481		value |= (bbatt << 2) & 0x003C;
1482	} else {
1483		value = b43legacy_phy_read(dev, 0x0060) & 0xFF87;
1484		value |= (bbatt << 3) & 0x0078;
1485	}
1486	b43legacy_phy_write(dev, 0x0060, value);
1487}
1488
1489/* http://bcm-specs.sipsolutions.net/LocalOscillator/Measure */
1490void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev)
1491{
1492	static const u8 pairorder[10] = { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8 };
1493	const int is_initializing = (b43legacy_status(dev)
1494				     < B43legacy_STAT_STARTED);
1495	struct b43legacy_phy *phy = &dev->phy;
1496	u16 h;
1497	u16 i;
1498	u16 oldi = 0;
1499	u16 j;
1500	struct b43legacy_lopair control;
1501	struct b43legacy_lopair *tmp_control;
1502	u16 tmp;
1503	u16 regstack[16] = { 0 };
1504	u8 oldchannel;
1505
1506	/* XXX: What are these? */
1507	u8 r27 = 0;
1508	u16 r31;
1509
1510	oldchannel = phy->channel;
1511	/* Setup */
1512	if (phy->gmode) {
1513		regstack[0] = b43legacy_phy_read(dev, B43legacy_PHY_G_CRS);
1514		regstack[1] = b43legacy_phy_read(dev, 0x0802);
1515		b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]
1516				    & 0x7FFF);
1517		b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC);
1518	}
1519	regstack[3] = b43legacy_read16(dev, 0x03E2);
1520	b43legacy_write16(dev, 0x03E2, regstack[3] | 0x8000);
1521	regstack[4] = b43legacy_read16(dev, B43legacy_MMIO_CHANNEL_EXT);
1522	regstack[5] = b43legacy_phy_read(dev, 0x15);
1523	regstack[6] = b43legacy_phy_read(dev, 0x2A);
1524	regstack[7] = b43legacy_phy_read(dev, 0x35);
1525	regstack[8] = b43legacy_phy_read(dev, 0x60);
1526	regstack[9] = b43legacy_radio_read16(dev, 0x43);
1527	regstack[10] = b43legacy_radio_read16(dev, 0x7A);
1528	regstack[11] = b43legacy_radio_read16(dev, 0x52);
1529	if (phy->gmode) {
1530		regstack[12] = b43legacy_phy_read(dev, 0x0811);
1531		regstack[13] = b43legacy_phy_read(dev, 0x0812);
1532		regstack[14] = b43legacy_phy_read(dev, 0x0814);
1533		regstack[15] = b43legacy_phy_read(dev, 0x0815);
1534	}
1535	b43legacy_radio_selectchannel(dev, 6, 0);
1536	if (phy->gmode) {
1537		b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]
1538				    & 0x7FFF);
1539		b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC);
1540		b43legacy_dummy_transmission(dev);
1541	}
1542	b43legacy_radio_write16(dev, 0x0043, 0x0006);
1543
1544	b43legacy_phy_set_baseband_attenuation(dev, 2);
1545
1546	b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x0000);
1547	b43legacy_phy_write(dev, 0x002E, 0x007F);
1548	b43legacy_phy_write(dev, 0x080F, 0x0078);
1549	b43legacy_phy_write(dev, 0x0035, regstack[7] & ~(1 << 7));
1550	b43legacy_radio_write16(dev, 0x007A, regstack[10] & 0xFFF0);
1551	b43legacy_phy_write(dev, 0x002B, 0x0203);
1552	b43legacy_phy_write(dev, 0x002A, 0x08A3);
1553	if (phy->gmode) {
1554		b43legacy_phy_write(dev, 0x0814, regstack[14] | 0x0003);
1555		b43legacy_phy_write(dev, 0x0815, regstack[15] & 0xFFFC);
1556		b43legacy_phy_write(dev, 0x0811, 0x01B3);
1557		b43legacy_phy_write(dev, 0x0812, 0x00B2);
1558	}
1559	if (is_initializing)
1560		b43legacy_phy_lo_g_measure_txctl2(dev);
1561	b43legacy_phy_write(dev, 0x080F, 0x8078);
1562
1563	/* Measure */
1564	control.low = 0;
1565	control.high = 0;
1566	for (h = 0; h < 10; h++) {
1567		/* Loop over each possible RadioAttenuation (0-9) */
1568		i = pairorder[h];
1569		if (is_initializing) {
1570			if (i == 3) {
1571				control.low = 0;
1572				control.high = 0;
1573			} else if (((i % 2 == 1) && (oldi % 2 == 1)) ||
1574				  ((i % 2 == 0) && (oldi % 2 == 0))) {
1575				tmp_control = b43legacy_get_lopair(phy, oldi,
1576								   0);
1577				memcpy(&control, tmp_control, sizeof(control));
1578			} else {
1579				tmp_control = b43legacy_get_lopair(phy, 3, 0);
1580				memcpy(&control, tmp_control, sizeof(control));
1581			}
1582		}
1583		/* Loop over each possible BasebandAttenuation/2 */
1584		for (j = 0; j < 4; j++) {
1585			if (is_initializing) {
1586				tmp = i * 2 + j;
1587				r27 = 0;
1588				r31 = 0;
1589				if (tmp > 14) {
1590					r31 = 1;
1591					if (tmp > 17)
1592						r27 = 1;
1593					if (tmp > 19)
1594						r27 = 2;
1595				}
1596			} else {
1597				tmp_control = b43legacy_get_lopair(phy, i,
1598								   j * 2);
1599				if (!tmp_control->used)
1600					continue;
1601				memcpy(&control, tmp_control, sizeof(control));
1602				r27 = 3;
1603				r31 = 0;
1604			}
1605			b43legacy_radio_write16(dev, 0x43, i);
1606			b43legacy_radio_write16(dev, 0x52, phy->txctl2);
1607			udelay(10);
1608			b43legacy_voluntary_preempt();
1609
1610			b43legacy_phy_set_baseband_attenuation(dev, j * 2);
1611
1612			tmp = (regstack[10] & 0xFFF0);
1613			if (r31)
1614				tmp |= 0x0008;
1615			b43legacy_radio_write16(dev, 0x007A, tmp);
1616
1617			tmp_control = b43legacy_get_lopair(phy, i, j * 2);
1618			b43legacy_phy_lo_g_state(dev, &control, tmp_control,
1619						 r27);
1620		}
1621		oldi = i;
1622	}
1623	/* Loop over each possible RadioAttenuation (10-13) */
1624	for (i = 10; i < 14; i++) {
1625		/* Loop over each possible BasebandAttenuation/2 */
1626		for (j = 0; j < 4; j++) {
1627			if (is_initializing) {
1628				tmp_control = b43legacy_get_lopair(phy, i - 9,
1629								 j * 2);
1630				memcpy(&control, tmp_control, sizeof(control));
1631				/* FIXME: The next line is wrong, as the
1632				 * following if statement can never trigger. */
1633				tmp = (i - 9) * 2 + j - 5;
1634				r27 = 0;
1635				r31 = 0;
1636				if (tmp > 14) {
1637					r31 = 1;
1638					if (tmp > 17)
1639						r27 = 1;
1640					if (tmp > 19)
1641						r27 = 2;
1642				}
1643			} else {
1644				tmp_control = b43legacy_get_lopair(phy, i - 9,
1645								   j * 2);
1646				if (!tmp_control->used)
1647					continue;
1648				memcpy(&control, tmp_control, sizeof(control));
1649				r27 = 3;
1650				r31 = 0;
1651			}
1652			b43legacy_radio_write16(dev, 0x43, i - 9);
1653			/* FIXME: shouldn't txctl1 be zero in the next line
1654			 * and 3 in the loop above? */
1655			b43legacy_radio_write16(dev, 0x52,
1656					      phy->txctl2
1657					      | (3/*txctl1*/ << 4));
1658			udelay(10);
1659			b43legacy_voluntary_preempt();
1660
1661			b43legacy_phy_set_baseband_attenuation(dev, j * 2);
1662
1663			tmp = (regstack[10] & 0xFFF0);
1664			if (r31)
1665				tmp |= 0x0008;
1666			b43legacy_radio_write16(dev, 0x7A, tmp);
1667
1668			tmp_control = b43legacy_get_lopair(phy, i, j * 2);
1669			b43legacy_phy_lo_g_state(dev, &control, tmp_control,
1670						 r27);
1671		}
1672	}
1673
1674	/* Restoration */
1675	if (phy->gmode) {
1676		b43legacy_phy_write(dev, 0x0015, 0xE300);
1677		b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA0);
1678		udelay(5);
1679		b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA2);
1680		udelay(2);
1681		b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA3);
1682		b43legacy_voluntary_preempt();
1683	} else
1684		b43legacy_phy_write(dev, 0x0015, r27 | 0xEFA0);
1685	b43legacy_phy_lo_adjust(dev, is_initializing);
1686	b43legacy_phy_write(dev, 0x002E, 0x807F);
1687	if (phy->gmode)
1688		b43legacy_phy_write(dev, 0x002F, 0x0202);
1689	else
1690		b43legacy_phy_write(dev, 0x002F, 0x0101);
1691	b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, regstack[4]);
1692	b43legacy_phy_write(dev, 0x0015, regstack[5]);
1693	b43legacy_phy_write(dev, 0x002A, regstack[6]);
1694	b43legacy_phy_write(dev, 0x0035, regstack[7]);
1695	b43legacy_phy_write(dev, 0x0060, regstack[8]);
1696	b43legacy_radio_write16(dev, 0x0043, regstack[9]);
1697	b43legacy_radio_write16(dev, 0x007A, regstack[10]);
1698	regstack[11] &= 0x00F0;
1699	regstack[11] |= (b43legacy_radio_read16(dev, 0x52) & 0x000F);
1700	b43legacy_radio_write16(dev, 0x52, regstack[11]);
1701	b43legacy_write16(dev, 0x03E2, regstack[3]);
1702	if (phy->gmode) {
1703		b43legacy_phy_write(dev, 0x0811, regstack[12]);
1704		b43legacy_phy_write(dev, 0x0812, regstack[13]);
1705		b43legacy_phy_write(dev, 0x0814, regstack[14]);
1706		b43legacy_phy_write(dev, 0x0815, regstack[15]);
1707		b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]);
1708		b43legacy_phy_write(dev, 0x0802, regstack[1]);
1709	}
1710	b43legacy_radio_selectchannel(dev, oldchannel, 1);
1711
1712#ifdef CONFIG_B43LEGACY_DEBUG
1713	{
1714		/* Sanity check for all lopairs. */
1715		for (i = 0; i < B43legacy_LO_COUNT; i++) {
1716			tmp_control = phy->_lo_pairs + i;
1717			if (tmp_control->low < -8 || tmp_control->low > 8 ||
1718			    tmp_control->high < -8 || tmp_control->high > 8)
1719				b43legacywarn(dev->wl,
1720				       "WARNING: Invalid LOpair (low: %d, high:"
1721				       " %d, index: %d)\n",
1722				       tmp_control->low, tmp_control->high, i);
1723		}
1724	}
1725#endif /* CONFIG_B43LEGACY_DEBUG */
1726}
1727
1728static
1729void b43legacy_phy_lo_mark_current_used(struct b43legacy_wldev *dev)
1730{
1731	struct b43legacy_lopair *pair;
1732
1733	pair = b43legacy_current_lopair(dev);
1734	pair->used = 1;
1735}
1736
1737void b43legacy_phy_lo_mark_all_unused(struct b43legacy_wldev *dev)
1738{
1739	struct b43legacy_phy *phy = &dev->phy;
1740	struct b43legacy_lopair *pair;
1741	int i;
1742
1743	for (i = 0; i < B43legacy_LO_COUNT; i++) {
1744		pair = phy->_lo_pairs + i;
1745		pair->used = 0;
1746	}
1747}
1748
1749/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1750 * This function converts a TSSI value to dBm in Q5.2
1751 */
1752static s8 b43legacy_phy_estimate_power_out(struct b43legacy_wldev *dev, s8 tssi)
1753{
1754	struct b43legacy_phy *phy = &dev->phy;
1755	s8 dbm = 0;
1756	s32 tmp;
1757
1758	tmp = phy->idle_tssi;
1759	tmp += tssi;
1760	tmp -= phy->savedpctlreg;
1761
1762	switch (phy->type) {
1763	case B43legacy_PHYTYPE_B:
1764	case B43legacy_PHYTYPE_G:
1765		tmp = clamp_val(tmp, 0x00, 0x3F);
1766		dbm = phy->tssi2dbm[tmp];
1767		break;
1768	default:
1769		B43legacy_BUG_ON(1);
1770	}
1771
1772	return dbm;
1773}
1774
1775/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1776void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev)
1777{
1778	struct b43legacy_phy *phy = &dev->phy;
1779	u16 tmp;
1780	u16 txpower;
1781	s8 v0;
1782	s8 v1;
1783	s8 v2;
1784	s8 v3;
1785	s8 average;
1786	int max_pwr;
1787	s16 desired_pwr;
1788	s16 estimated_pwr;
1789	s16 pwr_adjust;
1790	s16 radio_att_delta;
1791	s16 baseband_att_delta;
1792	s16 radio_attenuation;
1793	s16 baseband_attenuation;
1794
1795	if (phy->savedpctlreg == 0xFFFF)
1796		return;
1797	if ((dev->dev->bus->boardinfo.type == 0x0416) &&
1798	    is_bcm_board_vendor(dev))
1799		return;
1800#ifdef CONFIG_B43LEGACY_DEBUG
1801	if (phy->manual_txpower_control)
1802		return;
1803#endif
1804
1805	B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B ||
1806			 phy->type == B43legacy_PHYTYPE_G));
1807	tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x0058);
1808	v0 = (s8)(tmp & 0x00FF);
1809	v1 = (s8)((tmp & 0xFF00) >> 8);
1810	tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005A);
1811	v2 = (s8)(tmp & 0x00FF);
1812	v3 = (s8)((tmp & 0xFF00) >> 8);
1813	tmp = 0;
1814
1815	if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
1816		tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1817					 0x0070);
1818		v0 = (s8)(tmp & 0x00FF);
1819		v1 = (s8)((tmp & 0xFF00) >> 8);
1820		tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1821					 0x0072);
1822		v2 = (s8)(tmp & 0x00FF);
1823		v3 = (s8)((tmp & 0xFF00) >> 8);
1824		if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
1825			return;
1826		v0 = (v0 + 0x20) & 0x3F;
1827		v1 = (v1 + 0x20) & 0x3F;
1828		v2 = (v2 + 0x20) & 0x3F;
1829		v3 = (v3 + 0x20) & 0x3F;
1830		tmp = 1;
1831	}
1832	b43legacy_radio_clear_tssi(dev);
1833
1834	average = (v0 + v1 + v2 + v3 + 2) / 4;
1835
1836	if (tmp && (b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005E)
1837	    & 0x8))
1838		average -= 13;
1839
1840	estimated_pwr = b43legacy_phy_estimate_power_out(dev, average);
1841
1842	max_pwr = dev->dev->bus->sprom.maxpwr_bg;
1843
1844	if ((dev->dev->bus->sprom.boardflags_lo
1845	     & B43legacy_BFL_PACTRL) &&
1846	    (phy->type == B43legacy_PHYTYPE_G))
1847		max_pwr -= 0x3;
1848	if (unlikely(max_pwr <= 0)) {
1849		b43legacywarn(dev->wl, "Invalid max-TX-power value in SPROM."
1850			"\n");
1851		max_pwr = 74; /* fake it */
1852		dev->dev->bus->sprom.maxpwr_bg = max_pwr;
1853	}
1854
1855	/* Use regulatory information to get the maximum power.
1856	 * In the absence of such data from mac80211, we will use 20 dBm, which
1857	 * is the value for the EU, US, Canada, and most of the world.
1858	 * The regulatory maximum is reduced by the antenna gain (from sprom)
1859	 * and 1.5 dBm (a safety factor??). The result is in Q5.2 format
1860	 * which accounts for the factor of 4 */
1861#define REG_MAX_PWR 20
1862	max_pwr = min(REG_MAX_PWR * 4
1863		      - dev->dev->bus->sprom.antenna_gain.a0
1864		      - 0x6, max_pwr);
1865
1866	/* find the desired power in Q5.2 - power_level is in dBm
1867	 * and limit it - max_pwr is already in Q5.2 */
1868	desired_pwr = clamp_val(phy->power_level << 2, 0, max_pwr);
1869	if (b43legacy_debug(dev, B43legacy_DBG_XMITPOWER))
1870		b43legacydbg(dev->wl, "Current TX power output: " Q52_FMT
1871		       " dBm, Desired TX power output: " Q52_FMT
1872		       " dBm\n", Q52_ARG(estimated_pwr),
1873		       Q52_ARG(desired_pwr));
1874	/* Check if we need to adjust the current power. The factor of 2 is
1875	 * for damping */
1876	pwr_adjust = (desired_pwr - estimated_pwr) / 2;
1877	/* RF attenuation delta
1878	 * The minus sign is because lower attenuation => more power */
1879	radio_att_delta = -(pwr_adjust + 7) >> 3;
1880	/* Baseband attenuation delta */
1881	baseband_att_delta = -(pwr_adjust >> 1) - (4 * radio_att_delta);
1882	/* Do we need to adjust anything? */
1883	if ((radio_att_delta == 0) && (baseband_att_delta == 0)) {
1884		b43legacy_phy_lo_mark_current_used(dev);
1885		return;
1886	}
1887
1888	/* Calculate the new attenuation values. */
1889	baseband_attenuation = phy->bbatt;
1890	baseband_attenuation += baseband_att_delta;
1891	radio_attenuation = phy->rfatt;
1892	radio_attenuation += radio_att_delta;
1893
1894	/* Get baseband and radio attenuation values into permitted ranges.
1895	 * baseband 0-11, radio 0-9.
1896	 * Radio attenuation affects power level 4 times as much as baseband.
1897	 */
1898	if (radio_attenuation < 0) {
1899		baseband_attenuation -= (4 * -radio_attenuation);
1900		radio_attenuation = 0;
1901	} else if (radio_attenuation > 9) {
1902		baseband_attenuation += (4 * (radio_attenuation - 9));
1903		radio_attenuation = 9;
1904	} else {
1905		while (baseband_attenuation < 0 && radio_attenuation > 0) {
1906			baseband_attenuation += 4;
1907			radio_attenuation--;
1908		}
1909		while (baseband_attenuation > 11 && radio_attenuation < 9) {
1910			baseband_attenuation -= 4;
1911			radio_attenuation++;
1912		}
1913	}
1914	baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1915
1916	txpower = phy->txctl1;
1917	if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
1918		if (radio_attenuation <= 1) {
1919			if (txpower == 0) {
1920				txpower = 3;
1921				radio_attenuation += 2;
1922				baseband_attenuation += 2;
1923			} else if (dev->dev->bus->sprom.boardflags_lo
1924				   & B43legacy_BFL_PACTRL) {
1925				baseband_attenuation += 4 *
1926						     (radio_attenuation - 2);
1927				radio_attenuation = 2;
1928			}
1929		} else if (radio_attenuation > 4 && txpower != 0) {
1930			txpower = 0;
1931			if (baseband_attenuation < 3) {
1932				radio_attenuation -= 3;
1933				baseband_attenuation += 2;
1934			} else {
1935				radio_attenuation -= 2;
1936				baseband_attenuation -= 2;
1937			}
1938		}
1939	}
1940	/* Save the control values */
1941	phy->txctl1 = txpower;
1942	baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1943	radio_attenuation = clamp_val(radio_attenuation, 0, 9);
1944	phy->rfatt = radio_attenuation;
1945	phy->bbatt = baseband_attenuation;
1946
1947	/* Adjust the hardware */
1948	b43legacy_phy_lock(dev);
1949	b43legacy_radio_lock(dev);
1950	b43legacy_radio_set_txpower_bg(dev, baseband_attenuation,
1951				       radio_attenuation, txpower);
1952	b43legacy_phy_lo_mark_current_used(dev);
1953	b43legacy_radio_unlock(dev);
1954	b43legacy_phy_unlock(dev);
1955}
1956
1957static inline
1958s32 b43legacy_tssi2dbm_ad(s32 num, s32 den)
1959{
1960	if (num < 0)
1961		return num/den;
1962	else
1963		return (num+den/2)/den;
1964}
1965
1966static inline
1967s8 b43legacy_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
1968{
1969	s32 m1;
1970	s32 m2;
1971	s32 f = 256;
1972	s32 q;
1973	s32 delta;
1974	s8 i = 0;
1975
1976	m1 = b43legacy_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1977	m2 = max(b43legacy_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1978	do {
1979		if (i > 15)
1980			return -EINVAL;
1981		q = b43legacy_tssi2dbm_ad(f * 4096 -
1982					  b43legacy_tssi2dbm_ad(m2 * f, 16) *
1983					  f, 2048);
1984		delta = abs(q - f);
1985		f = q;
1986		i++;
1987	} while (delta >= 2);
1988	entry[index] = clamp_val(b43legacy_tssi2dbm_ad(m1 * f, 8192),
1989				   -127, 128);
1990	return 0;
1991}
1992
1993/* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1994int b43legacy_phy_init_tssi2dbm_table(struct b43legacy_wldev *dev)
1995{
1996	struct b43legacy_phy *phy = &dev->phy;
1997	s16 pab0;
1998	s16 pab1;
1999	s16 pab2;
2000	u8 idx;
2001	s8 *dyn_tssi2dbm;
2002
2003	B43legacy_WARN_ON(!(phy->type == B43legacy_PHYTYPE_B ||
2004			  phy->type == B43legacy_PHYTYPE_G));
2005	pab0 = (s16)(dev->dev->bus->sprom.pa0b0);
2006	pab1 = (s16)(dev->dev->bus->sprom.pa0b1);
2007	pab2 = (s16)(dev->dev->bus->sprom.pa0b2);
2008
2009	if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2010		phy->idle_tssi = 0x34;
2011		phy->tssi2dbm = b43legacy_tssi2dbm_b_table;
2012		return 0;
2013	}
2014
2015	if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2016	    pab0 != -1 && pab1 != -1 && pab2 != -1) {
2017		/* The pabX values are set in SPROM. Use them. */
2018		if ((s8)dev->dev->bus->sprom.itssi_bg != 0 &&
2019		    (s8)dev->dev->bus->sprom.itssi_bg != -1)
2020			phy->idle_tssi = (s8)(dev->dev->bus->sprom.
2021					  itssi_bg);
2022		else
2023			phy->idle_tssi = 62;
2024		dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2025		if (dyn_tssi2dbm == NULL) {
2026			b43legacyerr(dev->wl, "Could not allocate memory "
2027			       "for tssi2dbm table\n");
2028			return -ENOMEM;
2029		}
2030		for (idx = 0; idx < 64; idx++)
2031			if (b43legacy_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0,
2032						     pab1, pab2)) {
2033				phy->tssi2dbm = NULL;
2034				b43legacyerr(dev->wl, "Could not generate "
2035				       "tssi2dBm table\n");
2036				kfree(dyn_tssi2dbm);
2037				return -ENODEV;
2038			}
2039		phy->tssi2dbm = dyn_tssi2dbm;
2040		phy->dyn_tssi_tbl = 1;
2041	} else {
2042		/* pabX values not set in SPROM. */
2043		switch (phy->type) {
2044		case B43legacy_PHYTYPE_B:
2045			phy->idle_tssi = 0x34;
2046			phy->tssi2dbm = b43legacy_tssi2dbm_b_table;
2047			break;
2048		case B43legacy_PHYTYPE_G:
2049			phy->idle_tssi = 0x34;
2050			phy->tssi2dbm = b43legacy_tssi2dbm_g_table;
2051			break;
2052		}
2053	}
2054
2055	return 0;
2056}
2057
2058int b43legacy_phy_init(struct b43legacy_wldev *dev)
2059{
2060	struct b43legacy_phy *phy = &dev->phy;
2061	int err = -ENODEV;
2062
2063	switch (phy->type) {
2064	case B43legacy_PHYTYPE_B:
2065		switch (phy->rev) {
2066		case 2:
2067			b43legacy_phy_initb2(dev);
2068			err = 0;
2069			break;
2070		case 4:
2071			b43legacy_phy_initb4(dev);
2072			err = 0;
2073			break;
2074		case 5:
2075			b43legacy_phy_initb5(dev);
2076			err = 0;
2077			break;
2078		case 6:
2079			b43legacy_phy_initb6(dev);
2080			err = 0;
2081			break;
2082		}
2083		break;
2084	case B43legacy_PHYTYPE_G:
2085		b43legacy_phy_initg(dev);
2086		err = 0;
2087		break;
2088	}
2089	if (err)
2090		b43legacyerr(dev->wl, "Unknown PHYTYPE found\n");
2091
2092	return err;
2093}
2094
2095void b43legacy_phy_set_antenna_diversity(struct b43legacy_wldev *dev)
2096{
2097	struct b43legacy_phy *phy = &dev->phy;
2098	u16 antennadiv;
2099	u16 offset;
2100	u16 value;
2101	u32 ucodeflags;
2102
2103	antennadiv = phy->antenna_diversity;
2104
2105	if (antennadiv == 0xFFFF)
2106		antennadiv = 3;
2107	B43legacy_WARN_ON(antennadiv > 3);
2108
2109	ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2110					  B43legacy_UCODEFLAGS_OFFSET);
2111	b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
2112			      B43legacy_UCODEFLAGS_OFFSET,
2113			      ucodeflags & ~B43legacy_UCODEFLAG_AUTODIV);
2114
2115	switch (phy->type) {
2116	case B43legacy_PHYTYPE_G:
2117		offset = 0x0400;
2118
2119		if (antennadiv == 2)
2120			value = (3/*automatic*/ << 7);
2121		else
2122			value = (antennadiv << 7);
2123		b43legacy_phy_write(dev, offset + 1,
2124				    (b43legacy_phy_read(dev, offset + 1)
2125				    & 0x7E7F) | value);
2126
2127		if (antennadiv >= 2) {
2128			if (antennadiv == 2)
2129				value = (antennadiv << 7);
2130			else
2131				value = (0/*force0*/ << 7);
2132			b43legacy_phy_write(dev, offset + 0x2B,
2133					    (b43legacy_phy_read(dev,
2134					    offset + 0x2B)
2135					    & 0xFEFF) | value);
2136		}
2137
2138		if (phy->type == B43legacy_PHYTYPE_G) {
2139			if (antennadiv >= 2)
2140				b43legacy_phy_write(dev, 0x048C,
2141						    b43legacy_phy_read(dev,
2142						    0x048C) | 0x2000);
2143			else
2144				b43legacy_phy_write(dev, 0x048C,
2145						    b43legacy_phy_read(dev,
2146						    0x048C) & ~0x2000);
2147			if (phy->rev >= 2) {
2148				b43legacy_phy_write(dev, 0x0461,
2149						    b43legacy_phy_read(dev,
2150						    0x0461) | 0x0010);
2151				b43legacy_phy_write(dev, 0x04AD,
2152						    (b43legacy_phy_read(dev,
2153						    0x04AD)
2154						    & 0x00FF) | 0x0015);
2155				if (phy->rev == 2)
2156					b43legacy_phy_write(dev, 0x0427,
2157							    0x0008);
2158				else
2159					b43legacy_phy_write(dev, 0x0427,
2160						(b43legacy_phy_read(dev, 0x0427)
2161						 & 0x00FF) | 0x0008);
2162			} else if (phy->rev >= 6)
2163				b43legacy_phy_write(dev, 0x049B, 0x00DC);
2164		} else {
2165			if (phy->rev < 3)
2166				b43legacy_phy_write(dev, 0x002B,
2167						    (b43legacy_phy_read(dev,
2168						    0x002B) & 0x00FF)
2169						    | 0x0024);
2170			else {
2171				b43legacy_phy_write(dev, 0x0061,
2172						    b43legacy_phy_read(dev,
2173						    0x0061) | 0x0010);
2174				if (phy->rev == 3) {
2175					b43legacy_phy_write(dev, 0x0093,
2176							    0x001D);
2177					b43legacy_phy_write(dev, 0x0027,
2178							    0x0008);
2179				} else {
2180					b43legacy_phy_write(dev, 0x0093,
2181							    0x003A);
2182					b43legacy_phy_write(dev, 0x0027,
2183						(b43legacy_phy_read(dev, 0x0027)
2184						 & 0x00FF) | 0x0008);
2185				}
2186			}
2187		}
2188		break;
2189	case B43legacy_PHYTYPE_B:
2190		if (dev->dev->id.revision == 2)
2191			value = (3/*automatic*/ << 7);
2192		else
2193			value = (antennadiv << 7);
2194		b43legacy_phy_write(dev, 0x03E2,
2195				    (b43legacy_phy_read(dev, 0x03E2)
2196				    & 0xFE7F) | value);
2197		break;
2198	default:
2199		B43legacy_WARN_ON(1);
2200	}
2201
2202	if (antennadiv >= 2) {
2203		ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2204						  B43legacy_UCODEFLAGS_OFFSET);
2205		b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
2206				      B43legacy_UCODEFLAGS_OFFSET,
2207				      ucodeflags | B43legacy_UCODEFLAG_AUTODIV);
2208	}
2209
2210	phy->antenna_diversity = antennadiv;
2211}
2212
2213/* Set the PowerSavingControlBits.
2214 * Bitvalues:
2215 *   0  => unset the bit
2216 *   1  => set the bit
2217 *   -1 => calculate the bit
2218 */
2219void b43legacy_power_saving_ctl_bits(struct b43legacy_wldev *dev,
2220				     int bit25, int bit26)
2221{
2222	int i;
2223	u32 status;
2224
2225/* FIXME: Force 25 to off and 26 to on for now: */
2226bit25 = 0;
2227bit26 = 1;
2228
2229	if (bit25 == -1) {
2230		/* TODO: If powersave is not off and FIXME is not set and we
2231		 *	are not in adhoc and thus is not an AP and we arei
2232		 *	associated, set bit 25 */
2233	}
2234	if (bit26 == -1) {
2235		/* TODO: If the device is awake or this is an AP, or we are
2236		 *	scanning, or FIXME, or we are associated, or FIXME,
2237		 *	or the latest PS-Poll packet sent was successful,
2238		 *	set bit26  */
2239	}
2240	status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2241	if (bit25)
2242		status |= B43legacy_MACCTL_HWPS;
2243	else
2244		status &= ~B43legacy_MACCTL_HWPS;
2245	if (bit26)
2246		status |= B43legacy_MACCTL_AWAKE;
2247	else
2248		status &= ~B43legacy_MACCTL_AWAKE;
2249	b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
2250	if (bit26 && dev->dev->id.revision >= 5) {
2251		for (i = 0; i < 100; i++) {
2252			if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2253						 0x0040) != 4)
2254				break;
2255			udelay(10);
2256		}
2257	}
2258}
2259