1/* 2 * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices 3 * 4 * Author : Liu Junliang <liujunliang_ljl@163.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 */ 10 11#ifndef _SR9700_H 12#define _SR9700_H 13 14/* sr9700 spec. register table on Linux platform */ 15 16/* Network Control Reg */ 17#define SR_NCR 0x00 18#define NCR_RST (1 << 0) 19#define NCR_LBK (3 << 1) 20#define NCR_FDX (1 << 3) 21#define NCR_WAKEEN (1 << 6) 22/* Network Status Reg */ 23#define SR_NSR 0x01 24#define NSR_RXRDY (1 << 0) 25#define NSR_RXOV (1 << 1) 26#define NSR_TX1END (1 << 2) 27#define NSR_TX2END (1 << 3) 28#define NSR_TXFULL (1 << 4) 29#define NSR_WAKEST (1 << 5) 30#define NSR_LINKST (1 << 6) 31#define NSR_SPEED (1 << 7) 32/* Tx Control Reg */ 33#define SR_TCR 0x02 34#define TCR_CRC_DIS (1 << 1) 35#define TCR_PAD_DIS (1 << 2) 36#define TCR_LC_CARE (1 << 3) 37#define TCR_CRS_CARE (1 << 4) 38#define TCR_EXCECM (1 << 5) 39#define TCR_LF_EN (1 << 6) 40/* Tx Status Reg for Packet Index 1 */ 41#define SR_TSR1 0x03 42#define TSR1_EC (1 << 2) 43#define TSR1_COL (1 << 3) 44#define TSR1_LC (1 << 4) 45#define TSR1_NC (1 << 5) 46#define TSR1_LOC (1 << 6) 47#define TSR1_TLF (1 << 7) 48/* Tx Status Reg for Packet Index 2 */ 49#define SR_TSR2 0x04 50#define TSR2_EC (1 << 2) 51#define TSR2_COL (1 << 3) 52#define TSR2_LC (1 << 4) 53#define TSR2_NC (1 << 5) 54#define TSR2_LOC (1 << 6) 55#define TSR2_TLF (1 << 7) 56/* Rx Control Reg*/ 57#define SR_RCR 0x05 58#define RCR_RXEN (1 << 0) 59#define RCR_PRMSC (1 << 1) 60#define RCR_RUNT (1 << 2) 61#define RCR_ALL (1 << 3) 62#define RCR_DIS_CRC (1 << 4) 63#define RCR_DIS_LONG (1 << 5) 64/* Rx Status Reg */ 65#define SR_RSR 0x06 66#define RSR_AE (1 << 2) 67#define RSR_MF (1 << 6) 68#define RSR_RF (1 << 7) 69/* Rx Overflow Counter Reg */ 70#define SR_ROCR 0x07 71#define ROCR_ROC (0x7F << 0) 72#define ROCR_RXFU (1 << 7) 73/* Back Pressure Threshold Reg */ 74#define SR_BPTR 0x08 75#define BPTR_JPT (0x0F << 0) 76#define BPTR_BPHW (0x0F << 4) 77/* Flow Control Threshold Reg */ 78#define SR_FCTR 0x09 79#define FCTR_LWOT (0x0F << 0) 80#define FCTR_HWOT (0x0F << 4) 81/* rx/tx Flow Control Reg */ 82#define SR_FCR 0x0A 83#define FCR_FLCE (1 << 0) 84#define FCR_BKPA (1 << 4) 85#define FCR_TXPEN (1 << 5) 86#define FCR_TXPF (1 << 6) 87#define FCR_TXP0 (1 << 7) 88/* Eeprom & Phy Control Reg */ 89#define SR_EPCR 0x0B 90#define EPCR_ERRE (1 << 0) 91#define EPCR_ERPRW (1 << 1) 92#define EPCR_ERPRR (1 << 2) 93#define EPCR_EPOS (1 << 3) 94#define EPCR_WEP (1 << 4) 95/* Eeprom & Phy Address Reg */ 96#define SR_EPAR 0x0C 97#define EPAR_EROA (0x3F << 0) 98#define EPAR_PHY_ADR_MASK (0x03 << 6) 99#define EPAR_PHY_ADR (0x01 << 6) 100/* Eeprom & Phy Data Reg */ 101#define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */ 102/* Wakeup Control Reg */ 103#define SR_WCR 0x0F 104#define WCR_MAGICST (1 << 0) 105#define WCR_LINKST (1 << 2) 106#define WCR_MAGICEN (1 << 3) 107#define WCR_LINKEN (1 << 5) 108/* Physical Address Reg */ 109#define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */ 110/* Multicast Address Reg */ 111#define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */ 112/* 0x1e unused */ 113/* Phy Reset Reg */ 114#define SR_PRR 0x1F 115#define PRR_PHY_RST (1 << 0) 116/* Tx sdram Write Pointer Address Low */ 117#define SR_TWPAL 0x20 118/* Tx sdram Write Pointer Address High */ 119#define SR_TWPAH 0x21 120/* Tx sdram Read Pointer Address Low */ 121#define SR_TRPAL 0x22 122/* Tx sdram Read Pointer Address High */ 123#define SR_TRPAH 0x23 124/* Rx sdram Write Pointer Address Low */ 125#define SR_RWPAL 0x24 126/* Rx sdram Write Pointer Address High */ 127#define SR_RWPAH 0x25 128/* Rx sdram Read Pointer Address Low */ 129#define SR_RRPAL 0x26 130/* Rx sdram Read Pointer Address High */ 131#define SR_RRPAH 0x27 132/* Vendor ID register */ 133#define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */ 134/* Product ID register */ 135#define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */ 136/* CHIP Revision register */ 137#define SR_CHIPR 0x2C 138/* 0x2D --> 0xEF unused */ 139/* USB Device Address */ 140#define SR_USBDA 0xF0 141#define USBDA_USBFA (0x7F << 0) 142/* RX packet Counter Reg */ 143#define SR_RXC 0xF1 144/* Tx packet Counter & USB Status Reg */ 145#define SR_TXC_USBS 0xF2 146#define TXC_USBS_TXC0 (1 << 0) 147#define TXC_USBS_TXC1 (1 << 1) 148#define TXC_USBS_TXC2 (1 << 2) 149#define TXC_USBS_EP1RDY (1 << 5) 150#define TXC_USBS_SUSFLAG (1 << 6) 151#define TXC_USBS_RXFAULT (1 << 7) 152/* USB Control register */ 153#define SR_USBC 0xF4 154#define USBC_EP3NAK (1 << 4) 155#define USBC_EP3ACK (1 << 5) 156 157/* Register access commands and flags */ 158#define SR_RD_REGS 0x00 159#define SR_WR_REGS 0x01 160#define SR_WR_REG 0x03 161#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE) 162#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE) 163 164/* parameters */ 165#define SR_SHARE_TIMEOUT 1000 166#define SR_EEPROM_LEN 256 167#define SR_MCAST_SIZE 8 168#define SR_MCAST_ADDR_FLAG 0x80 169#define SR_MCAST_MAX 64 170#define SR_TX_OVERHEAD 2 /* 2bytes header */ 171#define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */ 172 173#endif /* _SR9700_H */ 174