1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2010-2012 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9#include <linux/pci.h> 10#include <linux/module.h> 11#include "net_driver.h" 12#include "efx.h" 13#include "nic.h" 14#include "io.h" 15#include "mcdi.h" 16#include "filter.h" 17#include "mcdi_pcol.h" 18#include "farch_regs.h" 19#include "siena_sriov.h" 20#include "vfdi.h" 21 22/* Number of longs required to track all the VIs in a VF */ 23#define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX) 24 25/* Maximum number of RX queues supported */ 26#define VF_MAX_RX_QUEUES 63 27 28/** 29 * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour 30 * @VF_TX_FILTER_OFF: Disabled 31 * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only 32 * 2 TX queues allowed per VF. 33 * @VF_TX_FILTER_ON: Enabled 34 */ 35enum efx_vf_tx_filter_mode { 36 VF_TX_FILTER_OFF, 37 VF_TX_FILTER_AUTO, 38 VF_TX_FILTER_ON, 39}; 40 41/** 42 * struct siena_vf - Back-end resource and protocol state for a PCI VF 43 * @efx: The Efx NIC owning this VF 44 * @pci_rid: The PCI requester ID for this VF 45 * @pci_name: The PCI name (formatted address) of this VF 46 * @index: Index of VF within its port and PF. 47 * @req: VFDI incoming request work item. Incoming USR_EV events are received 48 * by the NAPI handler, but must be handled by executing MCDI requests 49 * inside a work item. 50 * @req_addr: VFDI incoming request DMA address (in VF's PCI address space). 51 * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member. 52 * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member. 53 * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by 54 * @status_lock 55 * @busy: VFDI request queued to be processed or being processed. Receiving 56 * a VFDI request when @busy is set is an error condition. 57 * @buf: Incoming VFDI requests are DMA from the VF into this buffer. 58 * @buftbl_base: Buffer table entries for this VF start at this index. 59 * @rx_filtering: Receive filtering has been requested by the VF driver. 60 * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request. 61 * @rx_filter_qid: VF relative qid for RX filter requested by VF. 62 * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported. 63 * @tx_filter_mode: Transmit MAC filtering mode. 64 * @tx_filter_id: Transmit MAC filter ID. 65 * @addr: The MAC address and outer vlan tag of the VF. 66 * @status_addr: VF DMA address of page for &struct vfdi_status updates. 67 * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr, 68 * @peer_page_addrs and @peer_page_count from simultaneous 69 * updates by the VM and consumption by 70 * efx_siena_sriov_update_vf_addr() 71 * @peer_page_addrs: Pointer to an array of guest pages for local addresses. 72 * @peer_page_count: Number of entries in @peer_page_count. 73 * @evq0_addrs: Array of guest pages backing evq0. 74 * @evq0_count: Number of entries in @evq0_addrs. 75 * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler 76 * to wait for flush completions. 77 * @txq_lock: Mutex for TX queue allocation. 78 * @txq_mask: Mask of initialized transmit queues. 79 * @txq_count: Number of initialized transmit queues. 80 * @rxq_mask: Mask of initialized receive queues. 81 * @rxq_count: Number of initialized receive queues. 82 * @rxq_retry_mask: Mask or receive queues that need to be flushed again 83 * due to flush failure. 84 * @rxq_retry_count: Number of receive queues in @rxq_retry_mask. 85 * @reset_work: Work item to schedule a VF reset. 86 */ 87struct siena_vf { 88 struct efx_nic *efx; 89 unsigned int pci_rid; 90 char pci_name[13]; /* dddd:bb:dd.f */ 91 unsigned int index; 92 struct work_struct req; 93 u64 req_addr; 94 int req_type; 95 unsigned req_seqno; 96 unsigned msg_seqno; 97 bool busy; 98 struct efx_buffer buf; 99 unsigned buftbl_base; 100 bool rx_filtering; 101 enum efx_filter_flags rx_filter_flags; 102 unsigned rx_filter_qid; 103 int rx_filter_id; 104 enum efx_vf_tx_filter_mode tx_filter_mode; 105 int tx_filter_id; 106 struct vfdi_endpoint addr; 107 u64 status_addr; 108 struct mutex status_lock; 109 u64 *peer_page_addrs; 110 unsigned peer_page_count; 111 u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) / 112 EFX_BUF_SIZE]; 113 unsigned evq0_count; 114 wait_queue_head_t flush_waitq; 115 struct mutex txq_lock; 116 unsigned long txq_mask[VI_MASK_LENGTH]; 117 unsigned txq_count; 118 unsigned long rxq_mask[VI_MASK_LENGTH]; 119 unsigned rxq_count; 120 unsigned long rxq_retry_mask[VI_MASK_LENGTH]; 121 atomic_t rxq_retry_count; 122 struct work_struct reset_work; 123}; 124 125struct efx_memcpy_req { 126 unsigned int from_rid; 127 void *from_buf; 128 u64 from_addr; 129 unsigned int to_rid; 130 u64 to_addr; 131 unsigned length; 132}; 133 134/** 135 * struct efx_local_addr - A MAC address on the vswitch without a VF. 136 * 137 * Siena does not have a switch, so VFs can't transmit data to each 138 * other. Instead the VFs must be made aware of the local addresses 139 * on the vswitch, so that they can arrange for an alternative 140 * software datapath to be used. 141 * 142 * @link: List head for insertion into efx->local_addr_list. 143 * @addr: Ethernet address 144 */ 145struct efx_local_addr { 146 struct list_head link; 147 u8 addr[ETH_ALEN]; 148}; 149 150/** 151 * struct efx_endpoint_page - Page of vfdi_endpoint structures 152 * 153 * @link: List head for insertion into efx->local_page_list. 154 * @ptr: Pointer to page. 155 * @addr: DMA address of page. 156 */ 157struct efx_endpoint_page { 158 struct list_head link; 159 void *ptr; 160 dma_addr_t addr; 161}; 162 163/* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */ 164#define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \ 165 ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid)) 166#define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \ 167 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \ 168 (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE)) 169#define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \ 170 (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \ 171 (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE)) 172 173#define EFX_FIELD_MASK(_field) \ 174 ((1 << _field ## _WIDTH) - 1) 175 176/* VFs can only use this many transmit channels */ 177static unsigned int vf_max_tx_channels = 2; 178module_param(vf_max_tx_channels, uint, 0444); 179MODULE_PARM_DESC(vf_max_tx_channels, 180 "Limit the number of TX channels VFs can use"); 181 182static int max_vfs = -1; 183module_param(max_vfs, int, 0444); 184MODULE_PARM_DESC(max_vfs, 185 "Reduce the number of VFs initialized by the driver"); 186 187/* Workqueue used by VFDI communication. We can't use the global 188 * workqueue because it may be running the VF driver's probe() 189 * routine, which will be blocked there waiting for a VFDI response. 190 */ 191static struct workqueue_struct *vfdi_workqueue; 192 193static unsigned abs_index(struct siena_vf *vf, unsigned index) 194{ 195 return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index; 196} 197 198static int efx_siena_sriov_cmd(struct efx_nic *efx, bool enable, 199 unsigned *vi_scale_out, unsigned *vf_total_out) 200{ 201 MCDI_DECLARE_BUF(inbuf, MC_CMD_SRIOV_IN_LEN); 202 MCDI_DECLARE_BUF(outbuf, MC_CMD_SRIOV_OUT_LEN); 203 unsigned vi_scale, vf_total; 204 size_t outlen; 205 int rc; 206 207 MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0); 208 MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE); 209 MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count); 210 211 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN, 212 outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen); 213 if (rc) 214 return rc; 215 if (outlen < MC_CMD_SRIOV_OUT_LEN) 216 return -EIO; 217 218 vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL); 219 vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE); 220 if (vi_scale > EFX_VI_SCALE_MAX) 221 return -EOPNOTSUPP; 222 223 if (vi_scale_out) 224 *vi_scale_out = vi_scale; 225 if (vf_total_out) 226 *vf_total_out = vf_total; 227 228 return 0; 229} 230 231static void efx_siena_sriov_usrev(struct efx_nic *efx, bool enabled) 232{ 233 struct siena_nic_data *nic_data = efx->nic_data; 234 efx_oword_t reg; 235 236 EFX_POPULATE_OWORD_2(reg, 237 FRF_CZ_USREV_DIS, enabled ? 0 : 1, 238 FRF_CZ_DFLT_EVQ, nic_data->vfdi_channel->channel); 239 efx_writeo(efx, ®, FR_CZ_USR_EV_CFG); 240} 241 242static int efx_siena_sriov_memcpy(struct efx_nic *efx, 243 struct efx_memcpy_req *req, 244 unsigned int count) 245{ 246 MCDI_DECLARE_BUF(inbuf, MCDI_CTL_SDU_LEN_MAX_V1); 247 MCDI_DECLARE_STRUCT_PTR(record); 248 unsigned int index, used; 249 u64 from_addr; 250 u32 from_rid; 251 int rc; 252 253 mb(); /* Finish writing source/reading dest before DMA starts */ 254 255 if (WARN_ON(count > MC_CMD_MEMCPY_IN_RECORD_MAXNUM)) 256 return -ENOBUFS; 257 used = MC_CMD_MEMCPY_IN_LEN(count); 258 259 for (index = 0; index < count; index++) { 260 record = MCDI_ARRAY_STRUCT_PTR(inbuf, MEMCPY_IN_RECORD, index); 261 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_NUM_RECORDS, 262 count); 263 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID, 264 req->to_rid); 265 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR, 266 req->to_addr); 267 if (req->from_buf == NULL) { 268 from_rid = req->from_rid; 269 from_addr = req->from_addr; 270 } else { 271 if (WARN_ON(used + req->length > 272 MCDI_CTL_SDU_LEN_MAX_V1)) { 273 rc = -ENOBUFS; 274 goto out; 275 } 276 277 from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE; 278 from_addr = used; 279 memcpy(_MCDI_PTR(inbuf, used), req->from_buf, 280 req->length); 281 used += req->length; 282 } 283 284 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid); 285 MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR, 286 from_addr); 287 MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH, 288 req->length); 289 290 ++req; 291 } 292 293 rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL); 294out: 295 mb(); /* Don't write source/read dest before DMA is complete */ 296 297 return rc; 298} 299 300/* The TX filter is entirely controlled by this driver, and is modified 301 * underneath the feet of the VF 302 */ 303static void efx_siena_sriov_reset_tx_filter(struct siena_vf *vf) 304{ 305 struct efx_nic *efx = vf->efx; 306 struct efx_filter_spec filter; 307 u16 vlan; 308 int rc; 309 310 if (vf->tx_filter_id != -1) { 311 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED, 312 vf->tx_filter_id); 313 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n", 314 vf->pci_name, vf->tx_filter_id); 315 vf->tx_filter_id = -1; 316 } 317 318 if (is_zero_ether_addr(vf->addr.mac_addr)) 319 return; 320 321 /* Turn on TX filtering automatically if not explicitly 322 * enabled or disabled. 323 */ 324 if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2) 325 vf->tx_filter_mode = VF_TX_FILTER_ON; 326 327 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK; 328 efx_filter_init_tx(&filter, abs_index(vf, 0)); 329 rc = efx_filter_set_eth_local(&filter, 330 vlan ? vlan : EFX_FILTER_VID_UNSPEC, 331 vf->addr.mac_addr); 332 BUG_ON(rc); 333 334 rc = efx_filter_insert_filter(efx, &filter, true); 335 if (rc < 0) { 336 netif_warn(efx, hw, efx->net_dev, 337 "Unable to migrate tx filter for vf %s\n", 338 vf->pci_name); 339 } else { 340 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n", 341 vf->pci_name, rc); 342 vf->tx_filter_id = rc; 343 } 344} 345 346/* The RX filter is managed here on behalf of the VF driver */ 347static void efx_siena_sriov_reset_rx_filter(struct siena_vf *vf) 348{ 349 struct efx_nic *efx = vf->efx; 350 struct efx_filter_spec filter; 351 u16 vlan; 352 int rc; 353 354 if (vf->rx_filter_id != -1) { 355 efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED, 356 vf->rx_filter_id); 357 netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n", 358 vf->pci_name, vf->rx_filter_id); 359 vf->rx_filter_id = -1; 360 } 361 362 if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr)) 363 return; 364 365 vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK; 366 efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED, 367 vf->rx_filter_flags, 368 abs_index(vf, vf->rx_filter_qid)); 369 rc = efx_filter_set_eth_local(&filter, 370 vlan ? vlan : EFX_FILTER_VID_UNSPEC, 371 vf->addr.mac_addr); 372 BUG_ON(rc); 373 374 rc = efx_filter_insert_filter(efx, &filter, true); 375 if (rc < 0) { 376 netif_warn(efx, hw, efx->net_dev, 377 "Unable to insert rx filter for vf %s\n", 378 vf->pci_name); 379 } else { 380 netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n", 381 vf->pci_name, rc); 382 vf->rx_filter_id = rc; 383 } 384} 385 386static void __efx_siena_sriov_update_vf_addr(struct siena_vf *vf) 387{ 388 struct efx_nic *efx = vf->efx; 389 struct siena_nic_data *nic_data = efx->nic_data; 390 391 efx_siena_sriov_reset_tx_filter(vf); 392 efx_siena_sriov_reset_rx_filter(vf); 393 queue_work(vfdi_workqueue, &nic_data->peer_work); 394} 395 396/* Push the peer list to this VF. The caller must hold status_lock to interlock 397 * with VFDI requests, and they must be serialised against manipulation of 398 * local_page_list, either by acquiring local_lock or by running from 399 * efx_siena_sriov_peer_work() 400 */ 401static void __efx_siena_sriov_push_vf_status(struct siena_vf *vf) 402{ 403 struct efx_nic *efx = vf->efx; 404 struct siena_nic_data *nic_data = efx->nic_data; 405 struct vfdi_status *status = nic_data->vfdi_status.addr; 406 struct efx_memcpy_req copy[4]; 407 struct efx_endpoint_page *epp; 408 unsigned int pos, count; 409 unsigned data_offset; 410 efx_qword_t event; 411 412 WARN_ON(!mutex_is_locked(&vf->status_lock)); 413 WARN_ON(!vf->status_addr); 414 415 status->local = vf->addr; 416 status->generation_end = ++status->generation_start; 417 418 memset(copy, '\0', sizeof(copy)); 419 /* Write generation_start */ 420 copy[0].from_buf = &status->generation_start; 421 copy[0].to_rid = vf->pci_rid; 422 copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status, 423 generation_start); 424 copy[0].length = sizeof(status->generation_start); 425 /* DMA the rest of the structure (excluding the generations). This 426 * assumes that the non-generation portion of vfdi_status is in 427 * one chunk starting at the version member. 428 */ 429 data_offset = offsetof(struct vfdi_status, version); 430 copy[1].from_rid = efx->pci_dev->devfn; 431 copy[1].from_addr = nic_data->vfdi_status.dma_addr + data_offset; 432 copy[1].to_rid = vf->pci_rid; 433 copy[1].to_addr = vf->status_addr + data_offset; 434 copy[1].length = status->length - data_offset; 435 436 /* Copy the peer pages */ 437 pos = 2; 438 count = 0; 439 list_for_each_entry(epp, &nic_data->local_page_list, link) { 440 if (count == vf->peer_page_count) { 441 /* The VF driver will know they need to provide more 442 * pages because peer_addr_count is too large. 443 */ 444 break; 445 } 446 copy[pos].from_buf = NULL; 447 copy[pos].from_rid = efx->pci_dev->devfn; 448 copy[pos].from_addr = epp->addr; 449 copy[pos].to_rid = vf->pci_rid; 450 copy[pos].to_addr = vf->peer_page_addrs[count]; 451 copy[pos].length = EFX_PAGE_SIZE; 452 453 if (++pos == ARRAY_SIZE(copy)) { 454 efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy)); 455 pos = 0; 456 } 457 ++count; 458 } 459 460 /* Write generation_end */ 461 copy[pos].from_buf = &status->generation_end; 462 copy[pos].to_rid = vf->pci_rid; 463 copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status, 464 generation_end); 465 copy[pos].length = sizeof(status->generation_end); 466 efx_siena_sriov_memcpy(efx, copy, pos + 1); 467 468 /* Notify the guest */ 469 EFX_POPULATE_QWORD_3(event, 470 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV, 471 VFDI_EV_SEQ, (vf->msg_seqno & 0xff), 472 VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS); 473 ++vf->msg_seqno; 474 efx_farch_generate_event(efx, 475 EFX_VI_BASE + vf->index * efx_vf_size(efx), 476 &event); 477} 478 479static void efx_siena_sriov_bufs(struct efx_nic *efx, unsigned offset, 480 u64 *addr, unsigned count) 481{ 482 efx_qword_t buf; 483 unsigned pos; 484 485 for (pos = 0; pos < count; ++pos) { 486 EFX_POPULATE_QWORD_3(buf, 487 FRF_AZ_BUF_ADR_REGION, 0, 488 FRF_AZ_BUF_ADR_FBUF, 489 addr ? addr[pos] >> 12 : 0, 490 FRF_AZ_BUF_OWNER_ID_FBUF, 0); 491 efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL, 492 &buf, offset + pos); 493 } 494} 495 496static bool bad_vf_index(struct efx_nic *efx, unsigned index) 497{ 498 return index >= efx_vf_size(efx); 499} 500 501static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count) 502{ 503 unsigned max_buf_count = max_entry_count * 504 sizeof(efx_qword_t) / EFX_BUF_SIZE; 505 506 return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count); 507} 508 509/* Check that VI specified by per-port index belongs to a VF. 510 * Optionally set VF index and VI index within the VF. 511 */ 512static bool map_vi_index(struct efx_nic *efx, unsigned abs_index, 513 struct siena_vf **vf_out, unsigned *rel_index_out) 514{ 515 struct siena_nic_data *nic_data = efx->nic_data; 516 unsigned vf_i; 517 518 if (abs_index < EFX_VI_BASE) 519 return true; 520 vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx); 521 if (vf_i >= efx->vf_init_count) 522 return true; 523 524 if (vf_out) 525 *vf_out = nic_data->vf + vf_i; 526 if (rel_index_out) 527 *rel_index_out = abs_index % efx_vf_size(efx); 528 return false; 529} 530 531static int efx_vfdi_init_evq(struct siena_vf *vf) 532{ 533 struct efx_nic *efx = vf->efx; 534 struct vfdi_req *req = vf->buf.addr; 535 unsigned vf_evq = req->u.init_evq.index; 536 unsigned buf_count = req->u.init_evq.buf_count; 537 unsigned abs_evq = abs_index(vf, vf_evq); 538 unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq); 539 efx_oword_t reg; 540 541 if (bad_vf_index(efx, vf_evq) || 542 bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) { 543 if (net_ratelimit()) 544 netif_err(efx, hw, efx->net_dev, 545 "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n", 546 vf->pci_name, vf_evq, buf_count); 547 return VFDI_RC_EINVAL; 548 } 549 550 efx_siena_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count); 551 552 EFX_POPULATE_OWORD_3(reg, 553 FRF_CZ_TIMER_Q_EN, 1, 554 FRF_CZ_HOST_NOTIFY_MODE, 0, 555 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 556 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); 557 EFX_POPULATE_OWORD_3(reg, 558 FRF_AZ_EVQ_EN, 1, 559 FRF_AZ_EVQ_SIZE, __ffs(buf_count), 560 FRF_AZ_EVQ_BUF_BASE_ID, buftbl); 561 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); 562 563 if (vf_evq == 0) { 564 memcpy(vf->evq0_addrs, req->u.init_evq.addr, 565 buf_count * sizeof(u64)); 566 vf->evq0_count = buf_count; 567 } 568 569 return VFDI_RC_SUCCESS; 570} 571 572static int efx_vfdi_init_rxq(struct siena_vf *vf) 573{ 574 struct efx_nic *efx = vf->efx; 575 struct vfdi_req *req = vf->buf.addr; 576 unsigned vf_rxq = req->u.init_rxq.index; 577 unsigned vf_evq = req->u.init_rxq.evq; 578 unsigned buf_count = req->u.init_rxq.buf_count; 579 unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq); 580 unsigned label; 581 efx_oword_t reg; 582 583 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) || 584 vf_rxq >= VF_MAX_RX_QUEUES || 585 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) { 586 if (net_ratelimit()) 587 netif_err(efx, hw, efx->net_dev, 588 "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d " 589 "buf_count %d\n", vf->pci_name, vf_rxq, 590 vf_evq, buf_count); 591 return VFDI_RC_EINVAL; 592 } 593 if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask)) 594 ++vf->rxq_count; 595 efx_siena_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count); 596 597 label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL); 598 EFX_POPULATE_OWORD_6(reg, 599 FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl, 600 FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq), 601 FRF_AZ_RX_DESCQ_LABEL, label, 602 FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count), 603 FRF_AZ_RX_DESCQ_JUMBO, 604 !!(req->u.init_rxq.flags & 605 VFDI_RXQ_FLAG_SCATTER_EN), 606 FRF_AZ_RX_DESCQ_EN, 1); 607 efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, 608 abs_index(vf, vf_rxq)); 609 610 return VFDI_RC_SUCCESS; 611} 612 613static int efx_vfdi_init_txq(struct siena_vf *vf) 614{ 615 struct efx_nic *efx = vf->efx; 616 struct vfdi_req *req = vf->buf.addr; 617 unsigned vf_txq = req->u.init_txq.index; 618 unsigned vf_evq = req->u.init_txq.evq; 619 unsigned buf_count = req->u.init_txq.buf_count; 620 unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq); 621 unsigned label, eth_filt_en; 622 efx_oword_t reg; 623 624 if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) || 625 vf_txq >= vf_max_tx_channels || 626 bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) { 627 if (net_ratelimit()) 628 netif_err(efx, hw, efx->net_dev, 629 "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d " 630 "buf_count %d\n", vf->pci_name, vf_txq, 631 vf_evq, buf_count); 632 return VFDI_RC_EINVAL; 633 } 634 635 mutex_lock(&vf->txq_lock); 636 if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask)) 637 ++vf->txq_count; 638 mutex_unlock(&vf->txq_lock); 639 efx_siena_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count); 640 641 eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON; 642 643 label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL); 644 EFX_POPULATE_OWORD_8(reg, 645 FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U), 646 FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en, 647 FRF_AZ_TX_DESCQ_EN, 1, 648 FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl, 649 FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq), 650 FRF_AZ_TX_DESCQ_LABEL, label, 651 FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count), 652 FRF_BZ_TX_NON_IP_DROP_DIS, 1); 653 efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, 654 abs_index(vf, vf_txq)); 655 656 return VFDI_RC_SUCCESS; 657} 658 659/* Returns true when efx_vfdi_fini_all_queues should wake */ 660static bool efx_vfdi_flush_wake(struct siena_vf *vf) 661{ 662 /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */ 663 smp_mb(); 664 665 return (!vf->txq_count && !vf->rxq_count) || 666 atomic_read(&vf->rxq_retry_count); 667} 668 669static void efx_vfdi_flush_clear(struct siena_vf *vf) 670{ 671 memset(vf->txq_mask, 0, sizeof(vf->txq_mask)); 672 vf->txq_count = 0; 673 memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask)); 674 vf->rxq_count = 0; 675 memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask)); 676 atomic_set(&vf->rxq_retry_count, 0); 677} 678 679static int efx_vfdi_fini_all_queues(struct siena_vf *vf) 680{ 681 struct efx_nic *efx = vf->efx; 682 efx_oword_t reg; 683 unsigned count = efx_vf_size(efx); 684 unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx); 685 unsigned timeout = HZ; 686 unsigned index, rxqs_count; 687 MCDI_DECLARE_BUF(inbuf, MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX); 688 int rc; 689 690 BUILD_BUG_ON(VF_MAX_RX_QUEUES > 691 MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM); 692 693 rtnl_lock(); 694 siena_prepare_flush(efx); 695 rtnl_unlock(); 696 697 /* Flush all the initialized queues */ 698 rxqs_count = 0; 699 for (index = 0; index < count; ++index) { 700 if (test_bit(index, vf->txq_mask)) { 701 EFX_POPULATE_OWORD_2(reg, 702 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 703 FRF_AZ_TX_FLUSH_DESCQ, 704 vf_offset + index); 705 efx_writeo(efx, ®, FR_AZ_TX_FLUSH_DESCQ); 706 } 707 if (test_bit(index, vf->rxq_mask)) { 708 MCDI_SET_ARRAY_DWORD( 709 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, 710 rxqs_count, vf_offset + index); 711 rxqs_count++; 712 } 713 } 714 715 atomic_set(&vf->rxq_retry_count, 0); 716 while (timeout && (vf->rxq_count || vf->txq_count)) { 717 rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf, 718 MC_CMD_FLUSH_RX_QUEUES_IN_LEN(rxqs_count), 719 NULL, 0, NULL); 720 WARN_ON(rc < 0); 721 722 timeout = wait_event_timeout(vf->flush_waitq, 723 efx_vfdi_flush_wake(vf), 724 timeout); 725 rxqs_count = 0; 726 for (index = 0; index < count; ++index) { 727 if (test_and_clear_bit(index, vf->rxq_retry_mask)) { 728 atomic_dec(&vf->rxq_retry_count); 729 MCDI_SET_ARRAY_DWORD( 730 inbuf, FLUSH_RX_QUEUES_IN_QID_OFST, 731 rxqs_count, vf_offset + index); 732 rxqs_count++; 733 } 734 } 735 } 736 737 rtnl_lock(); 738 siena_finish_flush(efx); 739 rtnl_unlock(); 740 741 /* Irrespective of success/failure, fini the queues */ 742 EFX_ZERO_OWORD(reg); 743 for (index = 0; index < count; ++index) { 744 efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, 745 vf_offset + index); 746 efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, 747 vf_offset + index); 748 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, 749 vf_offset + index); 750 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, 751 vf_offset + index); 752 } 753 efx_siena_sriov_bufs(efx, vf->buftbl_base, NULL, 754 EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx)); 755 efx_vfdi_flush_clear(vf); 756 757 vf->evq0_count = 0; 758 759 return timeout ? 0 : VFDI_RC_ETIMEDOUT; 760} 761 762static int efx_vfdi_insert_filter(struct siena_vf *vf) 763{ 764 struct efx_nic *efx = vf->efx; 765 struct siena_nic_data *nic_data = efx->nic_data; 766 struct vfdi_req *req = vf->buf.addr; 767 unsigned vf_rxq = req->u.mac_filter.rxq; 768 unsigned flags; 769 770 if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) { 771 if (net_ratelimit()) 772 netif_err(efx, hw, efx->net_dev, 773 "ERROR: Invalid INSERT_FILTER from %s: rxq %d " 774 "flags 0x%x\n", vf->pci_name, vf_rxq, 775 req->u.mac_filter.flags); 776 return VFDI_RC_EINVAL; 777 } 778 779 flags = 0; 780 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS) 781 flags |= EFX_FILTER_FLAG_RX_RSS; 782 if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER) 783 flags |= EFX_FILTER_FLAG_RX_SCATTER; 784 vf->rx_filter_flags = flags; 785 vf->rx_filter_qid = vf_rxq; 786 vf->rx_filtering = true; 787 788 efx_siena_sriov_reset_rx_filter(vf); 789 queue_work(vfdi_workqueue, &nic_data->peer_work); 790 791 return VFDI_RC_SUCCESS; 792} 793 794static int efx_vfdi_remove_all_filters(struct siena_vf *vf) 795{ 796 struct efx_nic *efx = vf->efx; 797 struct siena_nic_data *nic_data = efx->nic_data; 798 799 vf->rx_filtering = false; 800 efx_siena_sriov_reset_rx_filter(vf); 801 queue_work(vfdi_workqueue, &nic_data->peer_work); 802 803 return VFDI_RC_SUCCESS; 804} 805 806static int efx_vfdi_set_status_page(struct siena_vf *vf) 807{ 808 struct efx_nic *efx = vf->efx; 809 struct siena_nic_data *nic_data = efx->nic_data; 810 struct vfdi_req *req = vf->buf.addr; 811 u64 page_count = req->u.set_status_page.peer_page_count; 812 u64 max_page_count = 813 (EFX_PAGE_SIZE - 814 offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0])) 815 / sizeof(req->u.set_status_page.peer_page_addr[0]); 816 817 if (!req->u.set_status_page.dma_addr || page_count > max_page_count) { 818 if (net_ratelimit()) 819 netif_err(efx, hw, efx->net_dev, 820 "ERROR: Invalid SET_STATUS_PAGE from %s\n", 821 vf->pci_name); 822 return VFDI_RC_EINVAL; 823 } 824 825 mutex_lock(&nic_data->local_lock); 826 mutex_lock(&vf->status_lock); 827 vf->status_addr = req->u.set_status_page.dma_addr; 828 829 kfree(vf->peer_page_addrs); 830 vf->peer_page_addrs = NULL; 831 vf->peer_page_count = 0; 832 833 if (page_count) { 834 vf->peer_page_addrs = kcalloc(page_count, sizeof(u64), 835 GFP_KERNEL); 836 if (vf->peer_page_addrs) { 837 memcpy(vf->peer_page_addrs, 838 req->u.set_status_page.peer_page_addr, 839 page_count * sizeof(u64)); 840 vf->peer_page_count = page_count; 841 } 842 } 843 844 __efx_siena_sriov_push_vf_status(vf); 845 mutex_unlock(&vf->status_lock); 846 mutex_unlock(&nic_data->local_lock); 847 848 return VFDI_RC_SUCCESS; 849} 850 851static int efx_vfdi_clear_status_page(struct siena_vf *vf) 852{ 853 mutex_lock(&vf->status_lock); 854 vf->status_addr = 0; 855 mutex_unlock(&vf->status_lock); 856 857 return VFDI_RC_SUCCESS; 858} 859 860typedef int (*efx_vfdi_op_t)(struct siena_vf *vf); 861 862static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = { 863 [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq, 864 [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq, 865 [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq, 866 [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues, 867 [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter, 868 [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters, 869 [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page, 870 [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page, 871}; 872 873static void efx_siena_sriov_vfdi(struct work_struct *work) 874{ 875 struct siena_vf *vf = container_of(work, struct siena_vf, req); 876 struct efx_nic *efx = vf->efx; 877 struct vfdi_req *req = vf->buf.addr; 878 struct efx_memcpy_req copy[2]; 879 int rc; 880 881 /* Copy this page into the local address space */ 882 memset(copy, '\0', sizeof(copy)); 883 copy[0].from_rid = vf->pci_rid; 884 copy[0].from_addr = vf->req_addr; 885 copy[0].to_rid = efx->pci_dev->devfn; 886 copy[0].to_addr = vf->buf.dma_addr; 887 copy[0].length = EFX_PAGE_SIZE; 888 rc = efx_siena_sriov_memcpy(efx, copy, 1); 889 if (rc) { 890 /* If we can't get the request, we can't reply to the caller */ 891 if (net_ratelimit()) 892 netif_err(efx, hw, efx->net_dev, 893 "ERROR: Unable to fetch VFDI request from %s rc %d\n", 894 vf->pci_name, -rc); 895 vf->busy = false; 896 return; 897 } 898 899 if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) { 900 rc = vfdi_ops[req->op](vf); 901 if (rc == 0) { 902 netif_dbg(efx, hw, efx->net_dev, 903 "vfdi request %d from %s ok\n", 904 req->op, vf->pci_name); 905 } 906 } else { 907 netif_dbg(efx, hw, efx->net_dev, 908 "ERROR: Unrecognised request %d from VF %s addr " 909 "%llx\n", req->op, vf->pci_name, 910 (unsigned long long)vf->req_addr); 911 rc = VFDI_RC_EOPNOTSUPP; 912 } 913 914 /* Allow subsequent VF requests */ 915 vf->busy = false; 916 smp_wmb(); 917 918 /* Respond to the request */ 919 req->rc = rc; 920 req->op = VFDI_OP_RESPONSE; 921 922 memset(copy, '\0', sizeof(copy)); 923 copy[0].from_buf = &req->rc; 924 copy[0].to_rid = vf->pci_rid; 925 copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc); 926 copy[0].length = sizeof(req->rc); 927 copy[1].from_buf = &req->op; 928 copy[1].to_rid = vf->pci_rid; 929 copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op); 930 copy[1].length = sizeof(req->op); 931 932 (void)efx_siena_sriov_memcpy(efx, copy, ARRAY_SIZE(copy)); 933} 934 935 936 937/* After a reset the event queues inside the guests no longer exist. Fill the 938 * event ring in guest memory with VFDI reset events, then (re-initialise) the 939 * event queue to raise an interrupt. The guest driver will then recover. 940 */ 941 942static void efx_siena_sriov_reset_vf(struct siena_vf *vf, 943 struct efx_buffer *buffer) 944{ 945 struct efx_nic *efx = vf->efx; 946 struct efx_memcpy_req copy_req[4]; 947 efx_qword_t event; 948 unsigned int pos, count, k, buftbl, abs_evq; 949 efx_oword_t reg; 950 efx_dword_t ptr; 951 int rc; 952 953 BUG_ON(buffer->len != EFX_PAGE_SIZE); 954 955 if (!vf->evq0_count) 956 return; 957 BUG_ON(vf->evq0_count & (vf->evq0_count - 1)); 958 959 mutex_lock(&vf->status_lock); 960 EFX_POPULATE_QWORD_3(event, 961 FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV, 962 VFDI_EV_SEQ, vf->msg_seqno, 963 VFDI_EV_TYPE, VFDI_EV_TYPE_RESET); 964 vf->msg_seqno++; 965 for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event)) 966 memcpy(buffer->addr + pos, &event, sizeof(event)); 967 968 for (pos = 0; pos < vf->evq0_count; pos += count) { 969 count = min_t(unsigned, vf->evq0_count - pos, 970 ARRAY_SIZE(copy_req)); 971 for (k = 0; k < count; k++) { 972 copy_req[k].from_buf = NULL; 973 copy_req[k].from_rid = efx->pci_dev->devfn; 974 copy_req[k].from_addr = buffer->dma_addr; 975 copy_req[k].to_rid = vf->pci_rid; 976 copy_req[k].to_addr = vf->evq0_addrs[pos + k]; 977 copy_req[k].length = EFX_PAGE_SIZE; 978 } 979 rc = efx_siena_sriov_memcpy(efx, copy_req, count); 980 if (rc) { 981 if (net_ratelimit()) 982 netif_err(efx, hw, efx->net_dev, 983 "ERROR: Unable to notify %s of reset" 984 ": %d\n", vf->pci_name, -rc); 985 break; 986 } 987 } 988 989 /* Reinitialise, arm and trigger evq0 */ 990 abs_evq = abs_index(vf, 0); 991 buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0); 992 efx_siena_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count); 993 994 EFX_POPULATE_OWORD_3(reg, 995 FRF_CZ_TIMER_Q_EN, 1, 996 FRF_CZ_HOST_NOTIFY_MODE, 0, 997 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 998 efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); 999 EFX_POPULATE_OWORD_3(reg, 1000 FRF_AZ_EVQ_EN, 1, 1001 FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count), 1002 FRF_AZ_EVQ_BUF_BASE_ID, buftbl); 1003 efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); 1004 EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0); 1005 efx_writed(efx, &ptr, FR_BZ_EVQ_RPTR + FR_BZ_EVQ_RPTR_STEP * abs_evq); 1006 1007 mutex_unlock(&vf->status_lock); 1008} 1009 1010static void efx_siena_sriov_reset_vf_work(struct work_struct *work) 1011{ 1012 struct siena_vf *vf = container_of(work, struct siena_vf, req); 1013 struct efx_nic *efx = vf->efx; 1014 struct efx_buffer buf; 1015 1016 if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) { 1017 efx_siena_sriov_reset_vf(vf, &buf); 1018 efx_nic_free_buffer(efx, &buf); 1019 } 1020} 1021 1022static void efx_siena_sriov_handle_no_channel(struct efx_nic *efx) 1023{ 1024 netif_err(efx, drv, efx->net_dev, 1025 "ERROR: IOV requires MSI-X and 1 additional interrupt" 1026 "vector. IOV disabled\n"); 1027 efx->vf_count = 0; 1028} 1029 1030static int efx_siena_sriov_probe_channel(struct efx_channel *channel) 1031{ 1032 struct siena_nic_data *nic_data = channel->efx->nic_data; 1033 nic_data->vfdi_channel = channel; 1034 1035 return 0; 1036} 1037 1038static void 1039efx_siena_sriov_get_channel_name(struct efx_channel *channel, 1040 char *buf, size_t len) 1041{ 1042 snprintf(buf, len, "%s-iov", channel->efx->name); 1043} 1044 1045static const struct efx_channel_type efx_siena_sriov_channel_type = { 1046 .handle_no_channel = efx_siena_sriov_handle_no_channel, 1047 .pre_probe = efx_siena_sriov_probe_channel, 1048 .post_remove = efx_channel_dummy_op_void, 1049 .get_name = efx_siena_sriov_get_channel_name, 1050 /* no copy operation; channel must not be reallocated */ 1051 .keep_eventq = true, 1052}; 1053 1054void efx_siena_sriov_probe(struct efx_nic *efx) 1055{ 1056 unsigned count; 1057 1058 if (!max_vfs) 1059 return; 1060 1061 if (efx_siena_sriov_cmd(efx, false, &efx->vi_scale, &count)) { 1062 netif_info(efx, probe, efx->net_dev, "no SR-IOV VFs probed\n"); 1063 return; 1064 } 1065 if (count > 0 && count > max_vfs) 1066 count = max_vfs; 1067 1068 /* efx_nic_dimension_resources() will reduce vf_count as appopriate */ 1069 efx->vf_count = count; 1070 1071 efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_siena_sriov_channel_type; 1072} 1073 1074/* Copy the list of individual addresses into the vfdi_status.peers 1075 * array and auxiliary pages, protected by %local_lock. Drop that lock 1076 * and then broadcast the address list to every VF. 1077 */ 1078static void efx_siena_sriov_peer_work(struct work_struct *data) 1079{ 1080 struct siena_nic_data *nic_data = container_of(data, 1081 struct siena_nic_data, 1082 peer_work); 1083 struct efx_nic *efx = nic_data->efx; 1084 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr; 1085 struct siena_vf *vf; 1086 struct efx_local_addr *local_addr; 1087 struct vfdi_endpoint *peer; 1088 struct efx_endpoint_page *epp; 1089 struct list_head pages; 1090 unsigned int peer_space; 1091 unsigned int peer_count; 1092 unsigned int pos; 1093 1094 mutex_lock(&nic_data->local_lock); 1095 1096 /* Move the existing peer pages off %local_page_list */ 1097 INIT_LIST_HEAD(&pages); 1098 list_splice_tail_init(&nic_data->local_page_list, &pages); 1099 1100 /* Populate the VF addresses starting from entry 1 (entry 0 is 1101 * the PF address) 1102 */ 1103 peer = vfdi_status->peers + 1; 1104 peer_space = ARRAY_SIZE(vfdi_status->peers) - 1; 1105 peer_count = 1; 1106 for (pos = 0; pos < efx->vf_count; ++pos) { 1107 vf = nic_data->vf + pos; 1108 1109 mutex_lock(&vf->status_lock); 1110 if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) { 1111 *peer++ = vf->addr; 1112 ++peer_count; 1113 --peer_space; 1114 BUG_ON(peer_space == 0); 1115 } 1116 mutex_unlock(&vf->status_lock); 1117 } 1118 1119 /* Fill the remaining addresses */ 1120 list_for_each_entry(local_addr, &nic_data->local_addr_list, link) { 1121 ether_addr_copy(peer->mac_addr, local_addr->addr); 1122 peer->tci = 0; 1123 ++peer; 1124 ++peer_count; 1125 if (--peer_space == 0) { 1126 if (list_empty(&pages)) { 1127 epp = kmalloc(sizeof(*epp), GFP_KERNEL); 1128 if (!epp) 1129 break; 1130 epp->ptr = dma_alloc_coherent( 1131 &efx->pci_dev->dev, EFX_PAGE_SIZE, 1132 &epp->addr, GFP_KERNEL); 1133 if (!epp->ptr) { 1134 kfree(epp); 1135 break; 1136 } 1137 } else { 1138 epp = list_first_entry( 1139 &pages, struct efx_endpoint_page, link); 1140 list_del(&epp->link); 1141 } 1142 1143 list_add_tail(&epp->link, &nic_data->local_page_list); 1144 peer = (struct vfdi_endpoint *)epp->ptr; 1145 peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint); 1146 } 1147 } 1148 vfdi_status->peer_count = peer_count; 1149 mutex_unlock(&nic_data->local_lock); 1150 1151 /* Free any now unused endpoint pages */ 1152 while (!list_empty(&pages)) { 1153 epp = list_first_entry( 1154 &pages, struct efx_endpoint_page, link); 1155 list_del(&epp->link); 1156 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE, 1157 epp->ptr, epp->addr); 1158 kfree(epp); 1159 } 1160 1161 /* Finally, push the pages */ 1162 for (pos = 0; pos < efx->vf_count; ++pos) { 1163 vf = nic_data->vf + pos; 1164 1165 mutex_lock(&vf->status_lock); 1166 if (vf->status_addr) 1167 __efx_siena_sriov_push_vf_status(vf); 1168 mutex_unlock(&vf->status_lock); 1169 } 1170} 1171 1172static void efx_siena_sriov_free_local(struct efx_nic *efx) 1173{ 1174 struct siena_nic_data *nic_data = efx->nic_data; 1175 struct efx_local_addr *local_addr; 1176 struct efx_endpoint_page *epp; 1177 1178 while (!list_empty(&nic_data->local_addr_list)) { 1179 local_addr = list_first_entry(&nic_data->local_addr_list, 1180 struct efx_local_addr, link); 1181 list_del(&local_addr->link); 1182 kfree(local_addr); 1183 } 1184 1185 while (!list_empty(&nic_data->local_page_list)) { 1186 epp = list_first_entry(&nic_data->local_page_list, 1187 struct efx_endpoint_page, link); 1188 list_del(&epp->link); 1189 dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE, 1190 epp->ptr, epp->addr); 1191 kfree(epp); 1192 } 1193} 1194 1195static int efx_siena_sriov_vf_alloc(struct efx_nic *efx) 1196{ 1197 unsigned index; 1198 struct siena_vf *vf; 1199 struct siena_nic_data *nic_data = efx->nic_data; 1200 1201 nic_data->vf = kcalloc(efx->vf_count, sizeof(*nic_data->vf), 1202 GFP_KERNEL); 1203 if (!nic_data->vf) 1204 return -ENOMEM; 1205 1206 for (index = 0; index < efx->vf_count; ++index) { 1207 vf = nic_data->vf + index; 1208 1209 vf->efx = efx; 1210 vf->index = index; 1211 vf->rx_filter_id = -1; 1212 vf->tx_filter_mode = VF_TX_FILTER_AUTO; 1213 vf->tx_filter_id = -1; 1214 INIT_WORK(&vf->req, efx_siena_sriov_vfdi); 1215 INIT_WORK(&vf->reset_work, efx_siena_sriov_reset_vf_work); 1216 init_waitqueue_head(&vf->flush_waitq); 1217 mutex_init(&vf->status_lock); 1218 mutex_init(&vf->txq_lock); 1219 } 1220 1221 return 0; 1222} 1223 1224static void efx_siena_sriov_vfs_fini(struct efx_nic *efx) 1225{ 1226 struct siena_nic_data *nic_data = efx->nic_data; 1227 struct siena_vf *vf; 1228 unsigned int pos; 1229 1230 for (pos = 0; pos < efx->vf_count; ++pos) { 1231 vf = nic_data->vf + pos; 1232 1233 efx_nic_free_buffer(efx, &vf->buf); 1234 kfree(vf->peer_page_addrs); 1235 vf->peer_page_addrs = NULL; 1236 vf->peer_page_count = 0; 1237 1238 vf->evq0_count = 0; 1239 } 1240} 1241 1242static int efx_siena_sriov_vfs_init(struct efx_nic *efx) 1243{ 1244 struct pci_dev *pci_dev = efx->pci_dev; 1245 struct siena_nic_data *nic_data = efx->nic_data; 1246 unsigned index, devfn, sriov, buftbl_base; 1247 u16 offset, stride; 1248 struct siena_vf *vf; 1249 int rc; 1250 1251 sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV); 1252 if (!sriov) 1253 return -ENOENT; 1254 1255 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset); 1256 pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride); 1257 1258 buftbl_base = nic_data->vf_buftbl_base; 1259 devfn = pci_dev->devfn + offset; 1260 for (index = 0; index < efx->vf_count; ++index) { 1261 vf = nic_data->vf + index; 1262 1263 /* Reserve buffer entries */ 1264 vf->buftbl_base = buftbl_base; 1265 buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx); 1266 1267 vf->pci_rid = devfn; 1268 snprintf(vf->pci_name, sizeof(vf->pci_name), 1269 "%04x:%02x:%02x.%d", 1270 pci_domain_nr(pci_dev->bus), pci_dev->bus->number, 1271 PCI_SLOT(devfn), PCI_FUNC(devfn)); 1272 1273 rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE, 1274 GFP_KERNEL); 1275 if (rc) 1276 goto fail; 1277 1278 devfn += stride; 1279 } 1280 1281 return 0; 1282 1283fail: 1284 efx_siena_sriov_vfs_fini(efx); 1285 return rc; 1286} 1287 1288int efx_siena_sriov_init(struct efx_nic *efx) 1289{ 1290 struct net_device *net_dev = efx->net_dev; 1291 struct siena_nic_data *nic_data = efx->nic_data; 1292 struct vfdi_status *vfdi_status; 1293 int rc; 1294 1295 /* Ensure there's room for vf_channel */ 1296 BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE); 1297 /* Ensure that VI_BASE is aligned on VI_SCALE */ 1298 BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1)); 1299 1300 if (efx->vf_count == 0) 1301 return 0; 1302 1303 rc = efx_siena_sriov_cmd(efx, true, NULL, NULL); 1304 if (rc) 1305 goto fail_cmd; 1306 1307 rc = efx_nic_alloc_buffer(efx, &nic_data->vfdi_status, 1308 sizeof(*vfdi_status), GFP_KERNEL); 1309 if (rc) 1310 goto fail_status; 1311 vfdi_status = nic_data->vfdi_status.addr; 1312 memset(vfdi_status, 0, sizeof(*vfdi_status)); 1313 vfdi_status->version = 1; 1314 vfdi_status->length = sizeof(*vfdi_status); 1315 vfdi_status->max_tx_channels = vf_max_tx_channels; 1316 vfdi_status->vi_scale = efx->vi_scale; 1317 vfdi_status->rss_rxq_count = efx->rss_spread; 1318 vfdi_status->peer_count = 1 + efx->vf_count; 1319 vfdi_status->timer_quantum_ns = efx->timer_quantum_ns; 1320 1321 rc = efx_siena_sriov_vf_alloc(efx); 1322 if (rc) 1323 goto fail_alloc; 1324 1325 mutex_init(&nic_data->local_lock); 1326 INIT_WORK(&nic_data->peer_work, efx_siena_sriov_peer_work); 1327 INIT_LIST_HEAD(&nic_data->local_addr_list); 1328 INIT_LIST_HEAD(&nic_data->local_page_list); 1329 1330 rc = efx_siena_sriov_vfs_init(efx); 1331 if (rc) 1332 goto fail_vfs; 1333 1334 rtnl_lock(); 1335 ether_addr_copy(vfdi_status->peers[0].mac_addr, net_dev->dev_addr); 1336 efx->vf_init_count = efx->vf_count; 1337 rtnl_unlock(); 1338 1339 efx_siena_sriov_usrev(efx, true); 1340 1341 /* At this point we must be ready to accept VFDI requests */ 1342 1343 rc = pci_enable_sriov(efx->pci_dev, efx->vf_count); 1344 if (rc) 1345 goto fail_pci; 1346 1347 netif_info(efx, probe, net_dev, 1348 "enabled SR-IOV for %d VFs, %d VI per VF\n", 1349 efx->vf_count, efx_vf_size(efx)); 1350 return 0; 1351 1352fail_pci: 1353 efx_siena_sriov_usrev(efx, false); 1354 rtnl_lock(); 1355 efx->vf_init_count = 0; 1356 rtnl_unlock(); 1357 efx_siena_sriov_vfs_fini(efx); 1358fail_vfs: 1359 cancel_work_sync(&nic_data->peer_work); 1360 efx_siena_sriov_free_local(efx); 1361 kfree(nic_data->vf); 1362fail_alloc: 1363 efx_nic_free_buffer(efx, &nic_data->vfdi_status); 1364fail_status: 1365 efx_siena_sriov_cmd(efx, false, NULL, NULL); 1366fail_cmd: 1367 return rc; 1368} 1369 1370void efx_siena_sriov_fini(struct efx_nic *efx) 1371{ 1372 struct siena_vf *vf; 1373 unsigned int pos; 1374 struct siena_nic_data *nic_data = efx->nic_data; 1375 1376 if (efx->vf_init_count == 0) 1377 return; 1378 1379 /* Disable all interfaces to reconfiguration */ 1380 BUG_ON(nic_data->vfdi_channel->enabled); 1381 efx_siena_sriov_usrev(efx, false); 1382 rtnl_lock(); 1383 efx->vf_init_count = 0; 1384 rtnl_unlock(); 1385 1386 /* Flush all reconfiguration work */ 1387 for (pos = 0; pos < efx->vf_count; ++pos) { 1388 vf = nic_data->vf + pos; 1389 cancel_work_sync(&vf->req); 1390 cancel_work_sync(&vf->reset_work); 1391 } 1392 cancel_work_sync(&nic_data->peer_work); 1393 1394 pci_disable_sriov(efx->pci_dev); 1395 1396 /* Tear down back-end state */ 1397 efx_siena_sriov_vfs_fini(efx); 1398 efx_siena_sriov_free_local(efx); 1399 kfree(nic_data->vf); 1400 efx_nic_free_buffer(efx, &nic_data->vfdi_status); 1401 efx_siena_sriov_cmd(efx, false, NULL, NULL); 1402} 1403 1404void efx_siena_sriov_event(struct efx_channel *channel, efx_qword_t *event) 1405{ 1406 struct efx_nic *efx = channel->efx; 1407 struct siena_vf *vf; 1408 unsigned qid, seq, type, data; 1409 1410 qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID); 1411 1412 /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */ 1413 BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0); 1414 seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ); 1415 type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE); 1416 data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA); 1417 1418 netif_vdbg(efx, hw, efx->net_dev, 1419 "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n", 1420 qid, seq, type, data); 1421 1422 if (map_vi_index(efx, qid, &vf, NULL)) 1423 return; 1424 if (vf->busy) 1425 goto error; 1426 1427 if (type == VFDI_EV_TYPE_REQ_WORD0) { 1428 /* Resynchronise */ 1429 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1430 vf->req_seqno = seq + 1; 1431 vf->req_addr = 0; 1432 } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type) 1433 goto error; 1434 1435 switch (vf->req_type) { 1436 case VFDI_EV_TYPE_REQ_WORD0: 1437 case VFDI_EV_TYPE_REQ_WORD1: 1438 case VFDI_EV_TYPE_REQ_WORD2: 1439 vf->req_addr |= (u64)data << (vf->req_type << 4); 1440 ++vf->req_type; 1441 return; 1442 1443 case VFDI_EV_TYPE_REQ_WORD3: 1444 vf->req_addr |= (u64)data << 48; 1445 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1446 vf->busy = true; 1447 queue_work(vfdi_workqueue, &vf->req); 1448 return; 1449 } 1450 1451error: 1452 if (net_ratelimit()) 1453 netif_err(efx, hw, efx->net_dev, 1454 "ERROR: Screaming VFDI request from %s\n", 1455 vf->pci_name); 1456 /* Reset the request and sequence number */ 1457 vf->req_type = VFDI_EV_TYPE_REQ_WORD0; 1458 vf->req_seqno = seq + 1; 1459} 1460 1461void efx_siena_sriov_flr(struct efx_nic *efx, unsigned vf_i) 1462{ 1463 struct siena_nic_data *nic_data = efx->nic_data; 1464 struct siena_vf *vf; 1465 1466 if (vf_i > efx->vf_init_count) 1467 return; 1468 vf = nic_data->vf + vf_i; 1469 netif_info(efx, hw, efx->net_dev, 1470 "FLR on VF %s\n", vf->pci_name); 1471 1472 vf->status_addr = 0; 1473 efx_vfdi_remove_all_filters(vf); 1474 efx_vfdi_flush_clear(vf); 1475 1476 vf->evq0_count = 0; 1477} 1478 1479int efx_siena_sriov_mac_address_changed(struct efx_nic *efx) 1480{ 1481 struct siena_nic_data *nic_data = efx->nic_data; 1482 struct vfdi_status *vfdi_status = nic_data->vfdi_status.addr; 1483 1484 if (!efx->vf_init_count) 1485 return 0; 1486 ether_addr_copy(vfdi_status->peers[0].mac_addr, 1487 efx->net_dev->dev_addr); 1488 queue_work(vfdi_workqueue, &nic_data->peer_work); 1489 1490 return 0; 1491} 1492 1493void efx_siena_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1494{ 1495 struct siena_vf *vf; 1496 unsigned queue, qid; 1497 1498 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); 1499 if (map_vi_index(efx, queue, &vf, &qid)) 1500 return; 1501 /* Ignore flush completions triggered by an FLR */ 1502 if (!test_bit(qid, vf->txq_mask)) 1503 return; 1504 1505 __clear_bit(qid, vf->txq_mask); 1506 --vf->txq_count; 1507 1508 if (efx_vfdi_flush_wake(vf)) 1509 wake_up(&vf->flush_waitq); 1510} 1511 1512void efx_siena_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event) 1513{ 1514 struct siena_vf *vf; 1515 unsigned ev_failed, queue, qid; 1516 1517 queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 1518 ev_failed = EFX_QWORD_FIELD(*event, 1519 FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 1520 if (map_vi_index(efx, queue, &vf, &qid)) 1521 return; 1522 if (!test_bit(qid, vf->rxq_mask)) 1523 return; 1524 1525 if (ev_failed) { 1526 set_bit(qid, vf->rxq_retry_mask); 1527 atomic_inc(&vf->rxq_retry_count); 1528 } else { 1529 __clear_bit(qid, vf->rxq_mask); 1530 --vf->rxq_count; 1531 } 1532 if (efx_vfdi_flush_wake(vf)) 1533 wake_up(&vf->flush_waitq); 1534} 1535 1536/* Called from napi. Schedule the reset work item */ 1537void efx_siena_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) 1538{ 1539 struct siena_vf *vf; 1540 unsigned int rel; 1541 1542 if (map_vi_index(efx, dmaq, &vf, &rel)) 1543 return; 1544 1545 if (net_ratelimit()) 1546 netif_err(efx, hw, efx->net_dev, 1547 "VF %d DMA Q %d reports descriptor fetch error.\n", 1548 vf->index, rel); 1549 queue_work(vfdi_workqueue, &vf->reset_work); 1550} 1551 1552/* Reset all VFs */ 1553void efx_siena_sriov_reset(struct efx_nic *efx) 1554{ 1555 struct siena_nic_data *nic_data = efx->nic_data; 1556 unsigned int vf_i; 1557 struct efx_buffer buf; 1558 struct siena_vf *vf; 1559 1560 ASSERT_RTNL(); 1561 1562 if (efx->vf_init_count == 0) 1563 return; 1564 1565 efx_siena_sriov_usrev(efx, true); 1566 (void)efx_siena_sriov_cmd(efx, true, NULL, NULL); 1567 1568 if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) 1569 return; 1570 1571 for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) { 1572 vf = nic_data->vf + vf_i; 1573 efx_siena_sriov_reset_vf(vf, &buf); 1574 } 1575 1576 efx_nic_free_buffer(efx, &buf); 1577} 1578 1579int efx_init_sriov(void) 1580{ 1581 /* A single threaded workqueue is sufficient. efx_siena_sriov_vfdi() and 1582 * efx_siena_sriov_peer_work() spend almost all their time sleeping for 1583 * MCDI to complete anyway 1584 */ 1585 vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi"); 1586 if (!vfdi_workqueue) 1587 return -ENOMEM; 1588 return 0; 1589} 1590 1591void efx_fini_sriov(void) 1592{ 1593 destroy_workqueue(vfdi_workqueue); 1594} 1595 1596int efx_siena_sriov_set_vf_mac(struct efx_nic *efx, int vf_i, u8 *mac) 1597{ 1598 struct siena_nic_data *nic_data = efx->nic_data; 1599 struct siena_vf *vf; 1600 1601 if (vf_i >= efx->vf_init_count) 1602 return -EINVAL; 1603 vf = nic_data->vf + vf_i; 1604 1605 mutex_lock(&vf->status_lock); 1606 ether_addr_copy(vf->addr.mac_addr, mac); 1607 __efx_siena_sriov_update_vf_addr(vf); 1608 mutex_unlock(&vf->status_lock); 1609 1610 return 0; 1611} 1612 1613int efx_siena_sriov_set_vf_vlan(struct efx_nic *efx, int vf_i, 1614 u16 vlan, u8 qos) 1615{ 1616 struct siena_nic_data *nic_data = efx->nic_data; 1617 struct siena_vf *vf; 1618 u16 tci; 1619 1620 if (vf_i >= efx->vf_init_count) 1621 return -EINVAL; 1622 vf = nic_data->vf + vf_i; 1623 1624 mutex_lock(&vf->status_lock); 1625 tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT); 1626 vf->addr.tci = htons(tci); 1627 __efx_siena_sriov_update_vf_addr(vf); 1628 mutex_unlock(&vf->status_lock); 1629 1630 return 0; 1631} 1632 1633int efx_siena_sriov_set_vf_spoofchk(struct efx_nic *efx, int vf_i, 1634 bool spoofchk) 1635{ 1636 struct siena_nic_data *nic_data = efx->nic_data; 1637 struct siena_vf *vf; 1638 int rc; 1639 1640 if (vf_i >= efx->vf_init_count) 1641 return -EINVAL; 1642 vf = nic_data->vf + vf_i; 1643 1644 mutex_lock(&vf->txq_lock); 1645 if (vf->txq_count == 0) { 1646 vf->tx_filter_mode = 1647 spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF; 1648 rc = 0; 1649 } else { 1650 /* This cannot be changed while TX queues are running */ 1651 rc = -EBUSY; 1652 } 1653 mutex_unlock(&vf->txq_lock); 1654 return rc; 1655} 1656 1657int efx_siena_sriov_get_vf_config(struct efx_nic *efx, int vf_i, 1658 struct ifla_vf_info *ivi) 1659{ 1660 struct siena_nic_data *nic_data = efx->nic_data; 1661 struct siena_vf *vf; 1662 u16 tci; 1663 1664 if (vf_i >= efx->vf_init_count) 1665 return -EINVAL; 1666 vf = nic_data->vf + vf_i; 1667 1668 ivi->vf = vf_i; 1669 ether_addr_copy(ivi->mac, vf->addr.mac_addr); 1670 ivi->max_tx_rate = 0; 1671 ivi->min_tx_rate = 0; 1672 tci = ntohs(vf->addr.tci); 1673 ivi->vlan = tci & VLAN_VID_MASK; 1674 ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7; 1675 ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON; 1676 1677 return 0; 1678} 1679 1680bool efx_siena_sriov_wanted(struct efx_nic *efx) 1681{ 1682 return efx->vf_count != 0; 1683} 1684 1685int efx_siena_sriov_configure(struct efx_nic *efx, int num_vfs) 1686{ 1687 return 0; 1688} 1689