1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10#include "net_driver.h" 11#include "ef10_regs.h" 12#include "io.h" 13#include "mcdi.h" 14#include "mcdi_pcol.h" 15#include "nic.h" 16#include "workarounds.h" 17#include "selftest.h" 18#include "ef10_sriov.h" 19#include <linux/in.h> 20#include <linux/jhash.h> 21#include <linux/wait.h> 22#include <linux/workqueue.h> 23 24/* Hardware control for EF10 architecture including 'Huntington'. */ 25 26#define EFX_EF10_DRVGEN_EV 7 27enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30}; 31 32/* The reserved RSS context value */ 33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34/* The maximum size of a shared RSS context */ 35/* TODO: this should really be from the mcdi protocol export */ 36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38/* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50#define HUNT_FILTER_TBL_ROWS 8192 51 52#define EFX_EF10_FILTER_ID_INVALID 0xffff 53struct efx_ef10_dev_addr { 54 u8 addr[ETH_ALEN]; 55 u16 id; 56}; 57 58struct efx_ef10_filter_table { 59/* The RX match field masks supported by this fw & hw, in order of priority */ 60 enum efx_filter_match_flags rx_match_flags[ 61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 62 unsigned int rx_match_count; 63 64 struct { 65 unsigned long spec; /* pointer to spec plus flag bits */ 66/* BUSY flag indicates that an update is in progress. AUTO_OLD is 67 * used to mark and sweep MAC filters for the device address lists. 68 */ 69#define EFX_EF10_FILTER_FLAG_BUSY 1UL 70#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 71#define EFX_EF10_FILTER_FLAGS 3UL 72 u64 handle; /* firmware handle */ 73 } *entry; 74 wait_queue_head_t waitq; 75/* Shadow of net_device address lists, guarded by mac_lock */ 76#define EFX_EF10_FILTER_DEV_UC_MAX 32 77#define EFX_EF10_FILTER_DEV_MC_MAX 256 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX]; 79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 80 int dev_uc_count; 81 int dev_mc_count; 82/* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */ 83 u16 ucdef_id; 84 u16 bcast_id; 85 u16 mcdef_id; 86}; 87 88/* An arbitrary search limit for the software hash table */ 89#define EFX_EF10_FILTER_SEARCH_LIMIT 200 90 91static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 92static void efx_ef10_filter_table_remove(struct efx_nic *efx); 93 94static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 95{ 96 efx_dword_t reg; 97 98 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 101} 102 103static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 104{ 105 int bar; 106 107 bar = efx->type->mem_bar; 108 return resource_size(&efx->pci_dev->resource[bar]); 109} 110 111static bool efx_ef10_is_vf(struct efx_nic *efx) 112{ 113 return efx->type->is_vf; 114} 115 116static int efx_ef10_get_pf_index(struct efx_nic *efx) 117{ 118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 119 struct efx_ef10_nic_data *nic_data = efx->nic_data; 120 size_t outlen; 121 int rc; 122 123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 124 sizeof(outbuf), &outlen); 125 if (rc) 126 return rc; 127 if (outlen < sizeof(outbuf)) 128 return -EIO; 129 130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 131 return 0; 132} 133 134#ifdef CONFIG_SFC_SRIOV 135static int efx_ef10_get_vf_index(struct efx_nic *efx) 136{ 137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 138 struct efx_ef10_nic_data *nic_data = efx->nic_data; 139 size_t outlen; 140 int rc; 141 142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 143 sizeof(outbuf), &outlen); 144 if (rc) 145 return rc; 146 if (outlen < sizeof(outbuf)) 147 return -EIO; 148 149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 150 return 0; 151} 152#endif 153 154static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 155{ 156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 157 struct efx_ef10_nic_data *nic_data = efx->nic_data; 158 size_t outlen; 159 int rc; 160 161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 162 163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 164 outbuf, sizeof(outbuf), &outlen); 165 if (rc) 166 return rc; 167 if (outlen < sizeof(outbuf)) { 168 netif_err(efx, drv, efx->net_dev, 169 "unable to read datapath firmware capabilities\n"); 170 return -EIO; 171 } 172 173 nic_data->datapath_caps = 174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 175 176 /* record the DPCPU firmware IDs to determine VEB vswitching support. 177 */ 178 nic_data->rx_dpcpu_fw_id = 179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 180 nic_data->tx_dpcpu_fw_id = 181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 182 183 if (!(nic_data->datapath_caps & 184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { 185 netif_err(efx, drv, efx->net_dev, 186 "current firmware does not support TSO\n"); 187 return -ENODEV; 188 } 189 190 if (!(nic_data->datapath_caps & 191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 192 netif_err(efx, probe, efx->net_dev, 193 "current firmware does not support an RX prefix\n"); 194 return -ENODEV; 195 } 196 197 return 0; 198} 199 200static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 201{ 202 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 203 int rc; 204 205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 206 outbuf, sizeof(outbuf), NULL); 207 if (rc) 208 return rc; 209 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 210 return rc > 0 ? rc : -ERANGE; 211} 212 213static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 214{ 215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 216 size_t outlen; 217 int rc; 218 219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 220 221 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 222 outbuf, sizeof(outbuf), &outlen); 223 if (rc) 224 return rc; 225 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 226 return -EIO; 227 228 ether_addr_copy(mac_address, 229 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 230 return 0; 231} 232 233static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 234{ 235 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 236 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 237 size_t outlen; 238 int num_addrs, rc; 239 240 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 241 EVB_PORT_ID_ASSIGNED); 242 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 243 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 244 245 if (rc) 246 return rc; 247 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 248 return -EIO; 249 250 num_addrs = MCDI_DWORD(outbuf, 251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 252 253 WARN_ON(num_addrs != 1); 254 255 ether_addr_copy(mac_address, 256 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 257 258 return 0; 259} 260 261static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 262 struct device_attribute *attr, 263 char *buf) 264{ 265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 266 267 return sprintf(buf, "%d\n", 268 ((efx->mcdi->fn_flags) & 269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 270 ? 1 : 0); 271} 272 273static ssize_t efx_ef10_show_primary_flag(struct device *dev, 274 struct device_attribute *attr, 275 char *buf) 276{ 277 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 278 279 return sprintf(buf, "%d\n", 280 ((efx->mcdi->fn_flags) & 281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 282 ? 1 : 0); 283} 284 285static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 286 NULL); 287static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 288 289static int efx_ef10_probe(struct efx_nic *efx) 290{ 291 struct efx_ef10_nic_data *nic_data; 292 struct net_device *net_dev = efx->net_dev; 293 int i, rc; 294 295 /* We can have one VI for each 8K region. However, until we 296 * use TX option descriptors we need two TX queues per channel. 297 */ 298 efx->max_channels = min_t(unsigned int, 299 EFX_MAX_CHANNELS, 300 efx_ef10_mem_map_size(efx) / 301 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 302 efx->max_tx_channels = efx->max_channels; 303 if (WARN_ON(efx->max_channels == 0)) 304 return -EIO; 305 306 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 307 if (!nic_data) 308 return -ENOMEM; 309 efx->nic_data = nic_data; 310 311 /* we assume later that we can copy from this buffer in dwords */ 312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 313 314 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 315 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 316 if (rc) 317 goto fail1; 318 319 /* Get the MC's warm boot count. In case it's rebooting right 320 * now, be prepared to retry. 321 */ 322 i = 0; 323 for (;;) { 324 rc = efx_ef10_get_warm_boot_count(efx); 325 if (rc >= 0) 326 break; 327 if (++i == 5) 328 goto fail2; 329 ssleep(1); 330 } 331 nic_data->warm_boot_count = rc; 332 333 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 334 335 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 336 337 /* In case we're recovering from a crash (kexec), we want to 338 * cancel any outstanding request by the previous user of this 339 * function. We send a special message using the least 340 * significant bits of the 'high' (doorbell) register. 341 */ 342 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 343 344 rc = efx_mcdi_init(efx); 345 if (rc) 346 goto fail2; 347 348 /* Reset (most) configuration for this function */ 349 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 350 if (rc) 351 goto fail3; 352 353 /* Enable event logging */ 354 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 355 if (rc) 356 goto fail3; 357 358 rc = device_create_file(&efx->pci_dev->dev, 359 &dev_attr_link_control_flag); 360 if (rc) 361 goto fail3; 362 363 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 364 if (rc) 365 goto fail4; 366 367 rc = efx_ef10_get_pf_index(efx); 368 if (rc) 369 goto fail5; 370 371 rc = efx_ef10_init_datapath_caps(efx); 372 if (rc < 0) 373 goto fail5; 374 375 efx->rx_packet_len_offset = 376 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 377 378 rc = efx_mcdi_port_get_number(efx); 379 if (rc < 0) 380 goto fail5; 381 efx->port_num = rc; 382 net_dev->dev_port = rc; 383 384 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 385 if (rc) 386 goto fail5; 387 388 rc = efx_ef10_get_sysclk_freq(efx); 389 if (rc < 0) 390 goto fail5; 391 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 392 393 /* Check whether firmware supports bug 35388 workaround. 394 * First try to enable it, then if we get EPERM, just 395 * ask if it's already enabled 396 */ 397 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL); 398 if (rc == 0) { 399 nic_data->workaround_35388 = true; 400 } else if (rc == -EPERM) { 401 unsigned int enabled; 402 403 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled); 404 if (rc) 405 goto fail3; 406 nic_data->workaround_35388 = enabled & 407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388; 408 } else if (rc != -ENOSYS && rc != -ENOENT) { 409 goto fail5; 410 } 411 netif_dbg(efx, probe, efx->net_dev, 412 "workaround for bug 35388 is %sabled\n", 413 nic_data->workaround_35388 ? "en" : "dis"); 414 415 rc = efx_mcdi_mon_probe(efx); 416 if (rc && rc != -EPERM) 417 goto fail5; 418 419 efx_ptp_probe(efx, NULL); 420 421#ifdef CONFIG_SFC_SRIOV 422 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 423 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 424 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 425 426 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 427 } else 428#endif 429 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 430 431 return 0; 432 433fail5: 434 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 435fail4: 436 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 437fail3: 438 efx_mcdi_fini(efx); 439fail2: 440 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 441fail1: 442 kfree(nic_data); 443 efx->nic_data = NULL; 444 return rc; 445} 446 447static int efx_ef10_free_vis(struct efx_nic *efx) 448{ 449 MCDI_DECLARE_BUF_ERR(outbuf); 450 size_t outlen; 451 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 452 outbuf, sizeof(outbuf), &outlen); 453 454 /* -EALREADY means nothing to free, so ignore */ 455 if (rc == -EALREADY) 456 rc = 0; 457 if (rc) 458 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 459 rc); 460 return rc; 461} 462 463#ifdef EFX_USE_PIO 464 465static void efx_ef10_free_piobufs(struct efx_nic *efx) 466{ 467 struct efx_ef10_nic_data *nic_data = efx->nic_data; 468 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 469 unsigned int i; 470 int rc; 471 472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 473 474 for (i = 0; i < nic_data->n_piobufs; i++) { 475 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 476 nic_data->piobuf_handle[i]); 477 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 478 NULL, 0, NULL); 479 WARN_ON(rc); 480 } 481 482 nic_data->n_piobufs = 0; 483} 484 485static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 486{ 487 struct efx_ef10_nic_data *nic_data = efx->nic_data; 488 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 489 unsigned int i; 490 size_t outlen; 491 int rc = 0; 492 493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 494 495 for (i = 0; i < n; i++) { 496 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 497 outbuf, sizeof(outbuf), &outlen); 498 if (rc) 499 break; 500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 501 rc = -EIO; 502 break; 503 } 504 nic_data->piobuf_handle[i] = 505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 506 netif_dbg(efx, probe, efx->net_dev, 507 "allocated PIO buffer %u handle %x\n", i, 508 nic_data->piobuf_handle[i]); 509 } 510 511 nic_data->n_piobufs = i; 512 if (rc) 513 efx_ef10_free_piobufs(efx); 514 return rc; 515} 516 517static int efx_ef10_link_piobufs(struct efx_nic *efx) 518{ 519 struct efx_ef10_nic_data *nic_data = efx->nic_data; 520 _MCDI_DECLARE_BUF(inbuf, 521 max(MC_CMD_LINK_PIOBUF_IN_LEN, 522 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 523 struct efx_channel *channel; 524 struct efx_tx_queue *tx_queue; 525 unsigned int offset, index; 526 int rc; 527 528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 530 531 memset(inbuf, 0, sizeof(inbuf)); 532 533 /* Link a buffer to each VI in the write-combining mapping */ 534 for (index = 0; index < nic_data->n_piobufs; ++index) { 535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 536 nic_data->piobuf_handle[index]); 537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 538 nic_data->pio_write_vi_base + index); 539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 541 NULL, 0, NULL); 542 if (rc) { 543 netif_err(efx, drv, efx->net_dev, 544 "failed to link VI %u to PIO buffer %u (%d)\n", 545 nic_data->pio_write_vi_base + index, index, 546 rc); 547 goto fail; 548 } 549 netif_dbg(efx, probe, efx->net_dev, 550 "linked VI %u to PIO buffer %u\n", 551 nic_data->pio_write_vi_base + index, index); 552 } 553 554 /* Link a buffer to each TX queue */ 555 efx_for_each_channel(channel, efx) { 556 efx_for_each_channel_tx_queue(tx_queue, channel) { 557 /* We assign the PIO buffers to queues in 558 * reverse order to allow for the following 559 * special case. 560 */ 561 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 562 tx_queue->channel->channel - 1) * 563 efx_piobuf_size); 564 index = offset / ER_DZ_TX_PIOBUF_SIZE; 565 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 566 567 /* When the host page size is 4K, the first 568 * host page in the WC mapping may be within 569 * the same VI page as the last TX queue. We 570 * can only link one buffer to each VI. 571 */ 572 if (tx_queue->queue == nic_data->pio_write_vi_base) { 573 BUG_ON(index != 0); 574 rc = 0; 575 } else { 576 MCDI_SET_DWORD(inbuf, 577 LINK_PIOBUF_IN_PIOBUF_HANDLE, 578 nic_data->piobuf_handle[index]); 579 MCDI_SET_DWORD(inbuf, 580 LINK_PIOBUF_IN_TXQ_INSTANCE, 581 tx_queue->queue); 582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 584 NULL, 0, NULL); 585 } 586 587 if (rc) { 588 /* This is non-fatal; the TX path just 589 * won't use PIO for this queue 590 */ 591 netif_err(efx, drv, efx->net_dev, 592 "failed to link VI %u to PIO buffer %u (%d)\n", 593 tx_queue->queue, index, rc); 594 tx_queue->piobuf = NULL; 595 } else { 596 tx_queue->piobuf = 597 nic_data->pio_write_base + 598 index * EFX_VI_PAGE_SIZE + offset; 599 tx_queue->piobuf_offset = offset; 600 netif_dbg(efx, probe, efx->net_dev, 601 "linked VI %u to PIO buffer %u offset %x addr %p\n", 602 tx_queue->queue, index, 603 tx_queue->piobuf_offset, 604 tx_queue->piobuf); 605 } 606 } 607 } 608 609 return 0; 610 611fail: 612 while (index--) { 613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 614 nic_data->pio_write_vi_base + index); 615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 617 NULL, 0, NULL); 618 } 619 return rc; 620} 621 622static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 623{ 624 struct efx_channel *channel; 625 struct efx_tx_queue *tx_queue; 626 627 /* All our existing PIO buffers went away */ 628 efx_for_each_channel(channel, efx) 629 efx_for_each_channel_tx_queue(tx_queue, channel) 630 tx_queue->piobuf = NULL; 631} 632 633#else /* !EFX_USE_PIO */ 634 635static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 636{ 637 return n == 0 ? 0 : -ENOBUFS; 638} 639 640static int efx_ef10_link_piobufs(struct efx_nic *efx) 641{ 642 return 0; 643} 644 645static void efx_ef10_free_piobufs(struct efx_nic *efx) 646{ 647} 648 649static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 650{ 651} 652 653#endif /* EFX_USE_PIO */ 654 655static void efx_ef10_remove(struct efx_nic *efx) 656{ 657 struct efx_ef10_nic_data *nic_data = efx->nic_data; 658 int rc; 659 660#ifdef CONFIG_SFC_SRIOV 661 struct efx_ef10_nic_data *nic_data_pf; 662 struct pci_dev *pci_dev_pf; 663 struct efx_nic *efx_pf; 664 struct ef10_vf *vf; 665 666 if (efx->pci_dev->is_virtfn) { 667 pci_dev_pf = efx->pci_dev->physfn; 668 if (pci_dev_pf) { 669 efx_pf = pci_get_drvdata(pci_dev_pf); 670 nic_data_pf = efx_pf->nic_data; 671 vf = nic_data_pf->vf + nic_data->vf_index; 672 vf->efx = NULL; 673 } else 674 netif_info(efx, drv, efx->net_dev, 675 "Could not get the PF id from VF\n"); 676 } 677#endif 678 679 efx_ptp_remove(efx); 680 681 efx_mcdi_mon_remove(efx); 682 683 efx_ef10_rx_free_indir_table(efx); 684 685 if (nic_data->wc_membase) 686 iounmap(nic_data->wc_membase); 687 688 rc = efx_ef10_free_vis(efx); 689 WARN_ON(rc != 0); 690 691 if (!nic_data->must_restore_piobufs) 692 efx_ef10_free_piobufs(efx); 693 694 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 696 697 efx_mcdi_fini(efx); 698 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 699 kfree(nic_data); 700} 701 702static int efx_ef10_probe_pf(struct efx_nic *efx) 703{ 704 return efx_ef10_probe(efx); 705} 706 707int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 708{ 709 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 710 711 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 712 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 713 NULL, 0, NULL); 714} 715 716int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 717{ 718 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 719 720 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 721 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 722 NULL, 0, NULL); 723} 724 725int efx_ef10_vport_add_mac(struct efx_nic *efx, 726 unsigned int port_id, u8 *mac) 727{ 728 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 729 730 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 731 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 732 733 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 734 sizeof(inbuf), NULL, 0, NULL); 735} 736 737int efx_ef10_vport_del_mac(struct efx_nic *efx, 738 unsigned int port_id, u8 *mac) 739{ 740 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 741 742 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 743 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 744 745 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 746 sizeof(inbuf), NULL, 0, NULL); 747} 748 749#ifdef CONFIG_SFC_SRIOV 750static int efx_ef10_probe_vf(struct efx_nic *efx) 751{ 752 int rc; 753 struct pci_dev *pci_dev_pf; 754 755 /* If the parent PF has no VF data structure, it doesn't know about this 756 * VF so fail probe. The VF needs to be re-created. This can happen 757 * if the PF driver is unloaded while the VF is assigned to a guest. 758 */ 759 pci_dev_pf = efx->pci_dev->physfn; 760 if (pci_dev_pf) { 761 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 762 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 763 764 if (!nic_data_pf->vf) { 765 netif_info(efx, drv, efx->net_dev, 766 "The VF cannot link to its parent PF; " 767 "please destroy and re-create the VF\n"); 768 return -EBUSY; 769 } 770 } 771 772 rc = efx_ef10_probe(efx); 773 if (rc) 774 return rc; 775 776 rc = efx_ef10_get_vf_index(efx); 777 if (rc) 778 goto fail; 779 780 if (efx->pci_dev->is_virtfn) { 781 if (efx->pci_dev->physfn) { 782 struct efx_nic *efx_pf = 783 pci_get_drvdata(efx->pci_dev->physfn); 784 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 785 struct efx_ef10_nic_data *nic_data = efx->nic_data; 786 787 nic_data_p->vf[nic_data->vf_index].efx = efx; 788 nic_data_p->vf[nic_data->vf_index].pci_dev = 789 efx->pci_dev; 790 } else 791 netif_info(efx, drv, efx->net_dev, 792 "Could not get the PF id from VF\n"); 793 } 794 795 return 0; 796 797fail: 798 efx_ef10_remove(efx); 799 return rc; 800} 801#else 802static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 803{ 804 return 0; 805} 806#endif 807 808static int efx_ef10_alloc_vis(struct efx_nic *efx, 809 unsigned int min_vis, unsigned int max_vis) 810{ 811 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 812 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 813 struct efx_ef10_nic_data *nic_data = efx->nic_data; 814 size_t outlen; 815 int rc; 816 817 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 818 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 819 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 820 outbuf, sizeof(outbuf), &outlen); 821 if (rc != 0) 822 return rc; 823 824 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 825 return -EIO; 826 827 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 828 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 829 830 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 831 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 832 return 0; 833} 834 835/* Note that the failure path of this function does not free 836 * resources, as this will be done by efx_ef10_remove(). 837 */ 838static int efx_ef10_dimension_resources(struct efx_nic *efx) 839{ 840 struct efx_ef10_nic_data *nic_data = efx->nic_data; 841 unsigned int uc_mem_map_size, wc_mem_map_size; 842 unsigned int min_vis = max(EFX_TXQ_TYPES, 843 efx_separate_tx_channels ? 2 : 1); 844 unsigned int channel_vis, pio_write_vi_base, max_vis; 845 void __iomem *membase; 846 int rc; 847 848 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 849 850#ifdef EFX_USE_PIO 851 /* Try to allocate PIO buffers if wanted and if the full 852 * number of PIO buffers would be sufficient to allocate one 853 * copy-buffer per TX channel. Failure is non-fatal, as there 854 * are only a small number of PIO buffers shared between all 855 * functions of the controller. 856 */ 857 if (efx_piobuf_size != 0 && 858 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 859 efx->n_tx_channels) { 860 unsigned int n_piobufs = 861 DIV_ROUND_UP(efx->n_tx_channels, 862 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 863 864 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 865 if (rc) 866 netif_err(efx, probe, efx->net_dev, 867 "failed to allocate PIO buffers (%d)\n", rc); 868 else 869 netif_dbg(efx, probe, efx->net_dev, 870 "allocated %u PIO buffers\n", n_piobufs); 871 } 872#else 873 nic_data->n_piobufs = 0; 874#endif 875 876 /* PIO buffers should be mapped with write-combining enabled, 877 * and we want to make single UC and WC mappings rather than 878 * several of each (in fact that's the only option if host 879 * page size is >4K). So we may allocate some extra VIs just 880 * for writing PIO buffers through. 881 * 882 * The UC mapping contains (channel_vis - 1) complete VIs and the 883 * first half of the next VI. Then the WC mapping begins with 884 * the second half of this last VI. 885 */ 886 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE + 887 ER_DZ_TX_PIOBUF); 888 if (nic_data->n_piobufs) { 889 /* pio_write_vi_base rounds down to give the number of complete 890 * VIs inside the UC mapping. 891 */ 892 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 893 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 894 nic_data->n_piobufs) * 895 EFX_VI_PAGE_SIZE) - 896 uc_mem_map_size); 897 max_vis = pio_write_vi_base + nic_data->n_piobufs; 898 } else { 899 pio_write_vi_base = 0; 900 wc_mem_map_size = 0; 901 max_vis = channel_vis; 902 } 903 904 /* In case the last attached driver failed to free VIs, do it now */ 905 rc = efx_ef10_free_vis(efx); 906 if (rc != 0) 907 return rc; 908 909 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 910 if (rc != 0) 911 return rc; 912 913 if (nic_data->n_allocated_vis < channel_vis) { 914 netif_info(efx, drv, efx->net_dev, 915 "Could not allocate enough VIs to satisfy RSS" 916 " requirements. Performance may not be optimal.\n"); 917 /* We didn't get the VIs to populate our channels. 918 * We could keep what we got but then we'd have more 919 * interrupts than we need. 920 * Instead calculate new max_channels and restart 921 */ 922 efx->max_channels = nic_data->n_allocated_vis; 923 efx->max_tx_channels = 924 nic_data->n_allocated_vis / EFX_TXQ_TYPES; 925 926 efx_ef10_free_vis(efx); 927 return -EAGAIN; 928 } 929 930 /* If we didn't get enough VIs to map all the PIO buffers, free the 931 * PIO buffers 932 */ 933 if (nic_data->n_piobufs && 934 nic_data->n_allocated_vis < 935 pio_write_vi_base + nic_data->n_piobufs) { 936 netif_dbg(efx, probe, efx->net_dev, 937 "%u VIs are not sufficient to map %u PIO buffers\n", 938 nic_data->n_allocated_vis, nic_data->n_piobufs); 939 efx_ef10_free_piobufs(efx); 940 } 941 942 /* Shrink the original UC mapping of the memory BAR */ 943 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 944 if (!membase) { 945 netif_err(efx, probe, efx->net_dev, 946 "could not shrink memory BAR to %x\n", 947 uc_mem_map_size); 948 return -ENOMEM; 949 } 950 iounmap(efx->membase); 951 efx->membase = membase; 952 953 /* Set up the WC mapping if needed */ 954 if (wc_mem_map_size) { 955 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 956 uc_mem_map_size, 957 wc_mem_map_size); 958 if (!nic_data->wc_membase) { 959 netif_err(efx, probe, efx->net_dev, 960 "could not allocate WC mapping of size %x\n", 961 wc_mem_map_size); 962 return -ENOMEM; 963 } 964 nic_data->pio_write_vi_base = pio_write_vi_base; 965 nic_data->pio_write_base = 966 nic_data->wc_membase + 967 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 968 uc_mem_map_size); 969 970 rc = efx_ef10_link_piobufs(efx); 971 if (rc) 972 efx_ef10_free_piobufs(efx); 973 } 974 975 netif_dbg(efx, probe, efx->net_dev, 976 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 977 &efx->membase_phys, efx->membase, uc_mem_map_size, 978 nic_data->wc_membase, wc_mem_map_size); 979 980 return 0; 981} 982 983static int efx_ef10_init_nic(struct efx_nic *efx) 984{ 985 struct efx_ef10_nic_data *nic_data = efx->nic_data; 986 int rc; 987 988 if (nic_data->must_check_datapath_caps) { 989 rc = efx_ef10_init_datapath_caps(efx); 990 if (rc) 991 return rc; 992 nic_data->must_check_datapath_caps = false; 993 } 994 995 if (nic_data->must_realloc_vis) { 996 /* We cannot let the number of VIs change now */ 997 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 998 nic_data->n_allocated_vis); 999 if (rc) 1000 return rc; 1001 nic_data->must_realloc_vis = false; 1002 } 1003 1004 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1005 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1006 if (rc == 0) { 1007 rc = efx_ef10_link_piobufs(efx); 1008 if (rc) 1009 efx_ef10_free_piobufs(efx); 1010 } 1011 1012 /* Log an error on failure, but this is non-fatal */ 1013 if (rc) 1014 netif_err(efx, drv, efx->net_dev, 1015 "failed to restore PIO buffers (%d)\n", rc); 1016 nic_data->must_restore_piobufs = false; 1017 } 1018 1019 /* don't fail init if RSS setup doesn't work */ 1020 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 1021 1022 return 0; 1023} 1024 1025static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 1026{ 1027 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1028#ifdef CONFIG_SFC_SRIOV 1029 unsigned int i; 1030#endif 1031 1032 /* All our allocations have been reset */ 1033 nic_data->must_realloc_vis = true; 1034 nic_data->must_restore_filters = true; 1035 nic_data->must_restore_piobufs = true; 1036 efx_ef10_forget_old_piobufs(efx); 1037 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1038 1039 /* Driver-created vswitches and vports must be re-created */ 1040 nic_data->must_probe_vswitching = true; 1041 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1042#ifdef CONFIG_SFC_SRIOV 1043 if (nic_data->vf) 1044 for (i = 0; i < efx->vf_count; i++) 1045 nic_data->vf[i].vport_id = 0; 1046#endif 1047} 1048 1049static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1050{ 1051 if (reason == RESET_TYPE_MC_FAILURE) 1052 return RESET_TYPE_DATAPATH; 1053 1054 return efx_mcdi_map_reset_reason(reason); 1055} 1056 1057static int efx_ef10_map_reset_flags(u32 *flags) 1058{ 1059 enum { 1060 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1061 ETH_RESET_SHARED_SHIFT), 1062 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1063 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1064 ETH_RESET_PHY | ETH_RESET_MGMT) << 1065 ETH_RESET_SHARED_SHIFT) 1066 }; 1067 1068 /* We assume for now that our PCI function is permitted to 1069 * reset everything. 1070 */ 1071 1072 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1073 *flags &= ~EF10_RESET_MC; 1074 return RESET_TYPE_WORLD; 1075 } 1076 1077 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1078 *flags &= ~EF10_RESET_PORT; 1079 return RESET_TYPE_ALL; 1080 } 1081 1082 /* no invisible reset implemented */ 1083 1084 return -EINVAL; 1085} 1086 1087static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1088{ 1089 int rc = efx_mcdi_reset(efx, reset_type); 1090 1091 /* Unprivileged functions return -EPERM, but need to return success 1092 * here so that the datapath is brought back up. 1093 */ 1094 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1095 rc = 0; 1096 1097 /* If it was a port reset, trigger reallocation of MC resources. 1098 * Note that on an MC reset nothing needs to be done now because we'll 1099 * detect the MC reset later and handle it then. 1100 * For an FLR, we never get an MC reset event, but the MC has reset all 1101 * resources assigned to us, so we have to trigger reallocation now. 1102 */ 1103 if ((reset_type == RESET_TYPE_ALL || 1104 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1105 efx_ef10_reset_mc_allocations(efx); 1106 return rc; 1107} 1108 1109#define EF10_DMA_STAT(ext_name, mcdi_name) \ 1110 [EF10_STAT_ ## ext_name] = \ 1111 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1112#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1113 [EF10_STAT_ ## int_name] = \ 1114 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1115#define EF10_OTHER_STAT(ext_name) \ 1116 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1117#define GENERIC_SW_STAT(ext_name) \ 1118 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1119 1120static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1121 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1122 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1123 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1124 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1125 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1126 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1127 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1128 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1129 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1130 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1131 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1132 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1133 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1134 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1135 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1136 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1137 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1138 EF10_OTHER_STAT(port_rx_good_bytes), 1139 EF10_OTHER_STAT(port_rx_bad_bytes), 1140 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1141 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1142 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1143 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1144 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1145 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1146 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1147 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1148 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1149 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1150 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1151 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1152 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1153 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1154 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1155 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1156 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1157 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1158 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1159 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1160 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1161 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1162 GENERIC_SW_STAT(rx_nodesc_trunc), 1163 GENERIC_SW_STAT(rx_noskb_drops), 1164 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1165 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1166 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1167 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1168 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1169 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1170 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1171 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1172 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1173 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1174 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1175 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1176 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1177 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1178 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1179 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1180 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1181 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1182 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1183 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1184 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1185 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1186 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1187 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1188 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1189 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1190 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1191 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1192 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1193 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1194}; 1195 1196#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1197 (1ULL << EF10_STAT_port_tx_packets) | \ 1198 (1ULL << EF10_STAT_port_tx_pause) | \ 1199 (1ULL << EF10_STAT_port_tx_unicast) | \ 1200 (1ULL << EF10_STAT_port_tx_multicast) | \ 1201 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1202 (1ULL << EF10_STAT_port_rx_bytes) | \ 1203 (1ULL << \ 1204 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1205 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1206 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1207 (1ULL << EF10_STAT_port_rx_packets) | \ 1208 (1ULL << EF10_STAT_port_rx_good) | \ 1209 (1ULL << EF10_STAT_port_rx_bad) | \ 1210 (1ULL << EF10_STAT_port_rx_pause) | \ 1211 (1ULL << EF10_STAT_port_rx_control) | \ 1212 (1ULL << EF10_STAT_port_rx_unicast) | \ 1213 (1ULL << EF10_STAT_port_rx_multicast) | \ 1214 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1215 (1ULL << EF10_STAT_port_rx_lt64) | \ 1216 (1ULL << EF10_STAT_port_rx_64) | \ 1217 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1218 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1219 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1220 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1221 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1222 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1223 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1224 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1225 (1ULL << EF10_STAT_port_rx_overflow) | \ 1226 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1227 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1228 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1229 1230/* These statistics are only provided by the 10G MAC. For a 10G/40G 1231 * switchable port we do not expose these because they might not 1232 * include all the packets they should. 1233 */ 1234#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1235 (1ULL << EF10_STAT_port_tx_lt64) | \ 1236 (1ULL << EF10_STAT_port_tx_64) | \ 1237 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1238 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1239 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1240 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1241 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1242 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1243 1244/* These statistics are only provided by the 40G MAC. For a 10G/40G 1245 * switchable port we do expose these because the errors will otherwise 1246 * be silent. 1247 */ 1248#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1249 (1ULL << EF10_STAT_port_rx_length_error)) 1250 1251/* These statistics are only provided if the firmware supports the 1252 * capability PM_AND_RXDP_COUNTERS. 1253 */ 1254#define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1255 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1256 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1257 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1258 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1259 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1260 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1261 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1262 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1263 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1264 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1265 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1266 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1267 1268static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1269{ 1270 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1271 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1272 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1273 1274 if (!(efx->mcdi->fn_flags & 1275 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1276 return 0; 1277 1278 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 1279 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1280 else 1281 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1282 1283 if (nic_data->datapath_caps & 1284 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1285 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1286 1287 return raw_mask; 1288} 1289 1290static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1291{ 1292 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1293 u64 raw_mask[2]; 1294 1295 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1296 1297 /* Only show vadaptor stats when EVB capability is present */ 1298 if (nic_data->datapath_caps & 1299 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1300 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1301 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1302 } else { 1303 raw_mask[1] = 0; 1304 } 1305 1306#if BITS_PER_LONG == 64 1307 mask[0] = raw_mask[0]; 1308 mask[1] = raw_mask[1]; 1309#else 1310 mask[0] = raw_mask[0] & 0xffffffff; 1311 mask[1] = raw_mask[0] >> 32; 1312 mask[2] = raw_mask[1] & 0xffffffff; 1313 mask[3] = raw_mask[1] >> 32; 1314#endif 1315} 1316 1317static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1318{ 1319 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1320 1321 efx_ef10_get_stat_mask(efx, mask); 1322 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1323 mask, names); 1324} 1325 1326static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1327 struct rtnl_link_stats64 *core_stats) 1328{ 1329 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1330 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1331 u64 *stats = nic_data->stats; 1332 size_t stats_count = 0, index; 1333 1334 efx_ef10_get_stat_mask(efx, mask); 1335 1336 if (full_stats) { 1337 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1338 if (efx_ef10_stat_desc[index].name) { 1339 *full_stats++ = stats[index]; 1340 ++stats_count; 1341 } 1342 } 1343 } 1344 1345 if (!core_stats) 1346 return stats_count; 1347 1348 if (nic_data->datapath_caps & 1349 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1350 /* Use vadaptor stats. */ 1351 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1352 stats[EF10_STAT_rx_multicast] + 1353 stats[EF10_STAT_rx_broadcast]; 1354 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1355 stats[EF10_STAT_tx_multicast] + 1356 stats[EF10_STAT_tx_broadcast]; 1357 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1358 stats[EF10_STAT_rx_multicast_bytes] + 1359 stats[EF10_STAT_rx_broadcast_bytes]; 1360 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1361 stats[EF10_STAT_tx_multicast_bytes] + 1362 stats[EF10_STAT_tx_broadcast_bytes]; 1363 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1364 stats[GENERIC_STAT_rx_noskb_drops]; 1365 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1366 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1367 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1368 core_stats->rx_errors = core_stats->rx_crc_errors; 1369 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1370 } else { 1371 /* Use port stats. */ 1372 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1373 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1374 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1375 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1376 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1377 stats[GENERIC_STAT_rx_nodesc_trunc] + 1378 stats[GENERIC_STAT_rx_noskb_drops]; 1379 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1380 core_stats->rx_length_errors = 1381 stats[EF10_STAT_port_rx_gtjumbo] + 1382 stats[EF10_STAT_port_rx_length_error]; 1383 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1384 core_stats->rx_frame_errors = 1385 stats[EF10_STAT_port_rx_align_error]; 1386 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1387 core_stats->rx_errors = (core_stats->rx_length_errors + 1388 core_stats->rx_crc_errors + 1389 core_stats->rx_frame_errors); 1390 } 1391 1392 return stats_count; 1393} 1394 1395static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1396{ 1397 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1398 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1399 __le64 generation_start, generation_end; 1400 u64 *stats = nic_data->stats; 1401 __le64 *dma_stats; 1402 1403 efx_ef10_get_stat_mask(efx, mask); 1404 1405 dma_stats = efx->stats_buffer.addr; 1406 nic_data = efx->nic_data; 1407 1408 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1409 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1410 return 0; 1411 rmb(); 1412 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1413 stats, efx->stats_buffer.addr, false); 1414 rmb(); 1415 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1416 if (generation_end != generation_start) 1417 return -EAGAIN; 1418 1419 /* Update derived statistics */ 1420 efx_nic_fix_nodesc_drop_stat(efx, 1421 &stats[EF10_STAT_port_rx_nodesc_drops]); 1422 stats[EF10_STAT_port_rx_good_bytes] = 1423 stats[EF10_STAT_port_rx_bytes] - 1424 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1425 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1426 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1427 efx_update_sw_stats(efx, stats); 1428 return 0; 1429} 1430 1431 1432static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1433 struct rtnl_link_stats64 *core_stats) 1434{ 1435 int retry; 1436 1437 /* If we're unlucky enough to read statistics during the DMA, wait 1438 * up to 10ms for it to finish (typically takes <500us) 1439 */ 1440 for (retry = 0; retry < 100; ++retry) { 1441 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1442 break; 1443 udelay(100); 1444 } 1445 1446 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1447} 1448 1449static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1450{ 1451 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1452 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1453 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1454 __le64 generation_start, generation_end; 1455 u64 *stats = nic_data->stats; 1456 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1457 struct efx_buffer stats_buf; 1458 __le64 *dma_stats; 1459 int rc; 1460 1461 spin_unlock_bh(&efx->stats_lock); 1462 1463 if (in_interrupt()) { 1464 /* If in atomic context, cannot update stats. Just update the 1465 * software stats and return so the caller can continue. 1466 */ 1467 spin_lock_bh(&efx->stats_lock); 1468 efx_update_sw_stats(efx, stats); 1469 return 0; 1470 } 1471 1472 efx_ef10_get_stat_mask(efx, mask); 1473 1474 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1475 if (rc) { 1476 spin_lock_bh(&efx->stats_lock); 1477 return rc; 1478 } 1479 1480 dma_stats = stats_buf.addr; 1481 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1482 1483 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1484 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1485 MAC_STATS_IN_DMA, 1); 1486 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1487 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1488 1489 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1490 NULL, 0, NULL); 1491 spin_lock_bh(&efx->stats_lock); 1492 if (rc) { 1493 /* Expect ENOENT if DMA queues have not been set up */ 1494 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1495 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1496 sizeof(inbuf), NULL, 0, rc); 1497 goto out; 1498 } 1499 1500 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1501 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1502 WARN_ON_ONCE(1); 1503 goto out; 1504 } 1505 rmb(); 1506 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1507 stats, stats_buf.addr, false); 1508 rmb(); 1509 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1510 if (generation_end != generation_start) { 1511 rc = -EAGAIN; 1512 goto out; 1513 } 1514 1515 efx_update_sw_stats(efx, stats); 1516out: 1517 efx_nic_free_buffer(efx, &stats_buf); 1518 return rc; 1519} 1520 1521static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1522 struct rtnl_link_stats64 *core_stats) 1523{ 1524 if (efx_ef10_try_update_nic_stats_vf(efx)) 1525 return 0; 1526 1527 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1528} 1529 1530static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1531{ 1532 struct efx_nic *efx = channel->efx; 1533 unsigned int mode, value; 1534 efx_dword_t timer_cmd; 1535 1536 if (channel->irq_moderation) { 1537 mode = 3; 1538 value = channel->irq_moderation - 1; 1539 } else { 1540 mode = 0; 1541 value = 0; 1542 } 1543 1544 if (EFX_EF10_WORKAROUND_35388(efx)) { 1545 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1546 EFE_DD_EVQ_IND_TIMER_FLAGS, 1547 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1548 ERF_DD_EVQ_IND_TIMER_VAL, value); 1549 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1550 channel->channel); 1551 } else { 1552 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1553 ERF_DZ_TC_TIMER_VAL, value); 1554 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1555 channel->channel); 1556 } 1557} 1558 1559static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1560 struct ethtool_wolinfo *wol) {} 1561 1562static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1563{ 1564 return -EOPNOTSUPP; 1565} 1566 1567static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1568{ 1569 wol->supported = 0; 1570 wol->wolopts = 0; 1571 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1572} 1573 1574static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1575{ 1576 if (type != 0) 1577 return -EINVAL; 1578 return 0; 1579} 1580 1581static void efx_ef10_mcdi_request(struct efx_nic *efx, 1582 const efx_dword_t *hdr, size_t hdr_len, 1583 const efx_dword_t *sdu, size_t sdu_len) 1584{ 1585 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1586 u8 *pdu = nic_data->mcdi_buf.addr; 1587 1588 memcpy(pdu, hdr, hdr_len); 1589 memcpy(pdu + hdr_len, sdu, sdu_len); 1590 wmb(); 1591 1592 /* The hardware provides 'low' and 'high' (doorbell) registers 1593 * for passing the 64-bit address of an MCDI request to 1594 * firmware. However the dwords are swapped by firmware. The 1595 * least significant bits of the doorbell are then 0 for all 1596 * MCDI requests due to alignment. 1597 */ 1598 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1599 ER_DZ_MC_DB_LWRD); 1600 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1601 ER_DZ_MC_DB_HWRD); 1602} 1603 1604static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1605{ 1606 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1607 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1608 1609 rmb(); 1610 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1611} 1612 1613static void 1614efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1615 size_t offset, size_t outlen) 1616{ 1617 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1618 const u8 *pdu = nic_data->mcdi_buf.addr; 1619 1620 memcpy(outbuf, pdu + offset, outlen); 1621} 1622 1623static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 1624{ 1625 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1626 1627 /* All our allocations have been reset */ 1628 efx_ef10_reset_mc_allocations(efx); 1629 1630 /* The datapath firmware might have been changed */ 1631 nic_data->must_check_datapath_caps = true; 1632 1633 /* MAC statistics have been cleared on the NIC; clear the local 1634 * statistic that we update with efx_update_diff_stat(). 1635 */ 1636 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1637} 1638 1639static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1640{ 1641 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1642 int rc; 1643 1644 rc = efx_ef10_get_warm_boot_count(efx); 1645 if (rc < 0) { 1646 /* The firmware is presumably in the process of 1647 * rebooting. However, we are supposed to report each 1648 * reboot just once, so we must only do that once we 1649 * can read and store the updated warm boot count. 1650 */ 1651 return 0; 1652 } 1653 1654 if (rc == nic_data->warm_boot_count) 1655 return 0; 1656 1657 nic_data->warm_boot_count = rc; 1658 efx_ef10_mcdi_reboot_detected(efx); 1659 1660 return -EIO; 1661} 1662 1663/* Handle an MSI interrupt 1664 * 1665 * Handle an MSI hardware interrupt. This routine schedules event 1666 * queue processing. No interrupt acknowledgement cycle is necessary. 1667 * Also, we never need to check that the interrupt is for us, since 1668 * MSI interrupts cannot be shared. 1669 */ 1670static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1671{ 1672 struct efx_msi_context *context = dev_id; 1673 struct efx_nic *efx = context->efx; 1674 1675 netif_vdbg(efx, intr, efx->net_dev, 1676 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1677 1678 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1679 /* Note test interrupts */ 1680 if (context->index == efx->irq_level) 1681 efx->last_irq_cpu = raw_smp_processor_id(); 1682 1683 /* Schedule processing of the channel */ 1684 efx_schedule_channel_irq(efx->channel[context->index]); 1685 } 1686 1687 return IRQ_HANDLED; 1688} 1689 1690static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1691{ 1692 struct efx_nic *efx = dev_id; 1693 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1694 struct efx_channel *channel; 1695 efx_dword_t reg; 1696 u32 queues; 1697 1698 /* Read the ISR which also ACKs the interrupts */ 1699 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1700 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1701 1702 if (queues == 0) 1703 return IRQ_NONE; 1704 1705 if (likely(soft_enabled)) { 1706 /* Note test interrupts */ 1707 if (queues & (1U << efx->irq_level)) 1708 efx->last_irq_cpu = raw_smp_processor_id(); 1709 1710 efx_for_each_channel(channel, efx) { 1711 if (queues & 1) 1712 efx_schedule_channel_irq(channel); 1713 queues >>= 1; 1714 } 1715 } 1716 1717 netif_vdbg(efx, intr, efx->net_dev, 1718 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1719 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1720 1721 return IRQ_HANDLED; 1722} 1723 1724static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1725{ 1726 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1727 1728 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1729 1730 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1731 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1732 inbuf, sizeof(inbuf), NULL, 0, NULL); 1733} 1734 1735static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1736{ 1737 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1738 (tx_queue->ptr_mask + 1) * 1739 sizeof(efx_qword_t), 1740 GFP_KERNEL); 1741} 1742 1743/* This writes to the TX_DESC_WPTR and also pushes data */ 1744static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1745 const efx_qword_t *txd) 1746{ 1747 unsigned int write_ptr; 1748 efx_oword_t reg; 1749 1750 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1751 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1752 reg.qword[0] = *txd; 1753 efx_writeo_page(tx_queue->efx, ®, 1754 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1755} 1756 1757static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1758{ 1759 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1760 EFX_BUF_SIZE)); 1761 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1762 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1763 struct efx_channel *channel = tx_queue->channel; 1764 struct efx_nic *efx = tx_queue->efx; 1765 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1766 size_t inlen; 1767 dma_addr_t dma_addr; 1768 efx_qword_t *txd; 1769 int rc; 1770 int i; 1771 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 1772 1773 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1774 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1775 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1776 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1777 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1778 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1779 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1780 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1781 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 1782 1783 dma_addr = tx_queue->txd.buf.dma_addr; 1784 1785 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1786 tx_queue->queue, entries, (u64)dma_addr); 1787 1788 for (i = 0; i < entries; ++i) { 1789 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1790 dma_addr += EFX_BUF_SIZE; 1791 } 1792 1793 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1794 1795 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1796 NULL, 0, NULL); 1797 if (rc) 1798 goto fail; 1799 1800 /* A previous user of this TX queue might have set us up the 1801 * bomb by writing a descriptor to the TX push collector but 1802 * not the doorbell. (Each collector belongs to a port, not a 1803 * queue or function, so cannot easily be reset.) We must 1804 * attempt to push a no-op descriptor in its place. 1805 */ 1806 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1807 tx_queue->insert_count = 1; 1808 txd = efx_tx_desc(tx_queue, 0); 1809 EFX_POPULATE_QWORD_4(*txd, 1810 ESF_DZ_TX_DESC_IS_OPT, true, 1811 ESF_DZ_TX_OPTION_TYPE, 1812 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1813 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1814 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1815 tx_queue->write_count = 1; 1816 wmb(); 1817 efx_ef10_push_tx_desc(tx_queue, txd); 1818 1819 return; 1820 1821fail: 1822 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1823 tx_queue->queue); 1824} 1825 1826static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1827{ 1828 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1829 MCDI_DECLARE_BUF_ERR(outbuf); 1830 struct efx_nic *efx = tx_queue->efx; 1831 size_t outlen; 1832 int rc; 1833 1834 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1835 tx_queue->queue); 1836 1837 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1838 outbuf, sizeof(outbuf), &outlen); 1839 1840 if (rc && rc != -EALREADY) 1841 goto fail; 1842 1843 return; 1844 1845fail: 1846 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1847 outbuf, outlen, rc); 1848} 1849 1850static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1851{ 1852 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1853} 1854 1855/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1856static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1857{ 1858 unsigned int write_ptr; 1859 efx_dword_t reg; 1860 1861 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1862 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1863 efx_writed_page(tx_queue->efx, ®, 1864 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1865} 1866 1867static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1868{ 1869 unsigned int old_write_count = tx_queue->write_count; 1870 struct efx_tx_buffer *buffer; 1871 unsigned int write_ptr; 1872 efx_qword_t *txd; 1873 1874 tx_queue->xmit_more_available = false; 1875 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 1876 return; 1877 1878 do { 1879 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1880 buffer = &tx_queue->buffer[write_ptr]; 1881 txd = efx_tx_desc(tx_queue, write_ptr); 1882 ++tx_queue->write_count; 1883 1884 /* Create TX descriptor ring entry */ 1885 if (buffer->flags & EFX_TX_BUF_OPTION) { 1886 *txd = buffer->option; 1887 } else { 1888 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1889 EFX_POPULATE_QWORD_3( 1890 *txd, 1891 ESF_DZ_TX_KER_CONT, 1892 buffer->flags & EFX_TX_BUF_CONT, 1893 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1894 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1895 } 1896 } while (tx_queue->write_count != tx_queue->insert_count); 1897 1898 wmb(); /* Ensure descriptors are written before they are fetched */ 1899 1900 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1901 txd = efx_tx_desc(tx_queue, 1902 old_write_count & tx_queue->ptr_mask); 1903 efx_ef10_push_tx_desc(tx_queue, txd); 1904 ++tx_queue->pushes; 1905 } else { 1906 efx_ef10_notify_tx_desc(tx_queue); 1907 } 1908} 1909 1910static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 1911 bool exclusive, unsigned *context_size) 1912{ 1913 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1914 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1915 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1916 size_t outlen; 1917 int rc; 1918 u32 alloc_type = exclusive ? 1919 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 1920 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 1921 unsigned rss_spread = exclusive ? 1922 efx->rss_spread : 1923 min(rounddown_pow_of_two(efx->rss_spread), 1924 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 1925 1926 if (!exclusive && rss_spread == 1) { 1927 *context = EFX_EF10_RSS_CONTEXT_INVALID; 1928 if (context_size) 1929 *context_size = 1; 1930 return 0; 1931 } 1932 1933 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1934 nic_data->vport_id); 1935 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 1936 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 1937 1938 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1939 outbuf, sizeof(outbuf), &outlen); 1940 if (rc != 0) 1941 return rc; 1942 1943 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1944 return -EIO; 1945 1946 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1947 1948 if (context_size) 1949 *context_size = rss_spread; 1950 1951 return 0; 1952} 1953 1954static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1955{ 1956 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1957 int rc; 1958 1959 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1960 context); 1961 1962 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1963 NULL, 0, NULL); 1964 WARN_ON(rc != 0); 1965} 1966 1967static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 1968 const u32 *rx_indir_table) 1969{ 1970 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1971 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1972 int i, rc; 1973 1974 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1975 context); 1976 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1977 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1978 1979 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1980 MCDI_PTR(tablebuf, 1981 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1982 (u8) rx_indir_table[i]; 1983 1984 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1985 sizeof(tablebuf), NULL, 0, NULL); 1986 if (rc != 0) 1987 return rc; 1988 1989 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1990 context); 1991 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1992 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1993 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1994 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1995 efx->rx_hash_key[i]; 1996 1997 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1998 sizeof(keybuf), NULL, 0, NULL); 1999} 2000 2001static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 2002{ 2003 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2004 2005 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2006 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 2007 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 2008} 2009 2010static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 2011 unsigned *context_size) 2012{ 2013 u32 new_rx_rss_context; 2014 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2015 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2016 false, context_size); 2017 2018 if (rc != 0) 2019 return rc; 2020 2021 nic_data->rx_rss_context = new_rx_rss_context; 2022 nic_data->rx_rss_context_exclusive = false; 2023 efx_set_default_rx_indir_table(efx); 2024 return 0; 2025} 2026 2027static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 2028 const u32 *rx_indir_table) 2029{ 2030 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2031 int rc; 2032 u32 new_rx_rss_context; 2033 2034 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 2035 !nic_data->rx_rss_context_exclusive) { 2036 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2037 true, NULL); 2038 if (rc == -EOPNOTSUPP) 2039 return rc; 2040 else if (rc != 0) 2041 goto fail1; 2042 } else { 2043 new_rx_rss_context = nic_data->rx_rss_context; 2044 } 2045 2046 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 2047 rx_indir_table); 2048 if (rc != 0) 2049 goto fail2; 2050 2051 if (nic_data->rx_rss_context != new_rx_rss_context) 2052 efx_ef10_rx_free_indir_table(efx); 2053 nic_data->rx_rss_context = new_rx_rss_context; 2054 nic_data->rx_rss_context_exclusive = true; 2055 if (rx_indir_table != efx->rx_indir_table) 2056 memcpy(efx->rx_indir_table, rx_indir_table, 2057 sizeof(efx->rx_indir_table)); 2058 return 0; 2059 2060fail2: 2061 if (new_rx_rss_context != nic_data->rx_rss_context) 2062 efx_ef10_free_rss_context(efx, new_rx_rss_context); 2063fail1: 2064 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2065 return rc; 2066} 2067 2068static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 2069 const u32 *rx_indir_table) 2070{ 2071 int rc; 2072 2073 if (efx->rss_spread == 1) 2074 return 0; 2075 2076 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 2077 2078 if (rc == -ENOBUFS && !user) { 2079 unsigned context_size; 2080 bool mismatch = false; 2081 size_t i; 2082 2083 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 2084 i++) 2085 mismatch = rx_indir_table[i] != 2086 ethtool_rxfh_indir_default(i, efx->rss_spread); 2087 2088 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2089 if (rc == 0) { 2090 if (context_size != efx->rss_spread) 2091 netif_warn(efx, probe, efx->net_dev, 2092 "Could not allocate an exclusive RSS" 2093 " context; allocated a shared one of" 2094 " different size." 2095 " Wanted %u, got %u.\n", 2096 efx->rss_spread, context_size); 2097 else if (mismatch) 2098 netif_warn(efx, probe, efx->net_dev, 2099 "Could not allocate an exclusive RSS" 2100 " context; allocated a shared one but" 2101 " could not apply custom" 2102 " indirection.\n"); 2103 else 2104 netif_info(efx, probe, efx->net_dev, 2105 "Could not allocate an exclusive RSS" 2106 " context; allocated a shared one.\n"); 2107 } 2108 } 2109 return rc; 2110} 2111 2112static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2113 const u32 *rx_indir_table 2114 __attribute__ ((unused))) 2115{ 2116 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2117 2118 if (user) 2119 return -EOPNOTSUPP; 2120 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2121 return 0; 2122 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2123} 2124 2125static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2126{ 2127 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2128 (rx_queue->ptr_mask + 1) * 2129 sizeof(efx_qword_t), 2130 GFP_KERNEL); 2131} 2132 2133static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2134{ 2135 MCDI_DECLARE_BUF(inbuf, 2136 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2137 EFX_BUF_SIZE)); 2138 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2139 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2140 struct efx_nic *efx = rx_queue->efx; 2141 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2142 size_t inlen; 2143 dma_addr_t dma_addr; 2144 int rc; 2145 int i; 2146 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2147 2148 rx_queue->scatter_n = 0; 2149 rx_queue->scatter_len = 0; 2150 2151 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2152 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2153 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2154 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2155 efx_rx_queue_index(rx_queue)); 2156 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2157 INIT_RXQ_IN_FLAG_PREFIX, 1, 2158 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2159 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2160 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2161 2162 dma_addr = rx_queue->rxd.buf.dma_addr; 2163 2164 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2165 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2166 2167 for (i = 0; i < entries; ++i) { 2168 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2169 dma_addr += EFX_BUF_SIZE; 2170 } 2171 2172 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2173 2174 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2175 NULL, 0, NULL); 2176 if (rc) 2177 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2178 efx_rx_queue_index(rx_queue)); 2179} 2180 2181static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2182{ 2183 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2184 MCDI_DECLARE_BUF_ERR(outbuf); 2185 struct efx_nic *efx = rx_queue->efx; 2186 size_t outlen; 2187 int rc; 2188 2189 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2190 efx_rx_queue_index(rx_queue)); 2191 2192 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2193 outbuf, sizeof(outbuf), &outlen); 2194 2195 if (rc && rc != -EALREADY) 2196 goto fail; 2197 2198 return; 2199 2200fail: 2201 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2202 outbuf, outlen, rc); 2203} 2204 2205static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2206{ 2207 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2208} 2209 2210/* This creates an entry in the RX descriptor queue */ 2211static inline void 2212efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2213{ 2214 struct efx_rx_buffer *rx_buf; 2215 efx_qword_t *rxd; 2216 2217 rxd = efx_rx_desc(rx_queue, index); 2218 rx_buf = efx_rx_buffer(rx_queue, index); 2219 EFX_POPULATE_QWORD_2(*rxd, 2220 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2221 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2222} 2223 2224static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2225{ 2226 struct efx_nic *efx = rx_queue->efx; 2227 unsigned int write_count; 2228 efx_dword_t reg; 2229 2230 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2231 write_count = rx_queue->added_count & ~7; 2232 if (rx_queue->notified_count == write_count) 2233 return; 2234 2235 do 2236 efx_ef10_build_rx_desc( 2237 rx_queue, 2238 rx_queue->notified_count & rx_queue->ptr_mask); 2239 while (++rx_queue->notified_count != write_count); 2240 2241 wmb(); 2242 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2243 write_count & rx_queue->ptr_mask); 2244 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2245 efx_rx_queue_index(rx_queue)); 2246} 2247 2248static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2249 2250static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2251{ 2252 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2253 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2254 efx_qword_t event; 2255 2256 EFX_POPULATE_QWORD_2(event, 2257 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2258 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2259 2260 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2261 2262 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2263 * already swapped the data to little-endian order. 2264 */ 2265 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2266 sizeof(efx_qword_t)); 2267 2268 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2269 inbuf, sizeof(inbuf), 0, 2270 efx_ef10_rx_defer_refill_complete, 0); 2271} 2272 2273static void 2274efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2275 int rc, efx_dword_t *outbuf, 2276 size_t outlen_actual) 2277{ 2278 /* nothing to do */ 2279} 2280 2281static int efx_ef10_ev_probe(struct efx_channel *channel) 2282{ 2283 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2284 (channel->eventq_mask + 1) * 2285 sizeof(efx_qword_t), 2286 GFP_KERNEL); 2287} 2288 2289static void efx_ef10_ev_fini(struct efx_channel *channel) 2290{ 2291 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2292 MCDI_DECLARE_BUF_ERR(outbuf); 2293 struct efx_nic *efx = channel->efx; 2294 size_t outlen; 2295 int rc; 2296 2297 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2298 2299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2300 outbuf, sizeof(outbuf), &outlen); 2301 2302 if (rc && rc != -EALREADY) 2303 goto fail; 2304 2305 return; 2306 2307fail: 2308 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2309 outbuf, outlen, rc); 2310} 2311 2312static int efx_ef10_ev_init(struct efx_channel *channel) 2313{ 2314 MCDI_DECLARE_BUF(inbuf, 2315 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2316 EFX_BUF_SIZE)); 2317 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 2318 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2319 struct efx_nic *efx = channel->efx; 2320 struct efx_ef10_nic_data *nic_data; 2321 bool supports_rx_merge; 2322 size_t inlen, outlen; 2323 unsigned int enabled, implemented; 2324 dma_addr_t dma_addr; 2325 int rc; 2326 int i; 2327 2328 nic_data = efx->nic_data; 2329 supports_rx_merge = 2330 !!(nic_data->datapath_caps & 2331 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2332 2333 /* Fill event queue with all ones (i.e. empty events) */ 2334 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2335 2336 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2337 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2338 /* INIT_EVQ expects index in vector table, not absolute */ 2339 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2340 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2341 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2342 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2343 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2344 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 2345 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2346 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2347 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2348 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2349 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2350 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2351 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2352 2353 dma_addr = channel->eventq.buf.dma_addr; 2354 for (i = 0; i < entries; ++i) { 2355 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2356 dma_addr += EFX_BUF_SIZE; 2357 } 2358 2359 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2360 2361 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2362 outbuf, sizeof(outbuf), &outlen); 2363 /* IRQ return is ignored */ 2364 if (channel->channel || rc) 2365 return rc; 2366 2367 /* Successfully created event queue on channel 0 */ 2368 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2369 if (rc == -ENOSYS) { 2370 /* GET_WORKAROUNDS was implemented before the bug26807 2371 * workaround, thus the latter must be unavailable in this fw 2372 */ 2373 nic_data->workaround_26807 = false; 2374 rc = 0; 2375 } else if (rc) { 2376 goto fail; 2377 } else { 2378 nic_data->workaround_26807 = 2379 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2380 2381 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 && 2382 !nic_data->workaround_26807) { 2383 unsigned int flags; 2384 2385 rc = efx_mcdi_set_workaround(efx, 2386 MC_CMD_WORKAROUND_BUG26807, 2387 true, &flags); 2388 2389 if (!rc) { 2390 if (flags & 2391 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2392 netif_info(efx, drv, efx->net_dev, 2393 "other functions on NIC have been reset\n"); 2394 /* MC's boot count has incremented */ 2395 ++nic_data->warm_boot_count; 2396 } 2397 nic_data->workaround_26807 = true; 2398 } else if (rc == -EPERM) { 2399 rc = 0; 2400 } 2401 } 2402 } 2403 2404 if (!rc) 2405 return 0; 2406 2407fail: 2408 efx_ef10_ev_fini(channel); 2409 return rc; 2410} 2411 2412static void efx_ef10_ev_remove(struct efx_channel *channel) 2413{ 2414 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 2415} 2416 2417static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2418 unsigned int rx_queue_label) 2419{ 2420 struct efx_nic *efx = rx_queue->efx; 2421 2422 netif_info(efx, hw, efx->net_dev, 2423 "rx event arrived on queue %d labeled as queue %u\n", 2424 efx_rx_queue_index(rx_queue), rx_queue_label); 2425 2426 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2427} 2428 2429static void 2430efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2431 unsigned int actual, unsigned int expected) 2432{ 2433 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2434 struct efx_nic *efx = rx_queue->efx; 2435 2436 netif_info(efx, hw, efx->net_dev, 2437 "dropped %d events (index=%d expected=%d)\n", 2438 dropped, actual, expected); 2439 2440 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2441} 2442 2443/* partially received RX was aborted. clean up. */ 2444static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2445{ 2446 unsigned int rx_desc_ptr; 2447 2448 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2449 "scattered RX aborted (dropping %u buffers)\n", 2450 rx_queue->scatter_n); 2451 2452 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2453 2454 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2455 0, EFX_RX_PKT_DISCARD); 2456 2457 rx_queue->removed_count += rx_queue->scatter_n; 2458 rx_queue->scatter_n = 0; 2459 rx_queue->scatter_len = 0; 2460 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2461} 2462 2463static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2464 const efx_qword_t *event) 2465{ 2466 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 2467 unsigned int n_descs, n_packets, i; 2468 struct efx_nic *efx = channel->efx; 2469 struct efx_rx_queue *rx_queue; 2470 bool rx_cont; 2471 u16 flags = 0; 2472 2473 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2474 return 0; 2475 2476 /* Basic packet information */ 2477 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2478 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2479 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2480 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 2481 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2482 2483 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2484 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2485 EFX_QWORD_FMT "\n", 2486 EFX_QWORD_VAL(*event)); 2487 2488 rx_queue = efx_channel_get_rx_queue(channel); 2489 2490 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2491 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2492 2493 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2494 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2495 2496 if (n_descs != rx_queue->scatter_n + 1) { 2497 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2498 2499 /* detect rx abort */ 2500 if (unlikely(n_descs == rx_queue->scatter_n)) { 2501 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2502 netdev_WARN(efx->net_dev, 2503 "invalid RX abort: scatter_n=%u event=" 2504 EFX_QWORD_FMT "\n", 2505 rx_queue->scatter_n, 2506 EFX_QWORD_VAL(*event)); 2507 efx_ef10_handle_rx_abort(rx_queue); 2508 return 0; 2509 } 2510 2511 /* Check that RX completion merging is valid, i.e. 2512 * the current firmware supports it and this is a 2513 * non-scattered packet. 2514 */ 2515 if (!(nic_data->datapath_caps & 2516 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2517 rx_queue->scatter_n != 0 || rx_cont) { 2518 efx_ef10_handle_rx_bad_lbits( 2519 rx_queue, next_ptr_lbits, 2520 (rx_queue->removed_count + 2521 rx_queue->scatter_n + 1) & 2522 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2523 return 0; 2524 } 2525 2526 /* Merged completion for multiple non-scattered packets */ 2527 rx_queue->scatter_n = 1; 2528 rx_queue->scatter_len = 0; 2529 n_packets = n_descs; 2530 ++channel->n_rx_merge_events; 2531 channel->n_rx_merge_packets += n_packets; 2532 flags |= EFX_RX_PKT_PREFIX_LEN; 2533 } else { 2534 ++rx_queue->scatter_n; 2535 rx_queue->scatter_len += rx_bytes; 2536 if (rx_cont) 2537 return 0; 2538 n_packets = 1; 2539 } 2540 2541 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 2542 flags |= EFX_RX_PKT_DISCARD; 2543 2544 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 2545 channel->n_rx_ip_hdr_chksum_err += n_packets; 2546 } else if (unlikely(EFX_QWORD_FIELD(*event, 2547 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 2548 channel->n_rx_tcp_udp_chksum_err += n_packets; 2549 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 2550 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 2551 flags |= EFX_RX_PKT_CSUMMED; 2552 } 2553 2554 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 2555 flags |= EFX_RX_PKT_TCP; 2556 2557 channel->irq_mod_score += 2 * n_packets; 2558 2559 /* Handle received packet(s) */ 2560 for (i = 0; i < n_packets; i++) { 2561 efx_rx_packet(rx_queue, 2562 rx_queue->removed_count & rx_queue->ptr_mask, 2563 rx_queue->scatter_n, rx_queue->scatter_len, 2564 flags); 2565 rx_queue->removed_count += rx_queue->scatter_n; 2566 } 2567 2568 rx_queue->scatter_n = 0; 2569 rx_queue->scatter_len = 0; 2570 2571 return n_packets; 2572} 2573 2574static int 2575efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2576{ 2577 struct efx_nic *efx = channel->efx; 2578 struct efx_tx_queue *tx_queue; 2579 unsigned int tx_ev_desc_ptr; 2580 unsigned int tx_ev_q_label; 2581 int tx_descs = 0; 2582 2583 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2584 return 0; 2585 2586 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2587 return 0; 2588 2589 /* Transmit completion */ 2590 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2591 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2592 tx_queue = efx_channel_get_tx_queue(channel, 2593 tx_ev_q_label % EFX_TXQ_TYPES); 2594 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 2595 tx_queue->ptr_mask); 2596 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2597 2598 return tx_descs; 2599} 2600 2601static void 2602efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2603{ 2604 struct efx_nic *efx = channel->efx; 2605 int subcode; 2606 2607 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2608 2609 switch (subcode) { 2610 case ESE_DZ_DRV_TIMER_EV: 2611 case ESE_DZ_DRV_WAKE_UP_EV: 2612 break; 2613 case ESE_DZ_DRV_START_UP_EV: 2614 /* event queue init complete. ok. */ 2615 break; 2616 default: 2617 netif_err(efx, hw, efx->net_dev, 2618 "channel %d unknown driver event type %d" 2619 " (data " EFX_QWORD_FMT ")\n", 2620 channel->channel, subcode, 2621 EFX_QWORD_VAL(*event)); 2622 2623 } 2624} 2625 2626static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2627 efx_qword_t *event) 2628{ 2629 struct efx_nic *efx = channel->efx; 2630 u32 subcode; 2631 2632 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2633 2634 switch (subcode) { 2635 case EFX_EF10_TEST: 2636 channel->event_test_cpu = raw_smp_processor_id(); 2637 break; 2638 case EFX_EF10_REFILL: 2639 /* The queue must be empty, so we won't receive any rx 2640 * events, so efx_process_channel() won't refill the 2641 * queue. Refill it here 2642 */ 2643 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2644 break; 2645 default: 2646 netif_err(efx, hw, efx->net_dev, 2647 "channel %d unknown driver event type %u" 2648 " (data " EFX_QWORD_FMT ")\n", 2649 channel->channel, (unsigned) subcode, 2650 EFX_QWORD_VAL(*event)); 2651 } 2652} 2653 2654static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2655{ 2656 struct efx_nic *efx = channel->efx; 2657 efx_qword_t event, *p_event; 2658 unsigned int read_ptr; 2659 int ev_code; 2660 int tx_descs = 0; 2661 int spent = 0; 2662 2663 if (quota <= 0) 2664 return spent; 2665 2666 read_ptr = channel->eventq_read_ptr; 2667 2668 for (;;) { 2669 p_event = efx_event(channel, read_ptr); 2670 event = *p_event; 2671 2672 if (!efx_event_present(&event)) 2673 break; 2674 2675 EFX_SET_QWORD(*p_event); 2676 2677 ++read_ptr; 2678 2679 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 2680 2681 netif_vdbg(efx, drv, efx->net_dev, 2682 "processing event on %d " EFX_QWORD_FMT "\n", 2683 channel->channel, EFX_QWORD_VAL(event)); 2684 2685 switch (ev_code) { 2686 case ESE_DZ_EV_CODE_MCDI_EV: 2687 efx_mcdi_process_event(channel, &event); 2688 break; 2689 case ESE_DZ_EV_CODE_RX_EV: 2690 spent += efx_ef10_handle_rx_event(channel, &event); 2691 if (spent >= quota) { 2692 /* XXX can we split a merged event to 2693 * avoid going over-quota? 2694 */ 2695 spent = quota; 2696 goto out; 2697 } 2698 break; 2699 case ESE_DZ_EV_CODE_TX_EV: 2700 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2701 if (tx_descs > efx->txq_entries) { 2702 spent = quota; 2703 goto out; 2704 } else if (++spent == quota) { 2705 goto out; 2706 } 2707 break; 2708 case ESE_DZ_EV_CODE_DRIVER_EV: 2709 efx_ef10_handle_driver_event(channel, &event); 2710 if (++spent == quota) 2711 goto out; 2712 break; 2713 case EFX_EF10_DRVGEN_EV: 2714 efx_ef10_handle_driver_generated_event(channel, &event); 2715 break; 2716 default: 2717 netif_err(efx, hw, efx->net_dev, 2718 "channel %d unknown event type %d" 2719 " (data " EFX_QWORD_FMT ")\n", 2720 channel->channel, ev_code, 2721 EFX_QWORD_VAL(event)); 2722 } 2723 } 2724 2725out: 2726 channel->eventq_read_ptr = read_ptr; 2727 return spent; 2728} 2729 2730static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2731{ 2732 struct efx_nic *efx = channel->efx; 2733 efx_dword_t rptr; 2734 2735 if (EFX_EF10_WORKAROUND_35388(efx)) { 2736 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2737 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2738 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2739 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2740 2741 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2742 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2743 ERF_DD_EVQ_IND_RPTR, 2744 (channel->eventq_read_ptr & 2745 channel->eventq_mask) >> 2746 ERF_DD_EVQ_IND_RPTR_WIDTH); 2747 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2748 channel->channel); 2749 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2750 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2751 ERF_DD_EVQ_IND_RPTR, 2752 channel->eventq_read_ptr & 2753 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2754 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2755 channel->channel); 2756 } else { 2757 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2758 channel->eventq_read_ptr & 2759 channel->eventq_mask); 2760 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2761 } 2762} 2763 2764static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2765{ 2766 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2767 struct efx_nic *efx = channel->efx; 2768 efx_qword_t event; 2769 int rc; 2770 2771 EFX_POPULATE_QWORD_2(event, 2772 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2773 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2774 2775 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2776 2777 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2778 * already swapped the data to little-endian order. 2779 */ 2780 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2781 sizeof(efx_qword_t)); 2782 2783 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2784 NULL, 0, NULL); 2785 if (rc != 0) 2786 goto fail; 2787 2788 return; 2789 2790fail: 2791 WARN_ON(true); 2792 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2793} 2794 2795void efx_ef10_handle_drain_event(struct efx_nic *efx) 2796{ 2797 if (atomic_dec_and_test(&efx->active_queues)) 2798 wake_up(&efx->flush_wq); 2799 2800 WARN_ON(atomic_read(&efx->active_queues) < 0); 2801} 2802 2803static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2804{ 2805 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2806 struct efx_channel *channel; 2807 struct efx_tx_queue *tx_queue; 2808 struct efx_rx_queue *rx_queue; 2809 int pending; 2810 2811 /* If the MC has just rebooted, the TX/RX queues will have already been 2812 * torn down, but efx->active_queues needs to be set to zero. 2813 */ 2814 if (nic_data->must_realloc_vis) { 2815 atomic_set(&efx->active_queues, 0); 2816 return 0; 2817 } 2818 2819 /* Do not attempt to write to the NIC during EEH recovery */ 2820 if (efx->state != STATE_RECOVERY) { 2821 efx_for_each_channel(channel, efx) { 2822 efx_for_each_channel_rx_queue(rx_queue, channel) 2823 efx_ef10_rx_fini(rx_queue); 2824 efx_for_each_channel_tx_queue(tx_queue, channel) 2825 efx_ef10_tx_fini(tx_queue); 2826 } 2827 2828 wait_event_timeout(efx->flush_wq, 2829 atomic_read(&efx->active_queues) == 0, 2830 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2831 pending = atomic_read(&efx->active_queues); 2832 if (pending) { 2833 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2834 pending); 2835 return -ETIMEDOUT; 2836 } 2837 } 2838 2839 return 0; 2840} 2841 2842static void efx_ef10_prepare_flr(struct efx_nic *efx) 2843{ 2844 atomic_set(&efx->active_queues, 0); 2845} 2846 2847static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2848 const struct efx_filter_spec *right) 2849{ 2850 if ((left->match_flags ^ right->match_flags) | 2851 ((left->flags ^ right->flags) & 2852 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2853 return false; 2854 2855 return memcmp(&left->outer_vid, &right->outer_vid, 2856 sizeof(struct efx_filter_spec) - 2857 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2858} 2859 2860static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2861{ 2862 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2863 return jhash2((const u32 *)&spec->outer_vid, 2864 (sizeof(struct efx_filter_spec) - 2865 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2866 0); 2867 /* XXX should we randomise the initval? */ 2868} 2869 2870/* Decide whether a filter should be exclusive or else should allow 2871 * delivery to additional recipients. Currently we decide that 2872 * filters for specific local unicast MAC and IP addresses are 2873 * exclusive. 2874 */ 2875static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2876{ 2877 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2878 !is_multicast_ether_addr(spec->loc_mac)) 2879 return true; 2880 2881 if ((spec->match_flags & 2882 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2883 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2884 if (spec->ether_type == htons(ETH_P_IP) && 2885 !ipv4_is_multicast(spec->loc_host[0])) 2886 return true; 2887 if (spec->ether_type == htons(ETH_P_IPV6) && 2888 ((const u8 *)spec->loc_host)[0] != 0xff) 2889 return true; 2890 } 2891 2892 return false; 2893} 2894 2895static struct efx_filter_spec * 2896efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2897 unsigned int filter_idx) 2898{ 2899 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2900 ~EFX_EF10_FILTER_FLAGS); 2901} 2902 2903static unsigned int 2904efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2905 unsigned int filter_idx) 2906{ 2907 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2908} 2909 2910static void 2911efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2912 unsigned int filter_idx, 2913 const struct efx_filter_spec *spec, 2914 unsigned int flags) 2915{ 2916 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2917} 2918 2919static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2920 const struct efx_filter_spec *spec, 2921 efx_dword_t *inbuf, u64 handle, 2922 bool replacing) 2923{ 2924 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2925 2926 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2927 2928 if (replacing) { 2929 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2930 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2931 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2932 } else { 2933 u32 match_fields = 0; 2934 2935 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2936 efx_ef10_filter_is_exclusive(spec) ? 2937 MC_CMD_FILTER_OP_IN_OP_INSERT : 2938 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2939 2940 /* Convert match flags and values. Unlike almost 2941 * everything else in MCDI, these fields are in 2942 * network byte order. 2943 */ 2944 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2945 match_fields |= 2946 is_multicast_ether_addr(spec->loc_mac) ? 2947 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2948 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2949#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2950 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2951 match_fields |= \ 2952 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2953 mcdi_field ## _LBN; \ 2954 BUILD_BUG_ON( \ 2955 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2956 sizeof(spec->gen_field)); \ 2957 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2958 &spec->gen_field, sizeof(spec->gen_field)); \ 2959 } 2960 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2961 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2962 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2963 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2964 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2965 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2966 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2967 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2968 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2969 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2970#undef COPY_FIELD 2971 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2972 match_fields); 2973 } 2974 2975 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 2976 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2977 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2978 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2979 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2980 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 2981 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2982 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2983 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2984 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2985 0 : spec->dmaq_id); 2986 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2987 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? 2988 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 2989 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 2990 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) 2991 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 2992 spec->rss_context != 2993 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 2994 spec->rss_context : nic_data->rx_rss_context); 2995} 2996 2997static int efx_ef10_filter_push(struct efx_nic *efx, 2998 const struct efx_filter_spec *spec, 2999 u64 *handle, bool replacing) 3000{ 3001 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3002 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 3003 int rc; 3004 3005 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 3006 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3007 outbuf, sizeof(outbuf), NULL); 3008 if (rc == 0) 3009 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3010 if (rc == -ENOSPC) 3011 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 3012 return rc; 3013} 3014 3015static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 3016 enum efx_filter_match_flags match_flags) 3017{ 3018 unsigned int match_pri; 3019 3020 for (match_pri = 0; 3021 match_pri < table->rx_match_count; 3022 match_pri++) 3023 if (table->rx_match_flags[match_pri] == match_flags) 3024 return match_pri; 3025 3026 return -EPROTONOSUPPORT; 3027} 3028 3029static s32 efx_ef10_filter_insert(struct efx_nic *efx, 3030 struct efx_filter_spec *spec, 3031 bool replace_equal) 3032{ 3033 struct efx_ef10_filter_table *table = efx->filter_state; 3034 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3035 struct efx_filter_spec *saved_spec; 3036 unsigned int match_pri, hash; 3037 unsigned int priv_flags; 3038 bool replacing = false; 3039 int ins_index = -1; 3040 DEFINE_WAIT(wait); 3041 bool is_mc_recip; 3042 s32 rc; 3043 3044 /* For now, only support RX filters */ 3045 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 3046 EFX_FILTER_FLAG_RX) 3047 return -EINVAL; 3048 3049 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 3050 if (rc < 0) 3051 return rc; 3052 match_pri = rc; 3053 3054 hash = efx_ef10_filter_hash(spec); 3055 is_mc_recip = efx_filter_is_mc_recipient(spec); 3056 if (is_mc_recip) 3057 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3058 3059 /* Find any existing filters with the same match tuple or 3060 * else a free slot to insert at. If any of them are busy, 3061 * we have to wait and retry. 3062 */ 3063 for (;;) { 3064 unsigned int depth = 1; 3065 unsigned int i; 3066 3067 spin_lock_bh(&efx->filter_lock); 3068 3069 for (;;) { 3070 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3071 saved_spec = efx_ef10_filter_entry_spec(table, i); 3072 3073 if (!saved_spec) { 3074 if (ins_index < 0) 3075 ins_index = i; 3076 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3077 if (table->entry[i].spec & 3078 EFX_EF10_FILTER_FLAG_BUSY) 3079 break; 3080 if (spec->priority < saved_spec->priority && 3081 spec->priority != EFX_FILTER_PRI_AUTO) { 3082 rc = -EPERM; 3083 goto out_unlock; 3084 } 3085 if (!is_mc_recip) { 3086 /* This is the only one */ 3087 if (spec->priority == 3088 saved_spec->priority && 3089 !replace_equal) { 3090 rc = -EEXIST; 3091 goto out_unlock; 3092 } 3093 ins_index = i; 3094 goto found; 3095 } else if (spec->priority > 3096 saved_spec->priority || 3097 (spec->priority == 3098 saved_spec->priority && 3099 replace_equal)) { 3100 if (ins_index < 0) 3101 ins_index = i; 3102 else 3103 __set_bit(depth, mc_rem_map); 3104 } 3105 } 3106 3107 /* Once we reach the maximum search depth, use 3108 * the first suitable slot or return -EBUSY if 3109 * there was none 3110 */ 3111 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3112 if (ins_index < 0) { 3113 rc = -EBUSY; 3114 goto out_unlock; 3115 } 3116 goto found; 3117 } 3118 3119 ++depth; 3120 } 3121 3122 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3123 spin_unlock_bh(&efx->filter_lock); 3124 schedule(); 3125 } 3126 3127found: 3128 /* Create a software table entry if necessary, and mark it 3129 * busy. We might yet fail to insert, but any attempt to 3130 * insert a conflicting filter while we're waiting for the 3131 * firmware must find the busy entry. 3132 */ 3133 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3134 if (saved_spec) { 3135 if (spec->priority == EFX_FILTER_PRI_AUTO && 3136 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3137 /* Just make sure it won't be removed */ 3138 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3139 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3140 table->entry[ins_index].spec &= 3141 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3142 rc = ins_index; 3143 goto out_unlock; 3144 } 3145 replacing = true; 3146 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3147 } else { 3148 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3149 if (!saved_spec) { 3150 rc = -ENOMEM; 3151 goto out_unlock; 3152 } 3153 *saved_spec = *spec; 3154 priv_flags = 0; 3155 } 3156 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3157 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3158 3159 /* Mark lower-priority multicast recipients busy prior to removal */ 3160 if (is_mc_recip) { 3161 unsigned int depth, i; 3162 3163 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3164 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3165 if (test_bit(depth, mc_rem_map)) 3166 table->entry[i].spec |= 3167 EFX_EF10_FILTER_FLAG_BUSY; 3168 } 3169 } 3170 3171 spin_unlock_bh(&efx->filter_lock); 3172 3173 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3174 replacing); 3175 3176 /* Finalise the software table entry */ 3177 spin_lock_bh(&efx->filter_lock); 3178 if (rc == 0) { 3179 if (replacing) { 3180 /* Update the fields that may differ */ 3181 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3182 saved_spec->flags |= 3183 EFX_FILTER_FLAG_RX_OVER_AUTO; 3184 saved_spec->priority = spec->priority; 3185 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3186 saved_spec->flags |= spec->flags; 3187 saved_spec->rss_context = spec->rss_context; 3188 saved_spec->dmaq_id = spec->dmaq_id; 3189 } 3190 } else if (!replacing) { 3191 kfree(saved_spec); 3192 saved_spec = NULL; 3193 } 3194 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3195 3196 /* Remove and finalise entries for lower-priority multicast 3197 * recipients 3198 */ 3199 if (is_mc_recip) { 3200 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3201 unsigned int depth, i; 3202 3203 memset(inbuf, 0, sizeof(inbuf)); 3204 3205 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3206 if (!test_bit(depth, mc_rem_map)) 3207 continue; 3208 3209 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3210 saved_spec = efx_ef10_filter_entry_spec(table, i); 3211 priv_flags = efx_ef10_filter_entry_flags(table, i); 3212 3213 if (rc == 0) { 3214 spin_unlock_bh(&efx->filter_lock); 3215 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3216 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3217 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3218 table->entry[i].handle); 3219 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3220 inbuf, sizeof(inbuf), 3221 NULL, 0, NULL); 3222 spin_lock_bh(&efx->filter_lock); 3223 } 3224 3225 if (rc == 0) { 3226 kfree(saved_spec); 3227 saved_spec = NULL; 3228 priv_flags = 0; 3229 } else { 3230 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3231 } 3232 efx_ef10_filter_set_entry(table, i, saved_spec, 3233 priv_flags); 3234 } 3235 } 3236 3237 /* If successful, return the inserted filter ID */ 3238 if (rc == 0) 3239 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3240 3241 wake_up_all(&table->waitq); 3242out_unlock: 3243 spin_unlock_bh(&efx->filter_lock); 3244 finish_wait(&table->waitq, &wait); 3245 return rc; 3246} 3247 3248static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3249{ 3250 /* no need to do anything here on EF10 */ 3251} 3252 3253/* Remove a filter. 3254 * If !by_index, remove by ID 3255 * If by_index, remove by index 3256 * Filter ID may come from userland and must be range-checked. 3257 */ 3258static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3259 unsigned int priority_mask, 3260 u32 filter_id, bool by_index) 3261{ 3262 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3263 struct efx_ef10_filter_table *table = efx->filter_state; 3264 MCDI_DECLARE_BUF(inbuf, 3265 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3266 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3267 struct efx_filter_spec *spec; 3268 DEFINE_WAIT(wait); 3269 int rc; 3270 3271 /* Find the software table entry and mark it busy. Don't 3272 * remove it yet; any attempt to update while we're waiting 3273 * for the firmware must find the busy entry. 3274 */ 3275 for (;;) { 3276 spin_lock_bh(&efx->filter_lock); 3277 if (!(table->entry[filter_idx].spec & 3278 EFX_EF10_FILTER_FLAG_BUSY)) 3279 break; 3280 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3281 spin_unlock_bh(&efx->filter_lock); 3282 schedule(); 3283 } 3284 3285 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3286 if (!spec || 3287 (!by_index && 3288 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 3289 filter_id / HUNT_FILTER_TBL_ROWS)) { 3290 rc = -ENOENT; 3291 goto out_unlock; 3292 } 3293 3294 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3295 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3296 /* Just remove flags */ 3297 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3298 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3299 rc = 0; 3300 goto out_unlock; 3301 } 3302 3303 if (!(priority_mask & (1U << spec->priority))) { 3304 rc = -ENOENT; 3305 goto out_unlock; 3306 } 3307 3308 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3309 spin_unlock_bh(&efx->filter_lock); 3310 3311 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3312 /* Reset to an automatic filter */ 3313 3314 struct efx_filter_spec new_spec = *spec; 3315 3316 new_spec.priority = EFX_FILTER_PRI_AUTO; 3317 new_spec.flags = (EFX_FILTER_FLAG_RX | 3318 (efx_rss_enabled(efx) ? 3319 EFX_FILTER_FLAG_RX_RSS : 0)); 3320 new_spec.dmaq_id = 0; 3321 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3322 rc = efx_ef10_filter_push(efx, &new_spec, 3323 &table->entry[filter_idx].handle, 3324 true); 3325 3326 spin_lock_bh(&efx->filter_lock); 3327 if (rc == 0) 3328 *spec = new_spec; 3329 } else { 3330 /* Really remove the filter */ 3331 3332 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3333 efx_ef10_filter_is_exclusive(spec) ? 3334 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3335 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3336 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3337 table->entry[filter_idx].handle); 3338 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3339 inbuf, sizeof(inbuf), NULL, 0, NULL); 3340 3341 spin_lock_bh(&efx->filter_lock); 3342 if (rc == 0) { 3343 kfree(spec); 3344 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3345 } 3346 } 3347 3348 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3349 wake_up_all(&table->waitq); 3350out_unlock: 3351 spin_unlock_bh(&efx->filter_lock); 3352 finish_wait(&table->waitq, &wait); 3353 return rc; 3354} 3355 3356static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3357 enum efx_filter_priority priority, 3358 u32 filter_id) 3359{ 3360 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3361 filter_id, false); 3362} 3363 3364static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id) 3365{ 3366 return filter_id % HUNT_FILTER_TBL_ROWS; 3367} 3368 3369static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx, 3370 enum efx_filter_priority priority, 3371 u32 filter_id) 3372{ 3373 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3374 filter_id, true); 3375} 3376 3377static int efx_ef10_filter_get_safe(struct efx_nic *efx, 3378 enum efx_filter_priority priority, 3379 u32 filter_id, struct efx_filter_spec *spec) 3380{ 3381 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3382 struct efx_ef10_filter_table *table = efx->filter_state; 3383 const struct efx_filter_spec *saved_spec; 3384 int rc; 3385 3386 spin_lock_bh(&efx->filter_lock); 3387 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 3388 if (saved_spec && saved_spec->priority == priority && 3389 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 3390 filter_id / HUNT_FILTER_TBL_ROWS) { 3391 *spec = *saved_spec; 3392 rc = 0; 3393 } else { 3394 rc = -ENOENT; 3395 } 3396 spin_unlock_bh(&efx->filter_lock); 3397 return rc; 3398} 3399 3400static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 3401 enum efx_filter_priority priority) 3402{ 3403 unsigned int priority_mask; 3404 unsigned int i; 3405 int rc; 3406 3407 priority_mask = (((1U << (priority + 1)) - 1) & 3408 ~(1U << EFX_FILTER_PRI_AUTO)); 3409 3410 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3411 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 3412 i, true); 3413 if (rc && rc != -ENOENT) 3414 return rc; 3415 } 3416 3417 return 0; 3418} 3419 3420static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 3421 enum efx_filter_priority priority) 3422{ 3423 struct efx_ef10_filter_table *table = efx->filter_state; 3424 unsigned int filter_idx; 3425 s32 count = 0; 3426 3427 spin_lock_bh(&efx->filter_lock); 3428 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3429 if (table->entry[filter_idx].spec && 3430 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 3431 priority) 3432 ++count; 3433 } 3434 spin_unlock_bh(&efx->filter_lock); 3435 return count; 3436} 3437 3438static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 3439{ 3440 struct efx_ef10_filter_table *table = efx->filter_state; 3441 3442 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 3443} 3444 3445static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 3446 enum efx_filter_priority priority, 3447 u32 *buf, u32 size) 3448{ 3449 struct efx_ef10_filter_table *table = efx->filter_state; 3450 struct efx_filter_spec *spec; 3451 unsigned int filter_idx; 3452 s32 count = 0; 3453 3454 spin_lock_bh(&efx->filter_lock); 3455 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3456 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3457 if (spec && spec->priority == priority) { 3458 if (count == size) { 3459 count = -EMSGSIZE; 3460 break; 3461 } 3462 buf[count++] = (efx_ef10_filter_rx_match_pri( 3463 table, spec->match_flags) * 3464 HUNT_FILTER_TBL_ROWS + 3465 filter_idx); 3466 } 3467 } 3468 spin_unlock_bh(&efx->filter_lock); 3469 return count; 3470} 3471 3472#ifdef CONFIG_RFS_ACCEL 3473 3474static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 3475 3476static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 3477 struct efx_filter_spec *spec) 3478{ 3479 struct efx_ef10_filter_table *table = efx->filter_state; 3480 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3481 struct efx_filter_spec *saved_spec; 3482 unsigned int hash, i, depth = 1; 3483 bool replacing = false; 3484 int ins_index = -1; 3485 u64 cookie; 3486 s32 rc; 3487 3488 /* Must be an RX filter without RSS and not for a multicast 3489 * destination address (RFS only works for connected sockets). 3490 * These restrictions allow us to pass only a tiny amount of 3491 * data through to the completion function. 3492 */ 3493 EFX_WARN_ON_PARANOID(spec->flags != 3494 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 3495 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 3496 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 3497 3498 hash = efx_ef10_filter_hash(spec); 3499 3500 spin_lock_bh(&efx->filter_lock); 3501 3502 /* Find any existing filter with the same match tuple or else 3503 * a free slot to insert at. If an existing filter is busy, 3504 * we have to give up. 3505 */ 3506 for (;;) { 3507 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3508 saved_spec = efx_ef10_filter_entry_spec(table, i); 3509 3510 if (!saved_spec) { 3511 if (ins_index < 0) 3512 ins_index = i; 3513 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3514 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 3515 rc = -EBUSY; 3516 goto fail_unlock; 3517 } 3518 if (spec->priority < saved_spec->priority) { 3519 rc = -EPERM; 3520 goto fail_unlock; 3521 } 3522 ins_index = i; 3523 break; 3524 } 3525 3526 /* Once we reach the maximum search depth, use the 3527 * first suitable slot or return -EBUSY if there was 3528 * none 3529 */ 3530 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3531 if (ins_index < 0) { 3532 rc = -EBUSY; 3533 goto fail_unlock; 3534 } 3535 break; 3536 } 3537 3538 ++depth; 3539 } 3540 3541 /* Create a software table entry if necessary, and mark it 3542 * busy. We might yet fail to insert, but any attempt to 3543 * insert a conflicting filter while we're waiting for the 3544 * firmware must find the busy entry. 3545 */ 3546 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3547 if (saved_spec) { 3548 replacing = true; 3549 } else { 3550 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3551 if (!saved_spec) { 3552 rc = -ENOMEM; 3553 goto fail_unlock; 3554 } 3555 *saved_spec = *spec; 3556 } 3557 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3558 EFX_EF10_FILTER_FLAG_BUSY); 3559 3560 spin_unlock_bh(&efx->filter_lock); 3561 3562 /* Pack up the variables needed on completion */ 3563 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 3564 3565 efx_ef10_filter_push_prep(efx, spec, inbuf, 3566 table->entry[ins_index].handle, replacing); 3567 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3568 MC_CMD_FILTER_OP_OUT_LEN, 3569 efx_ef10_filter_rfs_insert_complete, cookie); 3570 3571 return ins_index; 3572 3573fail_unlock: 3574 spin_unlock_bh(&efx->filter_lock); 3575 return rc; 3576} 3577 3578static void 3579efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 3580 int rc, efx_dword_t *outbuf, 3581 size_t outlen_actual) 3582{ 3583 struct efx_ef10_filter_table *table = efx->filter_state; 3584 unsigned int ins_index, dmaq_id; 3585 struct efx_filter_spec *spec; 3586 bool replacing; 3587 3588 /* Unpack the cookie */ 3589 replacing = cookie >> 31; 3590 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 3591 dmaq_id = cookie & 0xffff; 3592 3593 spin_lock_bh(&efx->filter_lock); 3594 spec = efx_ef10_filter_entry_spec(table, ins_index); 3595 if (rc == 0) { 3596 table->entry[ins_index].handle = 3597 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3598 if (replacing) 3599 spec->dmaq_id = dmaq_id; 3600 } else if (!replacing) { 3601 kfree(spec); 3602 spec = NULL; 3603 } 3604 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 3605 spin_unlock_bh(&efx->filter_lock); 3606 3607 wake_up_all(&table->waitq); 3608} 3609 3610static void 3611efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3612 unsigned long filter_idx, 3613 int rc, efx_dword_t *outbuf, 3614 size_t outlen_actual); 3615 3616static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 3617 unsigned int filter_idx) 3618{ 3619 struct efx_ef10_filter_table *table = efx->filter_state; 3620 struct efx_filter_spec *spec = 3621 efx_ef10_filter_entry_spec(table, filter_idx); 3622 MCDI_DECLARE_BUF(inbuf, 3623 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3624 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3625 3626 if (!spec || 3627 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 3628 spec->priority != EFX_FILTER_PRI_HINT || 3629 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 3630 flow_id, filter_idx)) 3631 return false; 3632 3633 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3634 MC_CMD_FILTER_OP_IN_OP_REMOVE); 3635 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3636 table->entry[filter_idx].handle); 3637 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 3638 efx_ef10_filter_rfs_expire_complete, filter_idx)) 3639 return false; 3640 3641 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3642 return true; 3643} 3644 3645static void 3646efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3647 unsigned long filter_idx, 3648 int rc, efx_dword_t *outbuf, 3649 size_t outlen_actual) 3650{ 3651 struct efx_ef10_filter_table *table = efx->filter_state; 3652 struct efx_filter_spec *spec = 3653 efx_ef10_filter_entry_spec(table, filter_idx); 3654 3655 spin_lock_bh(&efx->filter_lock); 3656 if (rc == 0) { 3657 kfree(spec); 3658 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3659 } 3660 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3661 wake_up_all(&table->waitq); 3662 spin_unlock_bh(&efx->filter_lock); 3663} 3664 3665#endif /* CONFIG_RFS_ACCEL */ 3666 3667static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 3668{ 3669 int match_flags = 0; 3670 3671#define MAP_FLAG(gen_flag, mcdi_field) { \ 3672 u32 old_mcdi_flags = mcdi_flags; \ 3673 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3674 mcdi_field ## _LBN); \ 3675 if (mcdi_flags != old_mcdi_flags) \ 3676 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 3677 } 3678 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 3679 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 3680 MAP_FLAG(REM_HOST, SRC_IP); 3681 MAP_FLAG(LOC_HOST, DST_IP); 3682 MAP_FLAG(REM_MAC, SRC_MAC); 3683 MAP_FLAG(REM_PORT, SRC_PORT); 3684 MAP_FLAG(LOC_MAC, DST_MAC); 3685 MAP_FLAG(LOC_PORT, DST_PORT); 3686 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 3687 MAP_FLAG(INNER_VID, INNER_VLAN); 3688 MAP_FLAG(OUTER_VID, OUTER_VLAN); 3689 MAP_FLAG(IP_PROTO, IP_PROTO); 3690#undef MAP_FLAG 3691 3692 /* Did we map them all? */ 3693 if (mcdi_flags) 3694 return -EINVAL; 3695 3696 return match_flags; 3697} 3698 3699static int efx_ef10_filter_table_probe(struct efx_nic *efx) 3700{ 3701 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 3702 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 3703 unsigned int pd_match_pri, pd_match_count; 3704 struct efx_ef10_filter_table *table; 3705 size_t outlen; 3706 int rc; 3707 3708 table = kzalloc(sizeof(*table), GFP_KERNEL); 3709 if (!table) 3710 return -ENOMEM; 3711 3712 /* Find out which RX filter types are supported, and their priorities */ 3713 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 3714 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 3715 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 3716 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 3717 &outlen); 3718 if (rc) 3719 goto fail; 3720 pd_match_count = MCDI_VAR_ARRAY_LEN( 3721 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3722 table->rx_match_count = 0; 3723 3724 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3725 u32 mcdi_flags = 3726 MCDI_ARRAY_DWORD( 3727 outbuf, 3728 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3729 pd_match_pri); 3730 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3731 if (rc < 0) { 3732 netif_dbg(efx, probe, efx->net_dev, 3733 "%s: fw flags %#x pri %u not supported in driver\n", 3734 __func__, mcdi_flags, pd_match_pri); 3735 } else { 3736 netif_dbg(efx, probe, efx->net_dev, 3737 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3738 __func__, mcdi_flags, pd_match_pri, 3739 rc, table->rx_match_count); 3740 table->rx_match_flags[table->rx_match_count++] = rc; 3741 } 3742 } 3743 3744 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3745 if (!table->entry) { 3746 rc = -ENOMEM; 3747 goto fail; 3748 } 3749 3750 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3751 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3752 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3753 3754 efx->filter_state = table; 3755 init_waitqueue_head(&table->waitq); 3756 return 0; 3757 3758fail: 3759 kfree(table); 3760 return rc; 3761} 3762 3763/* Caller must hold efx->filter_sem for read if race against 3764 * efx_ef10_filter_table_remove() is possible 3765 */ 3766static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3767{ 3768 struct efx_ef10_filter_table *table = efx->filter_state; 3769 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3770 struct efx_filter_spec *spec; 3771 unsigned int filter_idx; 3772 bool failed = false; 3773 int rc; 3774 3775 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 3776 3777 if (!nic_data->must_restore_filters) 3778 return; 3779 3780 if (!table) 3781 return; 3782 3783 spin_lock_bh(&efx->filter_lock); 3784 3785 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3786 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3787 if (!spec) 3788 continue; 3789 3790 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3791 spin_unlock_bh(&efx->filter_lock); 3792 3793 rc = efx_ef10_filter_push(efx, spec, 3794 &table->entry[filter_idx].handle, 3795 false); 3796 if (rc) 3797 failed = true; 3798 3799 spin_lock_bh(&efx->filter_lock); 3800 if (rc) { 3801 kfree(spec); 3802 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3803 } else { 3804 table->entry[filter_idx].spec &= 3805 ~EFX_EF10_FILTER_FLAG_BUSY; 3806 } 3807 } 3808 3809 spin_unlock_bh(&efx->filter_lock); 3810 3811 if (failed) 3812 netif_err(efx, hw, efx->net_dev, 3813 "unable to restore all filters\n"); 3814 else 3815 nic_data->must_restore_filters = false; 3816} 3817 3818/* Caller must hold efx->filter_sem for write */ 3819static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3820{ 3821 struct efx_ef10_filter_table *table = efx->filter_state; 3822 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3823 struct efx_filter_spec *spec; 3824 unsigned int filter_idx; 3825 int rc; 3826 3827 efx->filter_state = NULL; 3828 if (!table) 3829 return; 3830 3831 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3832 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3833 if (!spec) 3834 continue; 3835 3836 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3837 efx_ef10_filter_is_exclusive(spec) ? 3838 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3839 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3840 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3841 table->entry[filter_idx].handle); 3842 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3843 NULL, 0, NULL); 3844 if (rc) 3845 netdev_WARN(efx->net_dev, 3846 "filter_idx=%#x handle=%#llx\n", 3847 filter_idx, 3848 table->entry[filter_idx].handle); 3849 kfree(spec); 3850 } 3851 3852 vfree(table->entry); 3853 kfree(table); 3854} 3855 3856#define EFX_EF10_FILTER_DO_MARK_OLD(id) \ 3857 if (id != EFX_EF10_FILTER_ID_INVALID) { \ 3858 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \ 3859 WARN_ON(!table->entry[filter_idx].spec); \ 3860 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \ 3861 } 3862static void efx_ef10_filter_mark_old(struct efx_nic *efx) 3863{ 3864 struct efx_ef10_filter_table *table = efx->filter_state; 3865 unsigned int filter_idx, i; 3866 3867 if (!table) 3868 return; 3869 3870 /* Mark old filters that may need to be removed */ 3871 spin_lock_bh(&efx->filter_lock); 3872 for (i = 0; i < table->dev_uc_count; i++) 3873 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id); 3874 for (i = 0; i < table->dev_mc_count; i++) 3875 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id); 3876 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id); 3877 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id); 3878 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id); 3879 spin_unlock_bh(&efx->filter_lock); 3880} 3881#undef EFX_EF10_FILTER_DO_MARK_OLD 3882 3883static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc) 3884{ 3885 struct efx_ef10_filter_table *table = efx->filter_state; 3886 struct net_device *net_dev = efx->net_dev; 3887 struct netdev_hw_addr *uc; 3888 int addr_count; 3889 unsigned int i; 3890 3891 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3892 addr_count = netdev_uc_count(net_dev); 3893 if (net_dev->flags & IFF_PROMISC) 3894 *promisc = true; 3895 table->dev_uc_count = 1 + addr_count; 3896 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3897 i = 1; 3898 netdev_for_each_uc_addr(uc, net_dev) { 3899 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) { 3900 *promisc = true; 3901 break; 3902 } 3903 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3904 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3905 i++; 3906 } 3907} 3908 3909static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc) 3910{ 3911 struct efx_ef10_filter_table *table = efx->filter_state; 3912 struct net_device *net_dev = efx->net_dev; 3913 struct netdev_hw_addr *mc; 3914 unsigned int i, addr_count; 3915 3916 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3917 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3918 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 3919 *promisc = true; 3920 3921 addr_count = netdev_mc_count(net_dev); 3922 i = 0; 3923 netdev_for_each_mc_addr(mc, net_dev) { 3924 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) { 3925 *promisc = true; 3926 break; 3927 } 3928 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3929 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3930 i++; 3931 } 3932 3933 table->dev_mc_count = i; 3934} 3935 3936static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx, 3937 bool multicast, bool rollback) 3938{ 3939 struct efx_ef10_filter_table *table = efx->filter_state; 3940 struct efx_ef10_dev_addr *addr_list; 3941 enum efx_filter_flags filter_flags; 3942 struct efx_filter_spec spec; 3943 u8 baddr[ETH_ALEN]; 3944 unsigned int i, j; 3945 int addr_count; 3946 int rc; 3947 3948 if (multicast) { 3949 addr_list = table->dev_mc_list; 3950 addr_count = table->dev_mc_count; 3951 } else { 3952 addr_list = table->dev_uc_list; 3953 addr_count = table->dev_uc_count; 3954 } 3955 3956 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 3957 3958 /* Insert/renew filters */ 3959 for (i = 0; i < addr_count; i++) { 3960 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 3961 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3962 addr_list[i].addr); 3963 rc = efx_ef10_filter_insert(efx, &spec, true); 3964 if (rc < 0) { 3965 if (rollback) { 3966 netif_info(efx, drv, efx->net_dev, 3967 "efx_ef10_filter_insert failed rc=%d\n", 3968 rc); 3969 /* Fall back to promiscuous */ 3970 for (j = 0; j < i; j++) { 3971 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 3972 continue; 3973 efx_ef10_filter_remove_unsafe( 3974 efx, EFX_FILTER_PRI_AUTO, 3975 addr_list[j].id); 3976 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 3977 } 3978 return rc; 3979 } else { 3980 /* mark as not inserted, and carry on */ 3981 rc = EFX_EF10_FILTER_ID_INVALID; 3982 } 3983 } 3984 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc); 3985 } 3986 3987 if (multicast && rollback) { 3988 /* Also need an Ethernet broadcast filter */ 3989 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 3990 eth_broadcast_addr(baddr); 3991 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr); 3992 rc = efx_ef10_filter_insert(efx, &spec, true); 3993 if (rc < 0) { 3994 netif_warn(efx, drv, efx->net_dev, 3995 "Broadcast filter insert failed rc=%d\n", rc); 3996 /* Fall back to promiscuous */ 3997 for (j = 0; j < i; j++) { 3998 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 3999 continue; 4000 efx_ef10_filter_remove_unsafe( 4001 efx, EFX_FILTER_PRI_AUTO, 4002 addr_list[j].id); 4003 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 4004 } 4005 return rc; 4006 } else { 4007 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4008 } 4009 } 4010 4011 return 0; 4012} 4013 4014static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast, 4015 bool rollback) 4016{ 4017 struct efx_ef10_filter_table *table = efx->filter_state; 4018 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4019 enum efx_filter_flags filter_flags; 4020 struct efx_filter_spec spec; 4021 u8 baddr[ETH_ALEN]; 4022 int rc; 4023 4024 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4025 4026 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4027 4028 if (multicast) 4029 efx_filter_set_mc_def(&spec); 4030 else 4031 efx_filter_set_uc_def(&spec); 4032 4033 rc = efx_ef10_filter_insert(efx, &spec, true); 4034 if (rc < 0) { 4035 netif_warn(efx, drv, efx->net_dev, 4036 "%scast mismatch filter insert failed rc=%d\n", 4037 multicast ? "Multi" : "Uni", rc); 4038 } else if (multicast) { 4039 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4040 if (!nic_data->workaround_26807) { 4041 /* Also need an Ethernet broadcast filter */ 4042 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 4043 filter_flags, 0); 4044 eth_broadcast_addr(baddr); 4045 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 4046 baddr); 4047 rc = efx_ef10_filter_insert(efx, &spec, true); 4048 if (rc < 0) { 4049 netif_warn(efx, drv, efx->net_dev, 4050 "Broadcast filter insert failed rc=%d\n", 4051 rc); 4052 if (rollback) { 4053 /* Roll back the mc_def filter */ 4054 efx_ef10_filter_remove_unsafe( 4055 efx, EFX_FILTER_PRI_AUTO, 4056 table->mcdef_id); 4057 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 4058 return rc; 4059 } 4060 } else { 4061 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4062 } 4063 } 4064 rc = 0; 4065 } else { 4066 table->ucdef_id = rc; 4067 rc = 0; 4068 } 4069 return rc; 4070} 4071 4072/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD 4073 * flag or removes these filters, we don't need to hold the filter_lock while 4074 * scanning for these filters. 4075 */ 4076static void efx_ef10_filter_remove_old(struct efx_nic *efx) 4077{ 4078 struct efx_ef10_filter_table *table = efx->filter_state; 4079 bool remove_failed = false; 4080 int i; 4081 4082 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4083 if (ACCESS_ONCE(table->entry[i].spec) & 4084 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 4085 if (efx_ef10_filter_remove_internal( 4086 efx, 1U << EFX_FILTER_PRI_AUTO, 4087 i, true) < 0) 4088 remove_failed = true; 4089 } 4090 } 4091 WARN_ON(remove_failed); 4092} 4093 4094static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 4095{ 4096 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4097 u8 mac_old[ETH_ALEN]; 4098 int rc, rc2; 4099 4100 /* Only reconfigure a PF-created vport */ 4101 if (is_zero_ether_addr(nic_data->vport_mac)) 4102 return 0; 4103 4104 efx_device_detach_sync(efx); 4105 efx_net_stop(efx->net_dev); 4106 down_write(&efx->filter_sem); 4107 efx_ef10_filter_table_remove(efx); 4108 up_write(&efx->filter_sem); 4109 4110 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 4111 if (rc) 4112 goto restore_filters; 4113 4114 ether_addr_copy(mac_old, nic_data->vport_mac); 4115 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 4116 nic_data->vport_mac); 4117 if (rc) 4118 goto restore_vadaptor; 4119 4120 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 4121 efx->net_dev->dev_addr); 4122 if (!rc) { 4123 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 4124 } else { 4125 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 4126 if (rc2) { 4127 /* Failed to add original MAC, so clear vport_mac */ 4128 eth_zero_addr(nic_data->vport_mac); 4129 goto reset_nic; 4130 } 4131 } 4132 4133restore_vadaptor: 4134 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 4135 if (rc2) 4136 goto reset_nic; 4137restore_filters: 4138 down_write(&efx->filter_sem); 4139 rc2 = efx_ef10_filter_table_probe(efx); 4140 up_write(&efx->filter_sem); 4141 if (rc2) 4142 goto reset_nic; 4143 4144 rc2 = efx_net_open(efx->net_dev); 4145 if (rc2) 4146 goto reset_nic; 4147 4148 netif_device_attach(efx->net_dev); 4149 4150 return rc; 4151 4152reset_nic: 4153 netif_err(efx, drv, efx->net_dev, 4154 "Failed to restore when changing MAC address - scheduling reset\n"); 4155 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 4156 4157 return rc ? rc : rc2; 4158} 4159 4160/* Caller must hold efx->filter_sem for read if race against 4161 * efx_ef10_filter_table_remove() is possible 4162 */ 4163static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 4164{ 4165 struct efx_ef10_filter_table *table = efx->filter_state; 4166 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4167 struct net_device *net_dev = efx->net_dev; 4168 bool uc_promisc = false, mc_promisc = false; 4169 4170 if (!efx_dev_registered(efx)) 4171 return; 4172 4173 if (!table) 4174 return; 4175 4176 efx_ef10_filter_mark_old(efx); 4177 4178 /* Copy/convert the address lists; add the primary station 4179 * address and broadcast address 4180 */ 4181 netif_addr_lock_bh(net_dev); 4182 efx_ef10_filter_uc_addr_list(efx, &uc_promisc); 4183 efx_ef10_filter_mc_addr_list(efx, &mc_promisc); 4184 netif_addr_unlock_bh(net_dev); 4185 4186 /* Insert/renew unicast filters */ 4187 if (uc_promisc) { 4188 efx_ef10_filter_insert_def(efx, false, false); 4189 efx_ef10_filter_insert_addr_list(efx, false, false); 4190 } else { 4191 /* If any of the filters failed to insert, fall back to 4192 * promiscuous mode - add in the uc_def filter. But keep 4193 * our individual unicast filters. 4194 */ 4195 if (efx_ef10_filter_insert_addr_list(efx, false, false)) 4196 efx_ef10_filter_insert_def(efx, false, false); 4197 } 4198 4199 /* Insert/renew multicast filters */ 4200 /* If changing promiscuous state with cascaded multicast filters, remove 4201 * old filters first, so that packets are dropped rather than duplicated 4202 */ 4203 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc) 4204 efx_ef10_filter_remove_old(efx); 4205 if (mc_promisc) { 4206 if (nic_data->workaround_26807) { 4207 /* If we failed to insert promiscuous filters, rollback 4208 * and fall back to individual multicast filters 4209 */ 4210 if (efx_ef10_filter_insert_def(efx, true, true)) { 4211 /* Changing promisc state, so remove old filters */ 4212 efx_ef10_filter_remove_old(efx); 4213 efx_ef10_filter_insert_addr_list(efx, true, false); 4214 } 4215 } else { 4216 /* If we failed to insert promiscuous filters, don't 4217 * rollback. Regardless, also insert the mc_list 4218 */ 4219 efx_ef10_filter_insert_def(efx, true, false); 4220 efx_ef10_filter_insert_addr_list(efx, true, false); 4221 } 4222 } else { 4223 /* If any filters failed to insert, rollback and fall back to 4224 * promiscuous mode - mc_def filter and maybe broadcast. If 4225 * that fails, roll back again and insert as many of our 4226 * individual multicast filters as we can. 4227 */ 4228 if (efx_ef10_filter_insert_addr_list(efx, true, true)) { 4229 /* Changing promisc state, so remove old filters */ 4230 if (nic_data->workaround_26807) 4231 efx_ef10_filter_remove_old(efx); 4232 if (efx_ef10_filter_insert_def(efx, true, true)) 4233 efx_ef10_filter_insert_addr_list(efx, true, false); 4234 } 4235 } 4236 4237 efx_ef10_filter_remove_old(efx); 4238 efx->mc_promisc = mc_promisc; 4239} 4240 4241static int efx_ef10_set_mac_address(struct efx_nic *efx) 4242{ 4243 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 4244 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4245 bool was_enabled = efx->port_enabled; 4246 int rc; 4247 4248 efx_device_detach_sync(efx); 4249 efx_net_stop(efx->net_dev); 4250 down_write(&efx->filter_sem); 4251 efx_ef10_filter_table_remove(efx); 4252 4253 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 4254 efx->net_dev->dev_addr); 4255 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 4256 nic_data->vport_id); 4257 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 4258 sizeof(inbuf), NULL, 0, NULL); 4259 4260 efx_ef10_filter_table_probe(efx); 4261 up_write(&efx->filter_sem); 4262 if (was_enabled) 4263 efx_net_open(efx->net_dev); 4264 netif_device_attach(efx->net_dev); 4265 4266#ifdef CONFIG_SFC_SRIOV 4267 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 4268 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 4269 4270 if (rc == -EPERM) { 4271 struct efx_nic *efx_pf; 4272 4273 /* Switch to PF and change MAC address on vport */ 4274 efx_pf = pci_get_drvdata(pci_dev_pf); 4275 4276 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 4277 nic_data->vf_index, 4278 efx->net_dev->dev_addr); 4279 } else if (!rc) { 4280 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 4281 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 4282 unsigned int i; 4283 4284 /* MAC address successfully changed by VF (with MAC 4285 * spoofing) so update the parent PF if possible. 4286 */ 4287 for (i = 0; i < efx_pf->vf_count; ++i) { 4288 struct ef10_vf *vf = nic_data->vf + i; 4289 4290 if (vf->efx == efx) { 4291 ether_addr_copy(vf->mac, 4292 efx->net_dev->dev_addr); 4293 return 0; 4294 } 4295 } 4296 } 4297 } else 4298#endif 4299 if (rc == -EPERM) { 4300 netif_err(efx, drv, efx->net_dev, 4301 "Cannot change MAC address; use sfboot to enable" 4302 " mac-spoofing on this interface\n"); 4303 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 4304 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 4305 * fall-back to the method of changing the MAC address on the 4306 * vport. This only applies to PFs because such versions of 4307 * MCFW do not support VFs. 4308 */ 4309 rc = efx_ef10_vport_set_mac_address(efx); 4310 } else { 4311 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 4312 sizeof(inbuf), NULL, 0, rc); 4313 } 4314 4315 return rc; 4316} 4317 4318static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 4319{ 4320 efx_ef10_filter_sync_rx_mode(efx); 4321 4322 return efx_mcdi_set_mac(efx); 4323} 4324 4325static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 4326{ 4327 efx_ef10_filter_sync_rx_mode(efx); 4328 4329 return 0; 4330} 4331 4332static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 4333{ 4334 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 4335 4336 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 4337 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 4338 NULL, 0, NULL); 4339} 4340 4341/* MC BISTs follow a different poll mechanism to phy BISTs. 4342 * The BIST is done in the poll handler on the MC, and the MCDI command 4343 * will block until the BIST is done. 4344 */ 4345static int efx_ef10_poll_bist(struct efx_nic *efx) 4346{ 4347 int rc; 4348 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 4349 size_t outlen; 4350 u32 result; 4351 4352 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 4353 outbuf, sizeof(outbuf), &outlen); 4354 if (rc != 0) 4355 return rc; 4356 4357 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 4358 return -EIO; 4359 4360 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 4361 switch (result) { 4362 case MC_CMD_POLL_BIST_PASSED: 4363 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 4364 return 0; 4365 case MC_CMD_POLL_BIST_TIMEOUT: 4366 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 4367 return -EIO; 4368 case MC_CMD_POLL_BIST_FAILED: 4369 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 4370 return -EIO; 4371 default: 4372 netif_err(efx, hw, efx->net_dev, 4373 "BIST returned unknown result %u", result); 4374 return -EIO; 4375 } 4376} 4377 4378static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 4379{ 4380 int rc; 4381 4382 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 4383 4384 rc = efx_ef10_start_bist(efx, bist_type); 4385 if (rc != 0) 4386 return rc; 4387 4388 return efx_ef10_poll_bist(efx); 4389} 4390 4391static int 4392efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 4393{ 4394 int rc, rc2; 4395 4396 efx_reset_down(efx, RESET_TYPE_WORLD); 4397 4398 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 4399 NULL, 0, NULL, 0, NULL); 4400 if (rc != 0) 4401 goto out; 4402 4403 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 4404 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 4405 4406 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 4407 4408out: 4409 if (rc == -EPERM) 4410 rc = 0; 4411 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 4412 return rc ? rc : rc2; 4413} 4414 4415#ifdef CONFIG_SFC_MTD 4416 4417struct efx_ef10_nvram_type_info { 4418 u16 type, type_mask; 4419 u8 port; 4420 const char *name; 4421}; 4422 4423static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 4424 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 4425 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 4426 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 4427 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 4428 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 4429 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 4430 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 4431 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 4432 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 4433 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 4434 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 4435}; 4436 4437static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 4438 struct efx_mcdi_mtd_partition *part, 4439 unsigned int type) 4440{ 4441 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 4442 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 4443 const struct efx_ef10_nvram_type_info *info; 4444 size_t size, erase_size, outlen; 4445 bool protected; 4446 int rc; 4447 4448 for (info = efx_ef10_nvram_types; ; info++) { 4449 if (info == 4450 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 4451 return -ENODEV; 4452 if ((type & ~info->type_mask) == info->type) 4453 break; 4454 } 4455 if (info->port != efx_port_num(efx)) 4456 return -ENODEV; 4457 4458 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 4459 if (rc) 4460 return rc; 4461 if (protected) 4462 return -ENODEV; /* hide it */ 4463 4464 part->nvram_type = type; 4465 4466 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 4467 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 4468 outbuf, sizeof(outbuf), &outlen); 4469 if (rc) 4470 return rc; 4471 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 4472 return -EIO; 4473 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 4474 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 4475 part->fw_subtype = MCDI_DWORD(outbuf, 4476 NVRAM_METADATA_OUT_SUBTYPE); 4477 4478 part->common.dev_type_name = "EF10 NVRAM manager"; 4479 part->common.type_name = info->name; 4480 4481 part->common.mtd.type = MTD_NORFLASH; 4482 part->common.mtd.flags = MTD_CAP_NORFLASH; 4483 part->common.mtd.size = size; 4484 part->common.mtd.erasesize = erase_size; 4485 4486 return 0; 4487} 4488 4489static int efx_ef10_mtd_probe(struct efx_nic *efx) 4490{ 4491 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 4492 struct efx_mcdi_mtd_partition *parts; 4493 size_t outlen, n_parts_total, i, n_parts; 4494 unsigned int type; 4495 int rc; 4496 4497 ASSERT_RTNL(); 4498 4499 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 4500 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 4501 outbuf, sizeof(outbuf), &outlen); 4502 if (rc) 4503 return rc; 4504 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 4505 return -EIO; 4506 4507 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 4508 if (n_parts_total > 4509 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 4510 return -EIO; 4511 4512 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 4513 if (!parts) 4514 return -ENOMEM; 4515 4516 n_parts = 0; 4517 for (i = 0; i < n_parts_total; i++) { 4518 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 4519 i); 4520 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 4521 if (rc == 0) 4522 n_parts++; 4523 else if (rc != -ENODEV) 4524 goto fail; 4525 } 4526 4527 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 4528fail: 4529 if (rc) 4530 kfree(parts); 4531 return rc; 4532} 4533 4534#endif /* CONFIG_SFC_MTD */ 4535 4536static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 4537{ 4538 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 4539} 4540 4541static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 4542 u32 host_time) {} 4543 4544static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 4545 bool temp) 4546{ 4547 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 4548 int rc; 4549 4550 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 4551 channel->sync_events_state == SYNC_EVENTS_VALID || 4552 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 4553 return 0; 4554 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 4555 4556 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 4557 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4558 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 4559 channel->channel); 4560 4561 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4562 inbuf, sizeof(inbuf), NULL, 0, NULL); 4563 4564 if (rc != 0) 4565 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4566 SYNC_EVENTS_DISABLED; 4567 4568 return rc; 4569} 4570 4571static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 4572 bool temp) 4573{ 4574 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 4575 int rc; 4576 4577 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 4578 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 4579 return 0; 4580 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 4581 channel->sync_events_state = SYNC_EVENTS_DISABLED; 4582 return 0; 4583 } 4584 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4585 SYNC_EVENTS_DISABLED; 4586 4587 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 4588 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4589 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 4590 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 4591 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 4592 channel->channel); 4593 4594 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4595 inbuf, sizeof(inbuf), NULL, 0, NULL); 4596 4597 return rc; 4598} 4599 4600static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 4601 bool temp) 4602{ 4603 int (*set)(struct efx_channel *channel, bool temp); 4604 struct efx_channel *channel; 4605 4606 set = en ? 4607 efx_ef10_rx_enable_timestamping : 4608 efx_ef10_rx_disable_timestamping; 4609 4610 efx_for_each_channel(channel, efx) { 4611 int rc = set(channel, temp); 4612 if (en && rc != 0) { 4613 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 4614 return rc; 4615 } 4616 } 4617 4618 return 0; 4619} 4620 4621static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 4622 struct hwtstamp_config *init) 4623{ 4624 return -EOPNOTSUPP; 4625} 4626 4627static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 4628 struct hwtstamp_config *init) 4629{ 4630 int rc; 4631 4632 switch (init->rx_filter) { 4633 case HWTSTAMP_FILTER_NONE: 4634 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 4635 /* if TX timestamping is still requested then leave PTP on */ 4636 return efx_ptp_change_mode(efx, 4637 init->tx_type != HWTSTAMP_TX_OFF, 0); 4638 case HWTSTAMP_FILTER_ALL: 4639 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4640 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4641 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4642 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4643 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4644 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4645 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4647 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4648 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4649 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4650 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4651 init->rx_filter = HWTSTAMP_FILTER_ALL; 4652 rc = efx_ptp_change_mode(efx, true, 0); 4653 if (!rc) 4654 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 4655 if (rc) 4656 efx_ptp_change_mode(efx, false, 0); 4657 return rc; 4658 default: 4659 return -ERANGE; 4660 } 4661} 4662 4663const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4664 .is_vf = true, 4665 .mem_bar = EFX_MEM_VF_BAR, 4666 .mem_map_size = efx_ef10_mem_map_size, 4667 .probe = efx_ef10_probe_vf, 4668 .remove = efx_ef10_remove, 4669 .dimension_resources = efx_ef10_dimension_resources, 4670 .init = efx_ef10_init_nic, 4671 .fini = efx_port_dummy_op_void, 4672 .map_reset_reason = efx_ef10_map_reset_reason, 4673 .map_reset_flags = efx_ef10_map_reset_flags, 4674 .reset = efx_ef10_reset, 4675 .probe_port = efx_mcdi_port_probe, 4676 .remove_port = efx_mcdi_port_remove, 4677 .fini_dmaq = efx_ef10_fini_dmaq, 4678 .prepare_flr = efx_ef10_prepare_flr, 4679 .finish_flr = efx_port_dummy_op_void, 4680 .describe_stats = efx_ef10_describe_stats, 4681 .update_stats = efx_ef10_update_stats_vf, 4682 .start_stats = efx_port_dummy_op_void, 4683 .pull_stats = efx_port_dummy_op_void, 4684 .stop_stats = efx_port_dummy_op_void, 4685 .set_id_led = efx_mcdi_set_id_led, 4686 .push_irq_moderation = efx_ef10_push_irq_moderation, 4687 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 4688 .check_mac_fault = efx_mcdi_mac_check_fault, 4689 .reconfigure_port = efx_mcdi_port_reconfigure, 4690 .get_wol = efx_ef10_get_wol_vf, 4691 .set_wol = efx_ef10_set_wol_vf, 4692 .resume_wol = efx_port_dummy_op_void, 4693 .mcdi_request = efx_ef10_mcdi_request, 4694 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4695 .mcdi_read_response = efx_ef10_mcdi_read_response, 4696 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4697 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4698 .irq_enable_master = efx_port_dummy_op_void, 4699 .irq_test_generate = efx_ef10_irq_test_generate, 4700 .irq_disable_non_ev = efx_port_dummy_op_void, 4701 .irq_handle_msi = efx_ef10_msi_interrupt, 4702 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4703 .tx_probe = efx_ef10_tx_probe, 4704 .tx_init = efx_ef10_tx_init, 4705 .tx_remove = efx_ef10_tx_remove, 4706 .tx_write = efx_ef10_tx_write, 4707 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 4708 .rx_probe = efx_ef10_rx_probe, 4709 .rx_init = efx_ef10_rx_init, 4710 .rx_remove = efx_ef10_rx_remove, 4711 .rx_write = efx_ef10_rx_write, 4712 .rx_defer_refill = efx_ef10_rx_defer_refill, 4713 .ev_probe = efx_ef10_ev_probe, 4714 .ev_init = efx_ef10_ev_init, 4715 .ev_fini = efx_ef10_ev_fini, 4716 .ev_remove = efx_ef10_ev_remove, 4717 .ev_process = efx_ef10_ev_process, 4718 .ev_read_ack = efx_ef10_ev_read_ack, 4719 .ev_test_generate = efx_ef10_ev_test_generate, 4720 .filter_table_probe = efx_ef10_filter_table_probe, 4721 .filter_table_restore = efx_ef10_filter_table_restore, 4722 .filter_table_remove = efx_ef10_filter_table_remove, 4723 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4724 .filter_insert = efx_ef10_filter_insert, 4725 .filter_remove_safe = efx_ef10_filter_remove_safe, 4726 .filter_get_safe = efx_ef10_filter_get_safe, 4727 .filter_clear_rx = efx_ef10_filter_clear_rx, 4728 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4729 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4730 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4731#ifdef CONFIG_RFS_ACCEL 4732 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4733 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4734#endif 4735#ifdef CONFIG_SFC_MTD 4736 .mtd_probe = efx_port_dummy_op_int, 4737#endif 4738 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4739 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4740#ifdef CONFIG_SFC_SRIOV 4741 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4742 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4743 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4744 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 4745#endif 4746 .get_mac_address = efx_ef10_get_mac_address_vf, 4747 .set_mac_address = efx_ef10_set_mac_address, 4748 4749 .revision = EFX_REV_HUNT_A0, 4750 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4751 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4752 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4753 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4754 .can_rx_scatter = true, 4755 .always_rx_scatter = true, 4756 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4757 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4758 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4759 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4760 .mcdi_max_ver = 2, 4761 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4762 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4763 1 << HWTSTAMP_FILTER_ALL, 4764}; 4765 4766const struct efx_nic_type efx_hunt_a0_nic_type = { 4767 .is_vf = false, 4768 .mem_bar = EFX_MEM_BAR, 4769 .mem_map_size = efx_ef10_mem_map_size, 4770 .probe = efx_ef10_probe_pf, 4771 .remove = efx_ef10_remove, 4772 .dimension_resources = efx_ef10_dimension_resources, 4773 .init = efx_ef10_init_nic, 4774 .fini = efx_port_dummy_op_void, 4775 .map_reset_reason = efx_ef10_map_reset_reason, 4776 .map_reset_flags = efx_ef10_map_reset_flags, 4777 .reset = efx_ef10_reset, 4778 .probe_port = efx_mcdi_port_probe, 4779 .remove_port = efx_mcdi_port_remove, 4780 .fini_dmaq = efx_ef10_fini_dmaq, 4781 .prepare_flr = efx_ef10_prepare_flr, 4782 .finish_flr = efx_port_dummy_op_void, 4783 .describe_stats = efx_ef10_describe_stats, 4784 .update_stats = efx_ef10_update_stats_pf, 4785 .start_stats = efx_mcdi_mac_start_stats, 4786 .pull_stats = efx_mcdi_mac_pull_stats, 4787 .stop_stats = efx_mcdi_mac_stop_stats, 4788 .set_id_led = efx_mcdi_set_id_led, 4789 .push_irq_moderation = efx_ef10_push_irq_moderation, 4790 .reconfigure_mac = efx_ef10_mac_reconfigure, 4791 .check_mac_fault = efx_mcdi_mac_check_fault, 4792 .reconfigure_port = efx_mcdi_port_reconfigure, 4793 .get_wol = efx_ef10_get_wol, 4794 .set_wol = efx_ef10_set_wol, 4795 .resume_wol = efx_port_dummy_op_void, 4796 .test_chip = efx_ef10_test_chip, 4797 .test_nvram = efx_mcdi_nvram_test_all, 4798 .mcdi_request = efx_ef10_mcdi_request, 4799 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4800 .mcdi_read_response = efx_ef10_mcdi_read_response, 4801 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4802 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4803 .irq_enable_master = efx_port_dummy_op_void, 4804 .irq_test_generate = efx_ef10_irq_test_generate, 4805 .irq_disable_non_ev = efx_port_dummy_op_void, 4806 .irq_handle_msi = efx_ef10_msi_interrupt, 4807 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4808 .tx_probe = efx_ef10_tx_probe, 4809 .tx_init = efx_ef10_tx_init, 4810 .tx_remove = efx_ef10_tx_remove, 4811 .tx_write = efx_ef10_tx_write, 4812 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 4813 .rx_probe = efx_ef10_rx_probe, 4814 .rx_init = efx_ef10_rx_init, 4815 .rx_remove = efx_ef10_rx_remove, 4816 .rx_write = efx_ef10_rx_write, 4817 .rx_defer_refill = efx_ef10_rx_defer_refill, 4818 .ev_probe = efx_ef10_ev_probe, 4819 .ev_init = efx_ef10_ev_init, 4820 .ev_fini = efx_ef10_ev_fini, 4821 .ev_remove = efx_ef10_ev_remove, 4822 .ev_process = efx_ef10_ev_process, 4823 .ev_read_ack = efx_ef10_ev_read_ack, 4824 .ev_test_generate = efx_ef10_ev_test_generate, 4825 .filter_table_probe = efx_ef10_filter_table_probe, 4826 .filter_table_restore = efx_ef10_filter_table_restore, 4827 .filter_table_remove = efx_ef10_filter_table_remove, 4828 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4829 .filter_insert = efx_ef10_filter_insert, 4830 .filter_remove_safe = efx_ef10_filter_remove_safe, 4831 .filter_get_safe = efx_ef10_filter_get_safe, 4832 .filter_clear_rx = efx_ef10_filter_clear_rx, 4833 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4834 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4835 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4836#ifdef CONFIG_RFS_ACCEL 4837 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4838 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4839#endif 4840#ifdef CONFIG_SFC_MTD 4841 .mtd_probe = efx_ef10_mtd_probe, 4842 .mtd_rename = efx_mcdi_mtd_rename, 4843 .mtd_read = efx_mcdi_mtd_read, 4844 .mtd_erase = efx_mcdi_mtd_erase, 4845 .mtd_write = efx_mcdi_mtd_write, 4846 .mtd_sync = efx_mcdi_mtd_sync, 4847#endif 4848 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4849 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4850 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4851#ifdef CONFIG_SFC_SRIOV 4852 .sriov_configure = efx_ef10_sriov_configure, 4853 .sriov_init = efx_ef10_sriov_init, 4854 .sriov_fini = efx_ef10_sriov_fini, 4855 .sriov_wanted = efx_ef10_sriov_wanted, 4856 .sriov_reset = efx_ef10_sriov_reset, 4857 .sriov_flr = efx_ef10_sriov_flr, 4858 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4859 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4860 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4861 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4862 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4863 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4864 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4865 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4866#endif 4867 .get_mac_address = efx_ef10_get_mac_address_pf, 4868 .set_mac_address = efx_ef10_set_mac_address, 4869 4870 .revision = EFX_REV_HUNT_A0, 4871 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4872 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4873 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4874 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4875 .can_rx_scatter = true, 4876 .always_rx_scatter = true, 4877 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4878 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4879 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4880 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4881 .mcdi_max_ver = 2, 4882 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4883 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4884 1 << HWTSTAMP_FILTER_ALL, 4885}; 4886