1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/io-mapping.h>
36#include <linux/mlx5/driver.h>
37#include <linux/mlx5/cmd.h>
38#include "mlx5_core.h"
39
40enum {
41	NUM_DRIVER_UARS		= 4,
42	NUM_LOW_LAT_UUARS	= 4,
43};
44
45
46struct mlx5_alloc_uar_mbox_in {
47	struct mlx5_inbox_hdr	hdr;
48	u8			rsvd[8];
49};
50
51struct mlx5_alloc_uar_mbox_out {
52	struct mlx5_outbox_hdr	hdr;
53	__be32			uarn;
54	u8			rsvd[4];
55};
56
57struct mlx5_free_uar_mbox_in {
58	struct mlx5_inbox_hdr	hdr;
59	__be32			uarn;
60	u8			rsvd[4];
61};
62
63struct mlx5_free_uar_mbox_out {
64	struct mlx5_outbox_hdr	hdr;
65	u8			rsvd[8];
66};
67
68int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn)
69{
70	struct mlx5_alloc_uar_mbox_in	in;
71	struct mlx5_alloc_uar_mbox_out	out;
72	int err;
73
74	memset(&in, 0, sizeof(in));
75	memset(&out, 0, sizeof(out));
76	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ALLOC_UAR);
77	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
78	if (err)
79		goto ex;
80
81	if (out.hdr.status) {
82		err = mlx5_cmd_status_to_err(&out.hdr);
83		goto ex;
84	}
85
86	*uarn = be32_to_cpu(out.uarn) & 0xffffff;
87
88ex:
89	return err;
90}
91EXPORT_SYMBOL(mlx5_cmd_alloc_uar);
92
93int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
94{
95	struct mlx5_free_uar_mbox_in	in;
96	struct mlx5_free_uar_mbox_out	out;
97	int err;
98
99	memset(&in, 0, sizeof(in));
100	memset(&out, 0, sizeof(out));
101	in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DEALLOC_UAR);
102	in.uarn = cpu_to_be32(uarn);
103	err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
104	if (err)
105		goto ex;
106
107	if (out.hdr.status)
108		err = mlx5_cmd_status_to_err(&out.hdr);
109
110ex:
111	return err;
112}
113EXPORT_SYMBOL(mlx5_cmd_free_uar);
114
115static int need_uuar_lock(int uuarn)
116{
117	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
118
119	if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS)
120		return 0;
121
122	return 1;
123}
124
125int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
126{
127	int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
128	struct mlx5_bf *bf;
129	phys_addr_t addr;
130	int err;
131	int i;
132
133	uuari->num_uars = NUM_DRIVER_UARS;
134	uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;
135
136	mutex_init(&uuari->lock);
137	uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
138	if (!uuari->uars)
139		return -ENOMEM;
140
141	uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
142	if (!uuari->bfs) {
143		err = -ENOMEM;
144		goto out_uars;
145	}
146
147	uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
148				GFP_KERNEL);
149	if (!uuari->bitmap) {
150		err = -ENOMEM;
151		goto out_bfs;
152	}
153
154	uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
155	if (!uuari->count) {
156		err = -ENOMEM;
157		goto out_bitmap;
158	}
159
160	for (i = 0; i < uuari->num_uars; i++) {
161		err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
162		if (err)
163			goto out_count;
164
165		addr = dev->iseg_base + ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
166		uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
167		if (!uuari->uars[i].map) {
168			mlx5_cmd_free_uar(dev, uuari->uars[i].index);
169			err = -ENOMEM;
170			goto out_count;
171		}
172		mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
173			      uuari->uars[i].index, uuari->uars[i].map);
174	}
175
176	for (i = 0; i < tot_uuars; i++) {
177		bf = &uuari->bfs[i];
178
179		bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2;
180		bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
181		bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
182		bf->reg = NULL; /* Add WC support */
183		bf->offset = (i % MLX5_BF_REGS_PER_PAGE) *
184			     (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) +
185			     MLX5_BF_OFFSET;
186		bf->need_lock = need_uuar_lock(i);
187		spin_lock_init(&bf->lock);
188		spin_lock_init(&bf->lock32);
189		bf->uuarn = i;
190	}
191
192	return 0;
193
194out_count:
195	for (i--; i >= 0; i--) {
196		iounmap(uuari->uars[i].map);
197		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
198	}
199	kfree(uuari->count);
200
201out_bitmap:
202	kfree(uuari->bitmap);
203
204out_bfs:
205	kfree(uuari->bfs);
206
207out_uars:
208	kfree(uuari->uars);
209	return err;
210}
211
212int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
213{
214	int i = uuari->num_uars;
215
216	for (i--; i >= 0; i--) {
217		iounmap(uuari->uars[i].map);
218		mlx5_cmd_free_uar(dev, uuari->uars[i].index);
219	}
220
221	kfree(uuari->count);
222	kfree(uuari->bitmap);
223	kfree(uuari->bfs);
224	kfree(uuari->uars);
225
226	return 0;
227}
228
229int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
230{
231	phys_addr_t pfn;
232	phys_addr_t uar_bar_start;
233	int err;
234
235	err = mlx5_cmd_alloc_uar(mdev, &uar->index);
236	if (err) {
237		mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
238		return err;
239	}
240
241	uar_bar_start = pci_resource_start(mdev->pdev, 0);
242	pfn           = (uar_bar_start >> PAGE_SHIFT) + uar->index;
243	uar->map      = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
244	if (!uar->map) {
245		mlx5_core_warn(mdev, "ioremap() failed, %d\n", err);
246		err = -ENOMEM;
247		goto err_free_uar;
248	}
249
250	if (mdev->priv.bf_mapping)
251		uar->bf_map = io_mapping_map_wc(mdev->priv.bf_mapping,
252						uar->index << PAGE_SHIFT);
253
254	return 0;
255
256err_free_uar:
257	mlx5_cmd_free_uar(mdev, uar->index);
258
259	return err;
260}
261EXPORT_SYMBOL(mlx5_alloc_map_uar);
262
263void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
264{
265	io_mapping_unmap(uar->bf_map);
266	iounmap(uar->map);
267	mlx5_cmd_free_uar(mdev, uar->index);
268}
269EXPORT_SYMBOL(mlx5_unmap_free_uar);
270