1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 *     Inc. unless otherwise expressly agreed to in writing between Synopsys
29 *     and you.
30 *
31 *     The Software IS NOT an item of Licensed Software or Licensed Product
32 *     under any End User Software License Agreement or Agreement for Licensed
33 *     Product with Synopsys or any supplement thereto.  Permission is hereby
34 *     granted, free of charge, to any person obtaining a copy of this software
35 *     annotated with this license and the Software, to deal in the Software
36 *     without restriction, including without limitation the rights to use,
37 *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 *     of the Software, and to permit persons to whom the Software is furnished
39 *     to do so, subject to the following conditions:
40 *
41 *     The above copyright notice and this permission notice shall be included
42 *     in all copies or substantial portions of the Software.
43 *
44 *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 *     THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 *     * Redistributions of source code must retain the above copyright
65 *       notice, this list of conditions and the following disclaimer.
66 *     * Redistributions in binary form must reproduce the above copyright
67 *       notice, this list of conditions and the following disclaimer in the
68 *       documentation and/or other materials provided with the distribution.
69 *     * Neither the name of Advanced Micro Devices, Inc. nor the
70 *       names of its contributors may be used to endorse or promote products
71 *       derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 *     Inc. unless otherwise expressly agreed to in writing between Synopsys
89 *     and you.
90 *
91 *     The Software IS NOT an item of Licensed Software or Licensed Product
92 *     under any End User Software License Agreement or Agreement for Licensed
93 *     Product with Synopsys or any supplement thereto.  Permission is hereby
94 *     granted, free of charge, to any person obtaining a copy of this software
95 *     annotated with this license and the Software, to deal in the Software
96 *     without restriction, including without limitation the rights to use,
97 *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 *     of the Software, and to permit persons to whom the Software is furnished
99 *     to do so, subject to the following conditions:
100 *
101 *     The above copyright notice and this permission notice shall be included
102 *     in all copies or substantial portions of the Software.
103 *
104 *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 *     THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
118#include <linux/kmod.h>
119#include <linux/mdio.h>
120#include <linux/phy.h>
121#include <linux/of.h>
122#include <linux/bitops.h>
123#include <linux/jiffies.h>
124
125#include "xgbe.h"
126#include "xgbe-common.h"
127
128static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata)
129{
130	unsigned int reg;
131
132	reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
133
134	reg |= XGBE_KR_TRAINING_ENABLE;
135	XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
136}
137
138static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata)
139{
140	unsigned int reg;
141
142	reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
143
144	reg &= ~XGBE_KR_TRAINING_ENABLE;
145	XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
146}
147
148static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata)
149{
150	unsigned int reg;
151
152	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
153
154	reg |= MDIO_CTRL1_LPOWER;
155	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
156
157	usleep_range(75, 100);
158
159	reg &= ~MDIO_CTRL1_LPOWER;
160	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
161}
162
163static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata)
164{
165	/* Assert Rx and Tx ratechange */
166	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
167}
168
169static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata)
170{
171	unsigned int wait;
172	u16 status;
173
174	/* Release Rx and Tx ratechange */
175	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
176
177	/* Wait for Rx and Tx ready */
178	wait = XGBE_RATECHANGE_COUNT;
179	while (wait--) {
180		usleep_range(50, 75);
181
182		status = XSIR0_IOREAD(pdata, SIR0_STATUS);
183		if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
184		    XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
185			goto rx_reset;
186	}
187
188	netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",
189		  status);
190
191rx_reset:
192	/* Perform Rx reset for the DFE changes */
193	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
194	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
195}
196
197static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata)
198{
199	unsigned int reg;
200
201	/* Enable KR training */
202	xgbe_an_enable_kr_training(pdata);
203
204	/* Set MAC to 10G speed */
205	pdata->hw_if.set_xgmii_speed(pdata);
206
207	/* Set PCS to KR/10G speed */
208	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
209	reg &= ~MDIO_PCS_CTRL2_TYPE;
210	reg |= MDIO_PCS_CTRL2_10GBR;
211	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
212
213	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
214	reg &= ~MDIO_CTRL1_SPEEDSEL;
215	reg |= MDIO_CTRL1_SPEED10G;
216	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
217
218	xgbe_pcs_power_cycle(pdata);
219
220	/* Set SerDes to 10G speed */
221	xgbe_serdes_start_ratechange(pdata);
222
223	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
224	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
225	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
226
227	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
228			   pdata->serdes_cdr_rate[XGBE_SPEED_10000]);
229	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
230			   pdata->serdes_tx_amp[XGBE_SPEED_10000]);
231	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
232			   pdata->serdes_blwc[XGBE_SPEED_10000]);
233	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
234			   pdata->serdes_pq_skew[XGBE_SPEED_10000]);
235	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
236			   pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]);
237	XRXTX_IOWRITE(pdata, RXTX_REG22,
238		      pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]);
239
240	xgbe_serdes_complete_ratechange(pdata);
241
242	netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
243}
244
245static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata)
246{
247	unsigned int reg;
248
249	/* Disable KR training */
250	xgbe_an_disable_kr_training(pdata);
251
252	/* Set MAC to 2.5G speed */
253	pdata->hw_if.set_gmii_2500_speed(pdata);
254
255	/* Set PCS to KX/1G speed */
256	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
257	reg &= ~MDIO_PCS_CTRL2_TYPE;
258	reg |= MDIO_PCS_CTRL2_10GBX;
259	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
260
261	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
262	reg &= ~MDIO_CTRL1_SPEEDSEL;
263	reg |= MDIO_CTRL1_SPEED1G;
264	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
265
266	xgbe_pcs_power_cycle(pdata);
267
268	/* Set SerDes to 2.5G speed */
269	xgbe_serdes_start_ratechange(pdata);
270
271	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
272	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
273	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
274
275	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
276			   pdata->serdes_cdr_rate[XGBE_SPEED_2500]);
277	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
278			   pdata->serdes_tx_amp[XGBE_SPEED_2500]);
279	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
280			   pdata->serdes_blwc[XGBE_SPEED_2500]);
281	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
282			   pdata->serdes_pq_skew[XGBE_SPEED_2500]);
283	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
284			   pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]);
285	XRXTX_IOWRITE(pdata, RXTX_REG22,
286		      pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]);
287
288	xgbe_serdes_complete_ratechange(pdata);
289
290	netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
291}
292
293static void xgbe_gmii_mode(struct xgbe_prv_data *pdata)
294{
295	unsigned int reg;
296
297	/* Disable KR training */
298	xgbe_an_disable_kr_training(pdata);
299
300	/* Set MAC to 1G speed */
301	pdata->hw_if.set_gmii_speed(pdata);
302
303	/* Set PCS to KX/1G speed */
304	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
305	reg &= ~MDIO_PCS_CTRL2_TYPE;
306	reg |= MDIO_PCS_CTRL2_10GBX;
307	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
308
309	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
310	reg &= ~MDIO_CTRL1_SPEEDSEL;
311	reg |= MDIO_CTRL1_SPEED1G;
312	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
313
314	xgbe_pcs_power_cycle(pdata);
315
316	/* Set SerDes to 1G speed */
317	xgbe_serdes_start_ratechange(pdata);
318
319	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
320	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
321	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
322
323	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
324			   pdata->serdes_cdr_rate[XGBE_SPEED_1000]);
325	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
326			   pdata->serdes_tx_amp[XGBE_SPEED_1000]);
327	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
328			   pdata->serdes_blwc[XGBE_SPEED_1000]);
329	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
330			   pdata->serdes_pq_skew[XGBE_SPEED_1000]);
331	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
332			   pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]);
333	XRXTX_IOWRITE(pdata, RXTX_REG22,
334		      pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]);
335
336	xgbe_serdes_complete_ratechange(pdata);
337
338	netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
339}
340
341static void xgbe_cur_mode(struct xgbe_prv_data *pdata,
342			  enum xgbe_mode *mode)
343{
344	unsigned int reg;
345
346	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
347	if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
348		*mode = XGBE_MODE_KR;
349	else
350		*mode = XGBE_MODE_KX;
351}
352
353static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
354{
355	enum xgbe_mode mode;
356
357	xgbe_cur_mode(pdata, &mode);
358
359	return (mode == XGBE_MODE_KR);
360}
361
362static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
363{
364	/* If we are in KR switch to KX, and vice-versa */
365	if (xgbe_in_kr_mode(pdata)) {
366		if (pdata->speed_set == XGBE_SPEEDSET_1000_10000)
367			xgbe_gmii_mode(pdata);
368		else
369			xgbe_gmii_2500_mode(pdata);
370	} else {
371		xgbe_xgmii_mode(pdata);
372	}
373}
374
375static void xgbe_set_mode(struct xgbe_prv_data *pdata,
376			  enum xgbe_mode mode)
377{
378	enum xgbe_mode cur_mode;
379
380	xgbe_cur_mode(pdata, &cur_mode);
381	if (mode != cur_mode)
382		xgbe_switch_mode(pdata);
383}
384
385static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata)
386{
387	if (pdata->phy.autoneg == AUTONEG_ENABLE) {
388		if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
389			return true;
390	} else {
391		if (pdata->phy.speed == SPEED_10000)
392			return true;
393	}
394
395	return false;
396}
397
398static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata)
399{
400	if (pdata->phy.autoneg == AUTONEG_ENABLE) {
401		if (pdata->phy.advertising & ADVERTISED_2500baseX_Full)
402			return true;
403	} else {
404		if (pdata->phy.speed == SPEED_2500)
405			return true;
406	}
407
408	return false;
409}
410
411static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata)
412{
413	if (pdata->phy.autoneg == AUTONEG_ENABLE) {
414		if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full)
415			return true;
416	} else {
417		if (pdata->phy.speed == SPEED_1000)
418			return true;
419	}
420
421	return false;
422}
423
424static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart)
425{
426	unsigned int reg;
427
428	reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
429	reg &= ~MDIO_AN_CTRL1_ENABLE;
430
431	if (enable)
432		reg |= MDIO_AN_CTRL1_ENABLE;
433
434	if (restart)
435		reg |= MDIO_AN_CTRL1_RESTART;
436
437	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
438}
439
440static void xgbe_restart_an(struct xgbe_prv_data *pdata)
441{
442	xgbe_set_an(pdata, true, true);
443
444	netif_dbg(pdata, link, pdata->netdev, "AN enabled/restarted\n");
445}
446
447static void xgbe_disable_an(struct xgbe_prv_data *pdata)
448{
449	xgbe_set_an(pdata, false, false);
450
451	netif_dbg(pdata, link, pdata->netdev, "AN disabled\n");
452}
453
454static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata,
455					enum xgbe_rx *state)
456{
457	unsigned int ad_reg, lp_reg, reg;
458
459	*state = XGBE_RX_COMPLETE;
460
461	/* If we're not in KR mode then we're done */
462	if (!xgbe_in_kr_mode(pdata))
463		return XGBE_AN_PAGE_RECEIVED;
464
465	/* Enable/Disable FEC */
466	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
467	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
468
469	reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
470	reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
471	if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
472		reg |= pdata->fec_ability;
473
474	XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
475
476	/* Start KR training */
477	reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
478	if (reg & XGBE_KR_TRAINING_ENABLE) {
479		XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
480
481		reg |= XGBE_KR_TRAINING_START;
482		XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
483			    reg);
484
485		XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
486
487		netif_dbg(pdata, link, pdata->netdev,
488			  "KR training initiated\n");
489	}
490
491	return XGBE_AN_PAGE_RECEIVED;
492}
493
494static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata,
495				   enum xgbe_rx *state)
496{
497	u16 msg;
498
499	*state = XGBE_RX_XNP;
500
501	msg = XGBE_XNP_MCF_NULL_MESSAGE;
502	msg |= XGBE_XNP_MP_FORMATTED;
503
504	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
505	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
506	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
507
508	return XGBE_AN_PAGE_RECEIVED;
509}
510
511static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata,
512				   enum xgbe_rx *state)
513{
514	unsigned int link_support;
515	unsigned int reg, ad_reg, lp_reg;
516
517	/* Read Base Ability register 2 first */
518	reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
519
520	/* Check for a supported mode, otherwise restart in a different one */
521	link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
522	if (!(reg & link_support))
523		return XGBE_AN_INCOMPAT_LINK;
524
525	/* Check Extended Next Page support */
526	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
527	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
528
529	return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
530		(lp_reg & XGBE_XNP_NP_EXCHANGE))
531	       ? xgbe_an_tx_xnp(pdata, state)
532	       : xgbe_an_tx_training(pdata, state);
533}
534
535static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata,
536				   enum xgbe_rx *state)
537{
538	unsigned int ad_reg, lp_reg;
539
540	/* Check Extended Next Page support */
541	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
542	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
543
544	return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
545		(lp_reg & XGBE_XNP_NP_EXCHANGE))
546	       ? xgbe_an_tx_xnp(pdata, state)
547	       : xgbe_an_tx_training(pdata, state);
548}
549
550static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata)
551{
552	enum xgbe_rx *state;
553	unsigned long an_timeout;
554	enum xgbe_an ret;
555
556	if (!pdata->an_start) {
557		pdata->an_start = jiffies;
558	} else {
559		an_timeout = pdata->an_start +
560			     msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
561		if (time_after(jiffies, an_timeout)) {
562			/* Auto-negotiation timed out, reset state */
563			pdata->kr_state = XGBE_RX_BPA;
564			pdata->kx_state = XGBE_RX_BPA;
565
566			pdata->an_start = jiffies;
567
568			netif_dbg(pdata, link, pdata->netdev,
569				  "AN timed out, resetting state\n");
570		}
571	}
572
573	state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
574					   : &pdata->kx_state;
575
576	switch (*state) {
577	case XGBE_RX_BPA:
578		ret = xgbe_an_rx_bpa(pdata, state);
579		break;
580
581	case XGBE_RX_XNP:
582		ret = xgbe_an_rx_xnp(pdata, state);
583		break;
584
585	default:
586		ret = XGBE_AN_ERROR;
587	}
588
589	return ret;
590}
591
592static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata)
593{
594	/* Be sure we aren't looping trying to negotiate */
595	if (xgbe_in_kr_mode(pdata)) {
596		pdata->kr_state = XGBE_RX_ERROR;
597
598		if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) &&
599		    !(pdata->phy.advertising & ADVERTISED_2500baseX_Full))
600			return XGBE_AN_NO_LINK;
601
602		if (pdata->kx_state != XGBE_RX_BPA)
603			return XGBE_AN_NO_LINK;
604	} else {
605		pdata->kx_state = XGBE_RX_ERROR;
606
607		if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full))
608			return XGBE_AN_NO_LINK;
609
610		if (pdata->kr_state != XGBE_RX_BPA)
611			return XGBE_AN_NO_LINK;
612	}
613
614	xgbe_disable_an(pdata);
615
616	xgbe_switch_mode(pdata);
617
618	xgbe_restart_an(pdata);
619
620	return XGBE_AN_INCOMPAT_LINK;
621}
622
623static irqreturn_t xgbe_an_isr(int irq, void *data)
624{
625	struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
626
627	netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
628
629	/* Interrupt reason must be read and cleared outside of IRQ context */
630	disable_irq_nosync(pdata->an_irq);
631
632	queue_work(pdata->an_workqueue, &pdata->an_irq_work);
633
634	return IRQ_HANDLED;
635}
636
637static void xgbe_an_irq_work(struct work_struct *work)
638{
639	struct xgbe_prv_data *pdata = container_of(work,
640						   struct xgbe_prv_data,
641						   an_irq_work);
642
643	/* Avoid a race between enabling the IRQ and exiting the work by
644	 * waiting for the work to finish and then queueing it
645	 */
646	flush_work(&pdata->an_work);
647	queue_work(pdata->an_workqueue, &pdata->an_work);
648}
649
650static const char *xgbe_state_as_string(enum xgbe_an state)
651{
652	switch (state) {
653	case XGBE_AN_READY:
654		return "Ready";
655	case XGBE_AN_PAGE_RECEIVED:
656		return "Page-Received";
657	case XGBE_AN_INCOMPAT_LINK:
658		return "Incompatible-Link";
659	case XGBE_AN_COMPLETE:
660		return "Complete";
661	case XGBE_AN_NO_LINK:
662		return "No-Link";
663	case XGBE_AN_ERROR:
664		return "Error";
665	default:
666		return "Undefined";
667	}
668}
669
670static void xgbe_an_state_machine(struct work_struct *work)
671{
672	struct xgbe_prv_data *pdata = container_of(work,
673						   struct xgbe_prv_data,
674						   an_work);
675	enum xgbe_an cur_state = pdata->an_state;
676	unsigned int int_reg, int_mask;
677
678	mutex_lock(&pdata->an_mutex);
679
680	/* Read the interrupt */
681	int_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
682	if (!int_reg)
683		goto out;
684
685next_int:
686	if (int_reg & XGBE_AN_PG_RCV) {
687		pdata->an_state = XGBE_AN_PAGE_RECEIVED;
688		int_mask = XGBE_AN_PG_RCV;
689	} else if (int_reg & XGBE_AN_INC_LINK) {
690		pdata->an_state = XGBE_AN_INCOMPAT_LINK;
691		int_mask = XGBE_AN_INC_LINK;
692	} else if (int_reg & XGBE_AN_INT_CMPLT) {
693		pdata->an_state = XGBE_AN_COMPLETE;
694		int_mask = XGBE_AN_INT_CMPLT;
695	} else {
696		pdata->an_state = XGBE_AN_ERROR;
697		int_mask = 0;
698	}
699
700	/* Clear the interrupt to be processed */
701	int_reg &= ~int_mask;
702	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
703
704	pdata->an_result = pdata->an_state;
705
706again:
707	netif_dbg(pdata, link, pdata->netdev, "AN %s\n",
708		  xgbe_state_as_string(pdata->an_state));
709
710	cur_state = pdata->an_state;
711
712	switch (pdata->an_state) {
713	case XGBE_AN_READY:
714		pdata->an_supported = 0;
715		break;
716
717	case XGBE_AN_PAGE_RECEIVED:
718		pdata->an_state = xgbe_an_page_received(pdata);
719		pdata->an_supported++;
720		break;
721
722	case XGBE_AN_INCOMPAT_LINK:
723		pdata->an_supported = 0;
724		pdata->parallel_detect = 0;
725		pdata->an_state = xgbe_an_incompat_link(pdata);
726		break;
727
728	case XGBE_AN_COMPLETE:
729		pdata->parallel_detect = pdata->an_supported ? 0 : 1;
730		netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
731			  pdata->an_supported ? "Auto negotiation"
732					      : "Parallel detection");
733		break;
734
735	case XGBE_AN_NO_LINK:
736		break;
737
738	default:
739		pdata->an_state = XGBE_AN_ERROR;
740	}
741
742	if (pdata->an_state == XGBE_AN_NO_LINK) {
743		int_reg = 0;
744		XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
745	} else if (pdata->an_state == XGBE_AN_ERROR) {
746		netdev_err(pdata->netdev,
747			   "error during auto-negotiation, state=%u\n",
748			   cur_state);
749
750		int_reg = 0;
751		XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
752	}
753
754	if (pdata->an_state >= XGBE_AN_COMPLETE) {
755		pdata->an_result = pdata->an_state;
756		pdata->an_state = XGBE_AN_READY;
757		pdata->kr_state = XGBE_RX_BPA;
758		pdata->kx_state = XGBE_RX_BPA;
759		pdata->an_start = 0;
760
761		netif_dbg(pdata, link, pdata->netdev, "AN result: %s\n",
762			  xgbe_state_as_string(pdata->an_result));
763	}
764
765	if (cur_state != pdata->an_state)
766		goto again;
767
768	if (int_reg)
769		goto next_int;
770
771out:
772	enable_irq(pdata->an_irq);
773
774	mutex_unlock(&pdata->an_mutex);
775}
776
777static void xgbe_an_init(struct xgbe_prv_data *pdata)
778{
779	unsigned int reg;
780
781	/* Set up Advertisement register 3 first */
782	reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
783	if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC)
784		reg |= 0xc000;
785	else
786		reg &= ~0xc000;
787
788	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
789
790	/* Set up Advertisement register 2 next */
791	reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
792	if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
793		reg |= 0x80;
794	else
795		reg &= ~0x80;
796
797	if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
798	    (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
799		reg |= 0x20;
800	else
801		reg &= ~0x20;
802
803	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
804
805	/* Set up Advertisement register 1 last */
806	reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
807	if (pdata->phy.advertising & ADVERTISED_Pause)
808		reg |= 0x400;
809	else
810		reg &= ~0x400;
811
812	if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
813		reg |= 0x800;
814	else
815		reg &= ~0x800;
816
817	/* We don't intend to perform XNP */
818	reg &= ~XGBE_XNP_NP_EXCHANGE;
819
820	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
821
822	netif_dbg(pdata, link, pdata->netdev, "AN initialized\n");
823}
824
825static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
826{
827	if (pdata->tx_pause && pdata->rx_pause)
828		return "rx/tx";
829	else if (pdata->rx_pause)
830		return "rx";
831	else if (pdata->tx_pause)
832		return "tx";
833	else
834		return "off";
835}
836
837static const char *xgbe_phy_speed_string(int speed)
838{
839	switch (speed) {
840	case SPEED_1000:
841		return "1Gbps";
842	case SPEED_2500:
843		return "2.5Gbps";
844	case SPEED_10000:
845		return "10Gbps";
846	case SPEED_UNKNOWN:
847		return "Unknown";
848	default:
849		return "Unsupported";
850	}
851}
852
853static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
854{
855	if (pdata->phy.link)
856		netdev_info(pdata->netdev,
857			    "Link is Up - %s/%s - flow control %s\n",
858			    xgbe_phy_speed_string(pdata->phy.speed),
859			    pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
860			    xgbe_phy_fc_string(pdata));
861	else
862		netdev_info(pdata->netdev, "Link is Down\n");
863}
864
865static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
866{
867	int new_state = 0;
868
869	if (pdata->phy.link) {
870		/* Flow control support */
871		pdata->pause_autoneg = pdata->phy.pause_autoneg;
872
873		if (pdata->tx_pause != pdata->phy.tx_pause) {
874			new_state = 1;
875			pdata->hw_if.config_tx_flow_control(pdata);
876			pdata->tx_pause = pdata->phy.tx_pause;
877		}
878
879		if (pdata->rx_pause != pdata->phy.rx_pause) {
880			new_state = 1;
881			pdata->hw_if.config_rx_flow_control(pdata);
882			pdata->rx_pause = pdata->phy.rx_pause;
883		}
884
885		/* Speed support */
886		if (pdata->phy_speed != pdata->phy.speed) {
887			new_state = 1;
888			pdata->phy_speed = pdata->phy.speed;
889		}
890
891		if (pdata->phy_link != pdata->phy.link) {
892			new_state = 1;
893			pdata->phy_link = pdata->phy.link;
894		}
895	} else if (pdata->phy_link) {
896		new_state = 1;
897		pdata->phy_link = 0;
898		pdata->phy_speed = SPEED_UNKNOWN;
899	}
900
901	if (new_state && netif_msg_link(pdata))
902		xgbe_phy_print_status(pdata);
903}
904
905static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
906{
907	netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
908
909	/* Disable auto-negotiation */
910	xgbe_disable_an(pdata);
911
912	/* Validate/Set specified speed */
913	switch (pdata->phy.speed) {
914	case SPEED_10000:
915		xgbe_set_mode(pdata, XGBE_MODE_KR);
916		break;
917
918	case SPEED_2500:
919	case SPEED_1000:
920		xgbe_set_mode(pdata, XGBE_MODE_KX);
921		break;
922
923	default:
924		return -EINVAL;
925	}
926
927	/* Validate duplex mode */
928	if (pdata->phy.duplex != DUPLEX_FULL)
929		return -EINVAL;
930
931	return 0;
932}
933
934static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
935{
936	set_bit(XGBE_LINK_INIT, &pdata->dev_state);
937	pdata->link_check = jiffies;
938
939	if (pdata->phy.autoneg != AUTONEG_ENABLE)
940		return xgbe_phy_config_fixed(pdata);
941
942	netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
943
944	/* Disable auto-negotiation interrupt */
945	disable_irq(pdata->an_irq);
946
947	/* Start auto-negotiation in a supported mode */
948	if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) {
949		xgbe_set_mode(pdata, XGBE_MODE_KR);
950	} else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
951		   (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) {
952		xgbe_set_mode(pdata, XGBE_MODE_KX);
953	} else {
954		enable_irq(pdata->an_irq);
955		return -EINVAL;
956	}
957
958	/* Disable and stop any in progress auto-negotiation */
959	xgbe_disable_an(pdata);
960
961	/* Clear any auto-negotitation interrupts */
962	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
963
964	pdata->an_result = XGBE_AN_READY;
965	pdata->an_state = XGBE_AN_READY;
966	pdata->kr_state = XGBE_RX_BPA;
967	pdata->kx_state = XGBE_RX_BPA;
968
969	/* Re-enable auto-negotiation interrupt */
970	enable_irq(pdata->an_irq);
971
972	/* Set up advertisement registers based on current settings */
973	xgbe_an_init(pdata);
974
975	/* Enable and start auto-negotiation */
976	xgbe_restart_an(pdata);
977
978	return 0;
979}
980
981static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
982{
983	int ret;
984
985	mutex_lock(&pdata->an_mutex);
986
987	ret = __xgbe_phy_config_aneg(pdata);
988	if (ret)
989		set_bit(XGBE_LINK_ERR, &pdata->dev_state);
990	else
991		clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
992
993	mutex_unlock(&pdata->an_mutex);
994
995	return ret;
996}
997
998static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
999{
1000	return (pdata->an_result == XGBE_AN_COMPLETE);
1001}
1002
1003static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1004{
1005	unsigned long link_timeout;
1006
1007	link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1008	if (time_after(jiffies, link_timeout)) {
1009		netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1010		xgbe_phy_config_aneg(pdata);
1011	}
1012}
1013
1014static void xgbe_phy_status_force(struct xgbe_prv_data *pdata)
1015{
1016	if (xgbe_in_kr_mode(pdata)) {
1017		pdata->phy.speed = SPEED_10000;
1018	} else {
1019		switch (pdata->speed_set) {
1020		case XGBE_SPEEDSET_1000_10000:
1021			pdata->phy.speed = SPEED_1000;
1022			break;
1023
1024		case XGBE_SPEEDSET_2500_10000:
1025			pdata->phy.speed = SPEED_2500;
1026			break;
1027		}
1028	}
1029	pdata->phy.duplex = DUPLEX_FULL;
1030}
1031
1032static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1033{
1034	unsigned int ad_reg, lp_reg;
1035
1036	pdata->phy.lp_advertising = 0;
1037
1038	if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1039		return xgbe_phy_status_force(pdata);
1040
1041	pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
1042	pdata->phy.lp_advertising |= ADVERTISED_Backplane;
1043
1044	/* Compare Advertisement and Link Partner register 1 */
1045	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1046	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1047	if (lp_reg & 0x400)
1048		pdata->phy.lp_advertising |= ADVERTISED_Pause;
1049	if (lp_reg & 0x800)
1050		pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
1051
1052	if (pdata->phy.pause_autoneg) {
1053		/* Set flow control based on auto-negotiation result */
1054		pdata->phy.tx_pause = 0;
1055		pdata->phy.rx_pause = 0;
1056
1057		if (ad_reg & lp_reg & 0x400) {
1058			pdata->phy.tx_pause = 1;
1059			pdata->phy.rx_pause = 1;
1060		} else if (ad_reg & lp_reg & 0x800) {
1061			if (ad_reg & 0x400)
1062				pdata->phy.rx_pause = 1;
1063			else if (lp_reg & 0x400)
1064				pdata->phy.tx_pause = 1;
1065		}
1066	}
1067
1068	/* Compare Advertisement and Link Partner register 2 */
1069	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1070	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1071	if (lp_reg & 0x80)
1072		pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
1073	if (lp_reg & 0x20) {
1074		switch (pdata->speed_set) {
1075		case XGBE_SPEEDSET_1000_10000:
1076			pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
1077			break;
1078		case XGBE_SPEEDSET_2500_10000:
1079			pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full;
1080			break;
1081		}
1082	}
1083
1084	ad_reg &= lp_reg;
1085	if (ad_reg & 0x80) {
1086		pdata->phy.speed = SPEED_10000;
1087		xgbe_set_mode(pdata, XGBE_MODE_KR);
1088	} else if (ad_reg & 0x20) {
1089		switch (pdata->speed_set) {
1090		case XGBE_SPEEDSET_1000_10000:
1091			pdata->phy.speed = SPEED_1000;
1092			break;
1093
1094		case XGBE_SPEEDSET_2500_10000:
1095			pdata->phy.speed = SPEED_2500;
1096			break;
1097		}
1098
1099		xgbe_set_mode(pdata, XGBE_MODE_KX);
1100	} else {
1101		pdata->phy.speed = SPEED_UNKNOWN;
1102	}
1103
1104	/* Compare Advertisement and Link Partner register 3 */
1105	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1106	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1107	if (lp_reg & 0xc000)
1108		pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1109
1110	pdata->phy.duplex = DUPLEX_FULL;
1111}
1112
1113static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1114{
1115	unsigned int reg, link_aneg;
1116
1117	if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1118		netif_carrier_off(pdata->netdev);
1119
1120		pdata->phy.link = 0;
1121		goto adjust_link;
1122	}
1123
1124	link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1125
1126	/* Get the link status. Link status is latched low, so read
1127	 * once to clear and then read again to get current state
1128	 */
1129	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1130	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1131	pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;
1132
1133	if (pdata->phy.link) {
1134		if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1135			xgbe_check_link_timeout(pdata);
1136			return;
1137		}
1138
1139		xgbe_phy_status_aneg(pdata);
1140
1141		if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1142			clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1143
1144		netif_carrier_on(pdata->netdev);
1145	} else {
1146		if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1147			xgbe_check_link_timeout(pdata);
1148
1149			if (link_aneg)
1150				return;
1151		}
1152
1153		xgbe_phy_status_aneg(pdata);
1154
1155		netif_carrier_off(pdata->netdev);
1156	}
1157
1158adjust_link:
1159	xgbe_phy_adjust_link(pdata);
1160}
1161
1162static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1163{
1164	netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1165
1166	/* Disable auto-negotiation */
1167	xgbe_disable_an(pdata);
1168
1169	/* Disable auto-negotiation interrupts */
1170	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1171
1172	devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1173
1174	pdata->phy.link = 0;
1175	netif_carrier_off(pdata->netdev);
1176
1177	xgbe_phy_adjust_link(pdata);
1178}
1179
1180static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1181{
1182	struct net_device *netdev = pdata->netdev;
1183	int ret;
1184
1185	netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1186
1187	ret = devm_request_irq(pdata->dev, pdata->an_irq,
1188			       xgbe_an_isr, 0, pdata->an_name,
1189			       pdata);
1190	if (ret) {
1191		netdev_err(netdev, "phy irq request failed\n");
1192		return ret;
1193	}
1194
1195	/* Set initial mode - call the mode setting routines
1196	 * directly to insure we are properly configured
1197	 */
1198	if (xgbe_use_xgmii_mode(pdata)) {
1199		xgbe_xgmii_mode(pdata);
1200	} else if (xgbe_use_gmii_mode(pdata)) {
1201		xgbe_gmii_mode(pdata);
1202	} else if (xgbe_use_gmii_2500_mode(pdata)) {
1203		xgbe_gmii_2500_mode(pdata);
1204	} else {
1205		ret = -EINVAL;
1206		goto err_irq;
1207	}
1208
1209	/* Set up advertisement registers based on current settings */
1210	xgbe_an_init(pdata);
1211
1212	/* Enable auto-negotiation interrupts */
1213	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1214
1215	return xgbe_phy_config_aneg(pdata);
1216
1217err_irq:
1218	devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1219
1220	return ret;
1221}
1222
1223static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1224{
1225	unsigned int count, reg;
1226
1227	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1228	reg |= MDIO_CTRL1_RESET;
1229	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
1230
1231	count = 50;
1232	do {
1233		msleep(20);
1234		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1235	} while ((reg & MDIO_CTRL1_RESET) && --count);
1236
1237	if (reg & MDIO_CTRL1_RESET)
1238		return -ETIMEDOUT;
1239
1240	/* Disable auto-negotiation for now */
1241	xgbe_disable_an(pdata);
1242
1243	/* Clear auto-negotiation interrupts */
1244	XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
1245
1246	return 0;
1247}
1248
1249static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1250{
1251	struct device *dev = pdata->dev;
1252
1253	dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1254
1255	dev_dbg(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1256		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1257	dev_dbg(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1258		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1259	dev_dbg(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1,
1260		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1261	dev_dbg(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2,
1262		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1263	dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1,
1264		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1265	dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2,
1266		XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1267
1268	dev_dbg(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1269		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1270	dev_dbg(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1271		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1272	dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n",
1273		MDIO_AN_ADVERTISE,
1274		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1275	dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n",
1276		MDIO_AN_ADVERTISE + 1,
1277		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1278	dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n",
1279		MDIO_AN_ADVERTISE + 2,
1280		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1281	dev_dbg(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n",
1282		MDIO_AN_COMP_STAT,
1283		XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1284
1285	dev_dbg(dev, "\n*************************************************\n");
1286}
1287
1288static void xgbe_phy_init(struct xgbe_prv_data *pdata)
1289{
1290	mutex_init(&pdata->an_mutex);
1291	INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1292	INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1293	pdata->mdio_mmd = MDIO_MMD_PCS;
1294
1295	/* Initialize supported features */
1296	pdata->phy.supported = SUPPORTED_Autoneg;
1297	pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1298	pdata->phy.supported |= SUPPORTED_Backplane;
1299	pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
1300	switch (pdata->speed_set) {
1301	case XGBE_SPEEDSET_1000_10000:
1302		pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
1303		break;
1304	case XGBE_SPEEDSET_2500_10000:
1305		pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1306		break;
1307	}
1308
1309	pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1310					MDIO_PMA_10GBR_FECABLE);
1311	pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1312			       MDIO_PMA_10GBR_FECABLE_ERRABLE);
1313	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1314		pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
1315
1316	pdata->phy.advertising = pdata->phy.supported;
1317
1318	pdata->phy.address = 0;
1319
1320	pdata->phy.autoneg = AUTONEG_ENABLE;
1321	pdata->phy.speed = SPEED_UNKNOWN;
1322	pdata->phy.duplex = DUPLEX_UNKNOWN;
1323
1324	pdata->phy.link = 0;
1325
1326	pdata->phy.pause_autoneg = pdata->pause_autoneg;
1327	pdata->phy.tx_pause = pdata->tx_pause;
1328	pdata->phy.rx_pause = pdata->rx_pause;
1329
1330	/* Fix up Flow Control advertising */
1331	pdata->phy.advertising &= ~ADVERTISED_Pause;
1332	pdata->phy.advertising &= ~ADVERTISED_Asym_Pause;
1333
1334	if (pdata->rx_pause) {
1335		pdata->phy.advertising |= ADVERTISED_Pause;
1336		pdata->phy.advertising |= ADVERTISED_Asym_Pause;
1337	}
1338
1339	if (pdata->tx_pause)
1340		pdata->phy.advertising ^= ADVERTISED_Asym_Pause;
1341
1342	if (netif_msg_drv(pdata))
1343		xgbe_dump_phy_registers(pdata);
1344}
1345
1346void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1347{
1348	phy_if->phy_init        = xgbe_phy_init;
1349
1350	phy_if->phy_reset       = xgbe_phy_reset;
1351	phy_if->phy_start       = xgbe_phy_start;
1352	phy_if->phy_stop        = xgbe_phy_stop;
1353
1354	phy_if->phy_status      = xgbe_phy_status;
1355	phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1356}
1357