1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 */ 12 13#include <linux/clk.h> 14#include <linux/errno.h> 15#include <linux/if_arp.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/netdevice.h> 20#include <linux/of.h> 21#include <linux/platform_device.h> 22#include <linux/rtnetlink.h> 23#include <linux/skbuff.h> 24#include <linux/spinlock.h> 25#include <linux/string.h> 26#include <linux/types.h> 27 28#include <linux/can/dev.h> 29#include <linux/can/error.h> 30#include <linux/can/led.h> 31 32#define AT91_MB_MASK(i) ((1 << (i)) - 1) 33 34/* Common registers */ 35enum at91_reg { 36 AT91_MR = 0x000, 37 AT91_IER = 0x004, 38 AT91_IDR = 0x008, 39 AT91_IMR = 0x00C, 40 AT91_SR = 0x010, 41 AT91_BR = 0x014, 42 AT91_TIM = 0x018, 43 AT91_TIMESTP = 0x01C, 44 AT91_ECR = 0x020, 45 AT91_TCR = 0x024, 46 AT91_ACR = 0x028, 47}; 48 49/* Mailbox registers (0 <= i <= 15) */ 50#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 51#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 52#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 53#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 54#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 55#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 56#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 57#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 58 59/* Register bits */ 60#define AT91_MR_CANEN BIT(0) 61#define AT91_MR_LPM BIT(1) 62#define AT91_MR_ABM BIT(2) 63#define AT91_MR_OVL BIT(3) 64#define AT91_MR_TEOF BIT(4) 65#define AT91_MR_TTM BIT(5) 66#define AT91_MR_TIMFRZ BIT(6) 67#define AT91_MR_DRPT BIT(7) 68 69#define AT91_SR_RBSY BIT(29) 70 71#define AT91_MMR_PRIO_SHIFT (16) 72 73#define AT91_MID_MIDE BIT(29) 74 75#define AT91_MSR_MRTR BIT(20) 76#define AT91_MSR_MABT BIT(22) 77#define AT91_MSR_MRDY BIT(23) 78#define AT91_MSR_MMI BIT(24) 79 80#define AT91_MCR_MRTR BIT(20) 81#define AT91_MCR_MTCR BIT(23) 82 83/* Mailbox Modes */ 84enum at91_mb_mode { 85 AT91_MB_MODE_DISABLED = 0, 86 AT91_MB_MODE_RX = 1, 87 AT91_MB_MODE_RX_OVRWR = 2, 88 AT91_MB_MODE_TX = 3, 89 AT91_MB_MODE_CONSUMER = 4, 90 AT91_MB_MODE_PRODUCER = 5, 91}; 92 93/* Interrupt mask bits */ 94#define AT91_IRQ_ERRA (1 << 16) 95#define AT91_IRQ_WARN (1 << 17) 96#define AT91_IRQ_ERRP (1 << 18) 97#define AT91_IRQ_BOFF (1 << 19) 98#define AT91_IRQ_SLEEP (1 << 20) 99#define AT91_IRQ_WAKEUP (1 << 21) 100#define AT91_IRQ_TOVF (1 << 22) 101#define AT91_IRQ_TSTP (1 << 23) 102#define AT91_IRQ_CERR (1 << 24) 103#define AT91_IRQ_SERR (1 << 25) 104#define AT91_IRQ_AERR (1 << 26) 105#define AT91_IRQ_FERR (1 << 27) 106#define AT91_IRQ_BERR (1 << 28) 107 108#define AT91_IRQ_ERR_ALL (0x1fff0000) 109#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 110 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 111#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 112 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 113 114#define AT91_IRQ_ALL (0x1fffffff) 115 116enum at91_devtype { 117 AT91_DEVTYPE_SAM9263, 118 AT91_DEVTYPE_SAM9X5, 119}; 120 121struct at91_devtype_data { 122 unsigned int rx_first; 123 unsigned int rx_split; 124 unsigned int rx_last; 125 unsigned int tx_shift; 126 enum at91_devtype type; 127}; 128 129struct at91_priv { 130 struct can_priv can; /* must be the first member! */ 131 struct napi_struct napi; 132 133 void __iomem *reg_base; 134 135 u32 reg_sr; 136 unsigned int tx_next; 137 unsigned int tx_echo; 138 unsigned int rx_next; 139 struct at91_devtype_data devtype_data; 140 141 struct clk *clk; 142 struct at91_can_data *pdata; 143 144 canid_t mb0_id; 145}; 146 147static const struct at91_devtype_data at91_at91sam9263_data = { 148 .rx_first = 1, 149 .rx_split = 8, 150 .rx_last = 11, 151 .tx_shift = 2, 152 .type = AT91_DEVTYPE_SAM9263, 153}; 154 155static const struct at91_devtype_data at91_at91sam9x5_data = { 156 .rx_first = 0, 157 .rx_split = 4, 158 .rx_last = 5, 159 .tx_shift = 1, 160 .type = AT91_DEVTYPE_SAM9X5, 161}; 162 163static const struct can_bittiming_const at91_bittiming_const = { 164 .name = KBUILD_MODNAME, 165 .tseg1_min = 4, 166 .tseg1_max = 16, 167 .tseg2_min = 2, 168 .tseg2_max = 8, 169 .sjw_max = 4, 170 .brp_min = 2, 171 .brp_max = 128, 172 .brp_inc = 1, 173}; 174 175#define AT91_IS(_model) \ 176static inline int at91_is_sam##_model(const struct at91_priv *priv) \ 177{ \ 178 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 179} 180 181AT91_IS(9263); 182AT91_IS(9X5); 183 184static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 185{ 186 return priv->devtype_data.rx_first; 187} 188 189static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 190{ 191 return priv->devtype_data.rx_last; 192} 193 194static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 195{ 196 return priv->devtype_data.rx_split; 197} 198 199static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 200{ 201 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 202} 203 204static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 205{ 206 return get_mb_rx_split(priv) - 1; 207} 208 209static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 210{ 211 return AT91_MB_MASK(get_mb_rx_split(priv)) & 212 ~AT91_MB_MASK(get_mb_rx_first(priv)); 213} 214 215static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 216{ 217 return priv->devtype_data.tx_shift; 218} 219 220static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 221{ 222 return 1 << get_mb_tx_shift(priv); 223} 224 225static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 226{ 227 return get_mb_rx_last(priv) + 1; 228} 229 230static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 231{ 232 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 233} 234 235static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 236{ 237 return get_mb_tx_shift(priv); 238} 239 240static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 241{ 242 return 0xf << get_mb_tx_shift(priv); 243} 244 245static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 246{ 247 return AT91_MB_MASK(get_mb_tx_shift(priv)); 248} 249 250static inline unsigned int get_next_mask(const struct at91_priv *priv) 251{ 252 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 253} 254 255static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 256{ 257 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 258 ~AT91_MB_MASK(get_mb_rx_first(priv)); 259} 260 261static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 262{ 263 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 264 ~AT91_MB_MASK(get_mb_tx_first(priv)); 265} 266 267static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 268{ 269 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 270} 271 272static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 273{ 274 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 275} 276 277static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 278{ 279 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 280} 281 282static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 283{ 284 return readl_relaxed(priv->reg_base + reg); 285} 286 287static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 288 u32 value) 289{ 290 writel_relaxed(value, priv->reg_base + reg); 291} 292 293static inline void set_mb_mode_prio(const struct at91_priv *priv, 294 unsigned int mb, enum at91_mb_mode mode, int prio) 295{ 296 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 297} 298 299static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 300 enum at91_mb_mode mode) 301{ 302 set_mb_mode_prio(priv, mb, mode, 0); 303} 304 305static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 306{ 307 u32 reg_mid; 308 309 if (can_id & CAN_EFF_FLAG) 310 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 311 else 312 reg_mid = (can_id & CAN_SFF_MASK) << 18; 313 314 return reg_mid; 315} 316 317static void at91_setup_mailboxes(struct net_device *dev) 318{ 319 struct at91_priv *priv = netdev_priv(dev); 320 unsigned int i; 321 u32 reg_mid; 322 323 /* 324 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 325 * mailbox is disabled. The next 11 mailboxes are used as a 326 * reception FIFO. The last mailbox is configured with 327 * overwrite option. The overwrite flag indicates a FIFO 328 * overflow. 329 */ 330 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 331 for (i = 0; i < get_mb_rx_first(priv); i++) { 332 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 333 at91_write(priv, AT91_MID(i), reg_mid); 334 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 335 } 336 337 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 338 set_mb_mode(priv, i, AT91_MB_MODE_RX); 339 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 340 341 /* reset acceptance mask and id register */ 342 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 343 at91_write(priv, AT91_MAM(i), 0x0); 344 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 345 } 346 347 /* The last 4 mailboxes are used for transmitting. */ 348 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 349 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 350 351 /* Reset tx and rx helper pointers */ 352 priv->tx_next = priv->tx_echo = 0; 353 priv->rx_next = get_mb_rx_first(priv); 354} 355 356static int at91_set_bittiming(struct net_device *dev) 357{ 358 const struct at91_priv *priv = netdev_priv(dev); 359 const struct can_bittiming *bt = &priv->can.bittiming; 360 u32 reg_br; 361 362 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 363 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 364 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 365 ((bt->phase_seg2 - 1) << 0); 366 367 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 368 369 at91_write(priv, AT91_BR, reg_br); 370 371 return 0; 372} 373 374static int at91_get_berr_counter(const struct net_device *dev, 375 struct can_berr_counter *bec) 376{ 377 const struct at91_priv *priv = netdev_priv(dev); 378 u32 reg_ecr = at91_read(priv, AT91_ECR); 379 380 bec->rxerr = reg_ecr & 0xff; 381 bec->txerr = reg_ecr >> 16; 382 383 return 0; 384} 385 386static void at91_chip_start(struct net_device *dev) 387{ 388 struct at91_priv *priv = netdev_priv(dev); 389 u32 reg_mr, reg_ier; 390 391 /* disable interrupts */ 392 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 393 394 /* disable chip */ 395 reg_mr = at91_read(priv, AT91_MR); 396 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 397 398 at91_set_bittiming(dev); 399 at91_setup_mailboxes(dev); 400 401 /* enable chip */ 402 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 403 reg_mr = AT91_MR_CANEN | AT91_MR_ABM; 404 else 405 reg_mr = AT91_MR_CANEN; 406 at91_write(priv, AT91_MR, reg_mr); 407 408 priv->can.state = CAN_STATE_ERROR_ACTIVE; 409 410 /* Enable interrupts */ 411 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 412 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 413 at91_write(priv, AT91_IER, reg_ier); 414} 415 416static void at91_chip_stop(struct net_device *dev, enum can_state state) 417{ 418 struct at91_priv *priv = netdev_priv(dev); 419 u32 reg_mr; 420 421 /* disable interrupts */ 422 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 423 424 reg_mr = at91_read(priv, AT91_MR); 425 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 426 427 priv->can.state = state; 428} 429 430/* 431 * theory of operation: 432 * 433 * According to the datasheet priority 0 is the highest priority, 15 434 * is the lowest. If two mailboxes have the same priority level the 435 * message of the mailbox with the lowest number is sent first. 436 * 437 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 438 * the next mailbox with prio 0, and so on, until all mailboxes are 439 * used. Then we start from the beginning with mailbox 440 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 441 * prio 1. When we reach the last mailbox with prio 15, we have to 442 * stop sending, waiting for all messages to be delivered, then start 443 * again with mailbox AT91_MB_TX_FIRST prio 0. 444 * 445 * We use the priv->tx_next as counter for the next transmission 446 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 447 * encode the mailbox number, the upper 4 bits the mailbox priority: 448 * 449 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 450 * (mb - get_mb_tx_first(priv)); 451 * 452 */ 453static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 454{ 455 struct at91_priv *priv = netdev_priv(dev); 456 struct net_device_stats *stats = &dev->stats; 457 struct can_frame *cf = (struct can_frame *)skb->data; 458 unsigned int mb, prio; 459 u32 reg_mid, reg_mcr; 460 461 if (can_dropped_invalid_skb(dev, skb)) 462 return NETDEV_TX_OK; 463 464 mb = get_tx_next_mb(priv); 465 prio = get_tx_next_prio(priv); 466 467 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 468 netif_stop_queue(dev); 469 470 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 471 return NETDEV_TX_BUSY; 472 } 473 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 474 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 475 (cf->can_dlc << 16) | AT91_MCR_MTCR; 476 477 /* disable MB while writing ID (see datasheet) */ 478 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 479 at91_write(priv, AT91_MID(mb), reg_mid); 480 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 481 482 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 483 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 484 485 /* This triggers transmission */ 486 at91_write(priv, AT91_MCR(mb), reg_mcr); 487 488 stats->tx_bytes += cf->can_dlc; 489 490 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 491 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv)); 492 493 /* 494 * we have to stop the queue and deliver all messages in case 495 * of a prio+mb counter wrap around. This is the case if 496 * tx_next buffer prio and mailbox equals 0. 497 * 498 * also stop the queue if next buffer is still in use 499 * (== not ready) 500 */ 501 priv->tx_next++; 502 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 503 AT91_MSR_MRDY) || 504 (priv->tx_next & get_next_mask(priv)) == 0) 505 netif_stop_queue(dev); 506 507 /* Enable interrupt for this mailbox */ 508 at91_write(priv, AT91_IER, 1 << mb); 509 510 return NETDEV_TX_OK; 511} 512 513/** 514 * at91_activate_rx_low - activate lower rx mailboxes 515 * @priv: a91 context 516 * 517 * Reenables the lower mailboxes for reception of new CAN messages 518 */ 519static inline void at91_activate_rx_low(const struct at91_priv *priv) 520{ 521 u32 mask = get_mb_rx_low_mask(priv); 522 at91_write(priv, AT91_TCR, mask); 523} 524 525/** 526 * at91_activate_rx_mb - reactive single rx mailbox 527 * @priv: a91 context 528 * @mb: mailbox to reactivate 529 * 530 * Reenables given mailbox for reception of new CAN messages 531 */ 532static inline void at91_activate_rx_mb(const struct at91_priv *priv, 533 unsigned int mb) 534{ 535 u32 mask = 1 << mb; 536 at91_write(priv, AT91_TCR, mask); 537} 538 539/** 540 * at91_rx_overflow_err - send error frame due to rx overflow 541 * @dev: net device 542 */ 543static void at91_rx_overflow_err(struct net_device *dev) 544{ 545 struct net_device_stats *stats = &dev->stats; 546 struct sk_buff *skb; 547 struct can_frame *cf; 548 549 netdev_dbg(dev, "RX buffer overflow\n"); 550 stats->rx_over_errors++; 551 stats->rx_errors++; 552 553 skb = alloc_can_err_skb(dev, &cf); 554 if (unlikely(!skb)) 555 return; 556 557 cf->can_id |= CAN_ERR_CRTL; 558 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 559 560 stats->rx_packets++; 561 stats->rx_bytes += cf->can_dlc; 562 netif_receive_skb(skb); 563} 564 565/** 566 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 567 * @dev: net device 568 * @mb: mailbox number to read from 569 * @cf: can frame where to store message 570 * 571 * Reads a CAN message from the given mailbox and stores data into 572 * given can frame. "mb" and "cf" must be valid. 573 */ 574static void at91_read_mb(struct net_device *dev, unsigned int mb, 575 struct can_frame *cf) 576{ 577 const struct at91_priv *priv = netdev_priv(dev); 578 u32 reg_msr, reg_mid; 579 580 reg_mid = at91_read(priv, AT91_MID(mb)); 581 if (reg_mid & AT91_MID_MIDE) 582 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 583 else 584 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 585 586 reg_msr = at91_read(priv, AT91_MSR(mb)); 587 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 588 589 if (reg_msr & AT91_MSR_MRTR) 590 cf->can_id |= CAN_RTR_FLAG; 591 else { 592 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 593 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 594 } 595 596 /* allow RX of extended frames */ 597 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 598 599 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 600 at91_rx_overflow_err(dev); 601} 602 603/** 604 * at91_read_msg - read CAN message from mailbox 605 * @dev: net device 606 * @mb: mail box to read from 607 * 608 * Reads a CAN message from given mailbox, and put into linux network 609 * RX queue, does all housekeeping chores (stats, ...) 610 */ 611static void at91_read_msg(struct net_device *dev, unsigned int mb) 612{ 613 struct net_device_stats *stats = &dev->stats; 614 struct can_frame *cf; 615 struct sk_buff *skb; 616 617 skb = alloc_can_skb(dev, &cf); 618 if (unlikely(!skb)) { 619 stats->rx_dropped++; 620 return; 621 } 622 623 at91_read_mb(dev, mb, cf); 624 625 stats->rx_packets++; 626 stats->rx_bytes += cf->can_dlc; 627 netif_receive_skb(skb); 628 629 can_led_event(dev, CAN_LED_EVENT_RX); 630} 631 632/** 633 * at91_poll_rx - read multiple CAN messages from mailboxes 634 * @dev: net device 635 * @quota: max number of pkgs we're allowed to receive 636 * 637 * Theory of Operation: 638 * 639 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 640 * on the chip are reserved for RX. We split them into 2 groups. The 641 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 642 * 643 * Like it or not, but the chip always saves a received CAN message 644 * into the first free mailbox it finds (starting with the 645 * lowest). This makes it very difficult to read the messages in the 646 * right order from the chip. This is how we work around that problem: 647 * 648 * The first message goes into mb nr. 1 and issues an interrupt. All 649 * rx ints are disabled in the interrupt handler and a napi poll is 650 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 651 * receive another message). 652 * 653 * lower mbxs upper 654 * ____^______ __^__ 655 * / \ / \ 656 * +-+-+-+-+-+-+-+-++-+-+-+-+ 657 * | |x|x|x|x|x|x|x|| | | | | 658 * +-+-+-+-+-+-+-+-++-+-+-+-+ 659 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 660 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 661 * ^ 662 * | 663 * \ 664 * unused, due to chip bug 665 * 666 * The variable priv->rx_next points to the next mailbox to read a 667 * message from. As long we're in the lower mailboxes we just read the 668 * mailbox but not reenable it. 669 * 670 * With completion of the last of the lower mailboxes, we reenable the 671 * whole first group, but continue to look for filled mailboxes in the 672 * upper mailboxes. Imagine the second group like overflow mailboxes, 673 * which takes CAN messages if the lower goup is full. While in the 674 * upper group we reenable the mailbox right after reading it. Giving 675 * the chip more room to store messages. 676 * 677 * After finishing we look again in the lower group if we've still 678 * quota. 679 * 680 */ 681static int at91_poll_rx(struct net_device *dev, int quota) 682{ 683 struct at91_priv *priv = netdev_priv(dev); 684 u32 reg_sr = at91_read(priv, AT91_SR); 685 const unsigned long *addr = (unsigned long *)®_sr; 686 unsigned int mb; 687 int received = 0; 688 689 if (priv->rx_next > get_mb_rx_low_last(priv) && 690 reg_sr & get_mb_rx_low_mask(priv)) 691 netdev_info(dev, 692 "order of incoming frames cannot be guaranteed\n"); 693 694 again: 695 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 696 mb < get_mb_tx_first(priv) && quota > 0; 697 reg_sr = at91_read(priv, AT91_SR), 698 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 699 at91_read_msg(dev, mb); 700 701 /* reactivate mailboxes */ 702 if (mb == get_mb_rx_low_last(priv)) 703 /* all lower mailboxed, if just finished it */ 704 at91_activate_rx_low(priv); 705 else if (mb > get_mb_rx_low_last(priv)) 706 /* only the mailbox we read */ 707 at91_activate_rx_mb(priv, mb); 708 709 received++; 710 quota--; 711 } 712 713 /* upper group completed, look again in lower */ 714 if (priv->rx_next > get_mb_rx_low_last(priv) && 715 quota > 0 && mb > get_mb_rx_last(priv)) { 716 priv->rx_next = get_mb_rx_first(priv); 717 goto again; 718 } 719 720 return received; 721} 722 723static void at91_poll_err_frame(struct net_device *dev, 724 struct can_frame *cf, u32 reg_sr) 725{ 726 struct at91_priv *priv = netdev_priv(dev); 727 728 /* CRC error */ 729 if (reg_sr & AT91_IRQ_CERR) { 730 netdev_dbg(dev, "CERR irq\n"); 731 dev->stats.rx_errors++; 732 priv->can.can_stats.bus_error++; 733 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 734 } 735 736 /* Stuffing Error */ 737 if (reg_sr & AT91_IRQ_SERR) { 738 netdev_dbg(dev, "SERR irq\n"); 739 dev->stats.rx_errors++; 740 priv->can.can_stats.bus_error++; 741 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 742 cf->data[2] |= CAN_ERR_PROT_STUFF; 743 } 744 745 /* Acknowledgement Error */ 746 if (reg_sr & AT91_IRQ_AERR) { 747 netdev_dbg(dev, "AERR irq\n"); 748 dev->stats.tx_errors++; 749 cf->can_id |= CAN_ERR_ACK; 750 } 751 752 /* Form error */ 753 if (reg_sr & AT91_IRQ_FERR) { 754 netdev_dbg(dev, "FERR irq\n"); 755 dev->stats.rx_errors++; 756 priv->can.can_stats.bus_error++; 757 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 758 cf->data[2] |= CAN_ERR_PROT_FORM; 759 } 760 761 /* Bit Error */ 762 if (reg_sr & AT91_IRQ_BERR) { 763 netdev_dbg(dev, "BERR irq\n"); 764 dev->stats.tx_errors++; 765 priv->can.can_stats.bus_error++; 766 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 767 cf->data[2] |= CAN_ERR_PROT_BIT; 768 } 769} 770 771static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 772{ 773 struct sk_buff *skb; 774 struct can_frame *cf; 775 776 if (quota == 0) 777 return 0; 778 779 skb = alloc_can_err_skb(dev, &cf); 780 if (unlikely(!skb)) 781 return 0; 782 783 at91_poll_err_frame(dev, cf, reg_sr); 784 785 dev->stats.rx_packets++; 786 dev->stats.rx_bytes += cf->can_dlc; 787 netif_receive_skb(skb); 788 789 return 1; 790} 791 792static int at91_poll(struct napi_struct *napi, int quota) 793{ 794 struct net_device *dev = napi->dev; 795 const struct at91_priv *priv = netdev_priv(dev); 796 u32 reg_sr = at91_read(priv, AT91_SR); 797 int work_done = 0; 798 799 if (reg_sr & get_irq_mb_rx(priv)) 800 work_done += at91_poll_rx(dev, quota - work_done); 801 802 /* 803 * The error bits are clear on read, 804 * so use saved value from irq handler. 805 */ 806 reg_sr |= priv->reg_sr; 807 if (reg_sr & AT91_IRQ_ERR_FRAME) 808 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 809 810 if (work_done < quota) { 811 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 812 u32 reg_ier = AT91_IRQ_ERR_FRAME; 813 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 814 815 napi_complete(napi); 816 at91_write(priv, AT91_IER, reg_ier); 817 } 818 819 return work_done; 820} 821 822/* 823 * theory of operation: 824 * 825 * priv->tx_echo holds the number of the oldest can_frame put for 826 * transmission into the hardware, but not yet ACKed by the CAN tx 827 * complete IRQ. 828 * 829 * We iterate from priv->tx_echo to priv->tx_next and check if the 830 * packet has been transmitted, echo it back to the CAN framework. If 831 * we discover a not yet transmitted package, stop looking for more. 832 * 833 */ 834static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 835{ 836 struct at91_priv *priv = netdev_priv(dev); 837 u32 reg_msr; 838 unsigned int mb; 839 840 /* masking of reg_sr not needed, already done by at91_irq */ 841 842 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 843 mb = get_tx_echo_mb(priv); 844 845 /* no event in mailbox? */ 846 if (!(reg_sr & (1 << mb))) 847 break; 848 849 /* Disable irq for this TX mailbox */ 850 at91_write(priv, AT91_IDR, 1 << mb); 851 852 /* 853 * only echo if mailbox signals us a transfer 854 * complete (MSR_MRDY). Otherwise it's a tansfer 855 * abort. "can_bus_off()" takes care about the skbs 856 * parked in the echo queue. 857 */ 858 reg_msr = at91_read(priv, AT91_MSR(mb)); 859 if (likely(reg_msr & AT91_MSR_MRDY && 860 ~reg_msr & AT91_MSR_MABT)) { 861 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 862 can_get_echo_skb(dev, mb - get_mb_tx_first(priv)); 863 dev->stats.tx_packets++; 864 can_led_event(dev, CAN_LED_EVENT_TX); 865 } 866 } 867 868 /* 869 * restart queue if we don't have a wrap around but restart if 870 * we get a TX int for the last can frame directly before a 871 * wrap around. 872 */ 873 if ((priv->tx_next & get_next_mask(priv)) != 0 || 874 (priv->tx_echo & get_next_mask(priv)) == 0) 875 netif_wake_queue(dev); 876} 877 878static void at91_irq_err_state(struct net_device *dev, 879 struct can_frame *cf, enum can_state new_state) 880{ 881 struct at91_priv *priv = netdev_priv(dev); 882 u32 reg_idr = 0, reg_ier = 0; 883 struct can_berr_counter bec; 884 885 at91_get_berr_counter(dev, &bec); 886 887 switch (priv->can.state) { 888 case CAN_STATE_ERROR_ACTIVE: 889 /* 890 * from: ERROR_ACTIVE 891 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 892 * => : there was a warning int 893 */ 894 if (new_state >= CAN_STATE_ERROR_WARNING && 895 new_state <= CAN_STATE_BUS_OFF) { 896 netdev_dbg(dev, "Error Warning IRQ\n"); 897 priv->can.can_stats.error_warning++; 898 899 cf->can_id |= CAN_ERR_CRTL; 900 cf->data[1] = (bec.txerr > bec.rxerr) ? 901 CAN_ERR_CRTL_TX_WARNING : 902 CAN_ERR_CRTL_RX_WARNING; 903 } 904 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 905 /* 906 * from: ERROR_ACTIVE, ERROR_WARNING 907 * to : ERROR_PASSIVE, BUS_OFF 908 * => : error passive int 909 */ 910 if (new_state >= CAN_STATE_ERROR_PASSIVE && 911 new_state <= CAN_STATE_BUS_OFF) { 912 netdev_dbg(dev, "Error Passive IRQ\n"); 913 priv->can.can_stats.error_passive++; 914 915 cf->can_id |= CAN_ERR_CRTL; 916 cf->data[1] = (bec.txerr > bec.rxerr) ? 917 CAN_ERR_CRTL_TX_PASSIVE : 918 CAN_ERR_CRTL_RX_PASSIVE; 919 } 920 break; 921 case CAN_STATE_BUS_OFF: 922 /* 923 * from: BUS_OFF 924 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 925 */ 926 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 927 cf->can_id |= CAN_ERR_RESTARTED; 928 929 netdev_dbg(dev, "restarted\n"); 930 priv->can.can_stats.restarts++; 931 932 netif_carrier_on(dev); 933 netif_wake_queue(dev); 934 } 935 break; 936 default: 937 break; 938 } 939 940 941 /* process state changes depending on the new state */ 942 switch (new_state) { 943 case CAN_STATE_ERROR_ACTIVE: 944 /* 945 * actually we want to enable AT91_IRQ_WARN here, but 946 * it screws up the system under certain 947 * circumstances. so just enable AT91_IRQ_ERRP, thus 948 * the "fallthrough" 949 */ 950 netdev_dbg(dev, "Error Active\n"); 951 cf->can_id |= CAN_ERR_PROT; 952 cf->data[2] = CAN_ERR_PROT_ACTIVE; 953 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 954 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 955 reg_ier = AT91_IRQ_ERRP; 956 break; 957 case CAN_STATE_ERROR_PASSIVE: 958 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 959 reg_ier = AT91_IRQ_BOFF; 960 break; 961 case CAN_STATE_BUS_OFF: 962 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 963 AT91_IRQ_WARN | AT91_IRQ_BOFF; 964 reg_ier = 0; 965 966 cf->can_id |= CAN_ERR_BUSOFF; 967 968 netdev_dbg(dev, "bus-off\n"); 969 netif_carrier_off(dev); 970 priv->can.can_stats.bus_off++; 971 972 /* turn off chip, if restart is disabled */ 973 if (!priv->can.restart_ms) { 974 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 975 return; 976 } 977 break; 978 default: 979 break; 980 } 981 982 at91_write(priv, AT91_IDR, reg_idr); 983 at91_write(priv, AT91_IER, reg_ier); 984} 985 986static int at91_get_state_by_bec(const struct net_device *dev, 987 enum can_state *state) 988{ 989 struct can_berr_counter bec; 990 int err; 991 992 err = at91_get_berr_counter(dev, &bec); 993 if (err) 994 return err; 995 996 if (bec.txerr < 96 && bec.rxerr < 96) 997 *state = CAN_STATE_ERROR_ACTIVE; 998 else if (bec.txerr < 128 && bec.rxerr < 128) 999 *state = CAN_STATE_ERROR_WARNING; 1000 else if (bec.txerr < 256 && bec.rxerr < 256) 1001 *state = CAN_STATE_ERROR_PASSIVE; 1002 else 1003 *state = CAN_STATE_BUS_OFF; 1004 1005 return 0; 1006} 1007 1008 1009static void at91_irq_err(struct net_device *dev) 1010{ 1011 struct at91_priv *priv = netdev_priv(dev); 1012 struct sk_buff *skb; 1013 struct can_frame *cf; 1014 enum can_state new_state; 1015 u32 reg_sr; 1016 int err; 1017 1018 if (at91_is_sam9263(priv)) { 1019 reg_sr = at91_read(priv, AT91_SR); 1020 1021 /* we need to look at the unmasked reg_sr */ 1022 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 1023 new_state = CAN_STATE_BUS_OFF; 1024 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 1025 new_state = CAN_STATE_ERROR_PASSIVE; 1026 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 1027 new_state = CAN_STATE_ERROR_WARNING; 1028 else if (likely(reg_sr & AT91_IRQ_ERRA)) 1029 new_state = CAN_STATE_ERROR_ACTIVE; 1030 else { 1031 netdev_err(dev, "BUG! hardware in undefined state\n"); 1032 return; 1033 } 1034 } else { 1035 err = at91_get_state_by_bec(dev, &new_state); 1036 if (err) 1037 return; 1038 } 1039 1040 /* state hasn't changed */ 1041 if (likely(new_state == priv->can.state)) 1042 return; 1043 1044 skb = alloc_can_err_skb(dev, &cf); 1045 if (unlikely(!skb)) 1046 return; 1047 1048 at91_irq_err_state(dev, cf, new_state); 1049 1050 dev->stats.rx_packets++; 1051 dev->stats.rx_bytes += cf->can_dlc; 1052 netif_rx(skb); 1053 1054 priv->can.state = new_state; 1055} 1056 1057/* 1058 * interrupt handler 1059 */ 1060static irqreturn_t at91_irq(int irq, void *dev_id) 1061{ 1062 struct net_device *dev = dev_id; 1063 struct at91_priv *priv = netdev_priv(dev); 1064 irqreturn_t handled = IRQ_NONE; 1065 u32 reg_sr, reg_imr; 1066 1067 reg_sr = at91_read(priv, AT91_SR); 1068 reg_imr = at91_read(priv, AT91_IMR); 1069 1070 /* Ignore masked interrupts */ 1071 reg_sr &= reg_imr; 1072 if (!reg_sr) 1073 goto exit; 1074 1075 handled = IRQ_HANDLED; 1076 1077 /* Receive or error interrupt? -> napi */ 1078 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1079 /* 1080 * The error bits are clear on read, 1081 * save for later use. 1082 */ 1083 priv->reg_sr = reg_sr; 1084 at91_write(priv, AT91_IDR, 1085 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1086 napi_schedule(&priv->napi); 1087 } 1088 1089 /* Transmission complete interrupt */ 1090 if (reg_sr & get_irq_mb_tx(priv)) 1091 at91_irq_tx(dev, reg_sr); 1092 1093 at91_irq_err(dev); 1094 1095 exit: 1096 return handled; 1097} 1098 1099static int at91_open(struct net_device *dev) 1100{ 1101 struct at91_priv *priv = netdev_priv(dev); 1102 int err; 1103 1104 err = clk_prepare_enable(priv->clk); 1105 if (err) 1106 return err; 1107 1108 /* check or determine and set bittime */ 1109 err = open_candev(dev); 1110 if (err) 1111 goto out; 1112 1113 /* register interrupt handler */ 1114 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1115 dev->name, dev)) { 1116 err = -EAGAIN; 1117 goto out_close; 1118 } 1119 1120 can_led_event(dev, CAN_LED_EVENT_OPEN); 1121 1122 /* start chip and queuing */ 1123 at91_chip_start(dev); 1124 napi_enable(&priv->napi); 1125 netif_start_queue(dev); 1126 1127 return 0; 1128 1129 out_close: 1130 close_candev(dev); 1131 out: 1132 clk_disable_unprepare(priv->clk); 1133 1134 return err; 1135} 1136 1137/* 1138 * stop CAN bus activity 1139 */ 1140static int at91_close(struct net_device *dev) 1141{ 1142 struct at91_priv *priv = netdev_priv(dev); 1143 1144 netif_stop_queue(dev); 1145 napi_disable(&priv->napi); 1146 at91_chip_stop(dev, CAN_STATE_STOPPED); 1147 1148 free_irq(dev->irq, dev); 1149 clk_disable_unprepare(priv->clk); 1150 1151 close_candev(dev); 1152 1153 can_led_event(dev, CAN_LED_EVENT_STOP); 1154 1155 return 0; 1156} 1157 1158static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1159{ 1160 switch (mode) { 1161 case CAN_MODE_START: 1162 at91_chip_start(dev); 1163 netif_wake_queue(dev); 1164 break; 1165 1166 default: 1167 return -EOPNOTSUPP; 1168 } 1169 1170 return 0; 1171} 1172 1173static const struct net_device_ops at91_netdev_ops = { 1174 .ndo_open = at91_open, 1175 .ndo_stop = at91_close, 1176 .ndo_start_xmit = at91_start_xmit, 1177 .ndo_change_mtu = can_change_mtu, 1178}; 1179 1180static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1181 struct device_attribute *attr, char *buf) 1182{ 1183 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1184 1185 if (priv->mb0_id & CAN_EFF_FLAG) 1186 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1187 else 1188 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1189} 1190 1191static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1192 struct device_attribute *attr, const char *buf, size_t count) 1193{ 1194 struct net_device *ndev = to_net_dev(dev); 1195 struct at91_priv *priv = netdev_priv(ndev); 1196 unsigned long can_id; 1197 ssize_t ret; 1198 int err; 1199 1200 rtnl_lock(); 1201 1202 if (ndev->flags & IFF_UP) { 1203 ret = -EBUSY; 1204 goto out; 1205 } 1206 1207 err = kstrtoul(buf, 0, &can_id); 1208 if (err) { 1209 ret = err; 1210 goto out; 1211 } 1212 1213 if (can_id & CAN_EFF_FLAG) 1214 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1215 else 1216 can_id &= CAN_SFF_MASK; 1217 1218 priv->mb0_id = can_id; 1219 ret = count; 1220 1221 out: 1222 rtnl_unlock(); 1223 return ret; 1224} 1225 1226static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1227 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1228 1229static struct attribute *at91_sysfs_attrs[] = { 1230 &dev_attr_mb0_id.attr, 1231 NULL, 1232}; 1233 1234static struct attribute_group at91_sysfs_attr_group = { 1235 .attrs = at91_sysfs_attrs, 1236}; 1237 1238#if defined(CONFIG_OF) 1239static const struct of_device_id at91_can_dt_ids[] = { 1240 { 1241 .compatible = "atmel,at91sam9x5-can", 1242 .data = &at91_at91sam9x5_data, 1243 }, { 1244 .compatible = "atmel,at91sam9263-can", 1245 .data = &at91_at91sam9263_data, 1246 }, { 1247 /* sentinel */ 1248 } 1249}; 1250MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1251#endif 1252 1253static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1254{ 1255 if (pdev->dev.of_node) { 1256 const struct of_device_id *match; 1257 1258 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1259 if (!match) { 1260 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1261 return NULL; 1262 } 1263 return (const struct at91_devtype_data *)match->data; 1264 } 1265 return (const struct at91_devtype_data *) 1266 platform_get_device_id(pdev)->driver_data; 1267} 1268 1269static int at91_can_probe(struct platform_device *pdev) 1270{ 1271 const struct at91_devtype_data *devtype_data; 1272 struct net_device *dev; 1273 struct at91_priv *priv; 1274 struct resource *res; 1275 struct clk *clk; 1276 void __iomem *addr; 1277 int err, irq; 1278 1279 devtype_data = at91_can_get_driver_data(pdev); 1280 if (!devtype_data) { 1281 dev_err(&pdev->dev, "no driver data\n"); 1282 err = -ENODEV; 1283 goto exit; 1284 } 1285 1286 clk = clk_get(&pdev->dev, "can_clk"); 1287 if (IS_ERR(clk)) { 1288 dev_err(&pdev->dev, "no clock defined\n"); 1289 err = -ENODEV; 1290 goto exit; 1291 } 1292 1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1294 irq = platform_get_irq(pdev, 0); 1295 if (!res || irq <= 0) { 1296 err = -ENODEV; 1297 goto exit_put; 1298 } 1299 1300 if (!request_mem_region(res->start, 1301 resource_size(res), 1302 pdev->name)) { 1303 err = -EBUSY; 1304 goto exit_put; 1305 } 1306 1307 addr = ioremap_nocache(res->start, resource_size(res)); 1308 if (!addr) { 1309 err = -ENOMEM; 1310 goto exit_release; 1311 } 1312 1313 dev = alloc_candev(sizeof(struct at91_priv), 1314 1 << devtype_data->tx_shift); 1315 if (!dev) { 1316 err = -ENOMEM; 1317 goto exit_iounmap; 1318 } 1319 1320 dev->netdev_ops = &at91_netdev_ops; 1321 dev->irq = irq; 1322 dev->flags |= IFF_ECHO; 1323 1324 priv = netdev_priv(dev); 1325 priv->can.clock.freq = clk_get_rate(clk); 1326 priv->can.bittiming_const = &at91_bittiming_const; 1327 priv->can.do_set_mode = at91_set_mode; 1328 priv->can.do_get_berr_counter = at91_get_berr_counter; 1329 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1330 CAN_CTRLMODE_LISTENONLY; 1331 priv->reg_base = addr; 1332 priv->devtype_data = *devtype_data; 1333 priv->clk = clk; 1334 priv->pdata = dev_get_platdata(&pdev->dev); 1335 priv->mb0_id = 0x7ff; 1336 1337 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1338 1339 if (at91_is_sam9263(priv)) 1340 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1341 1342 platform_set_drvdata(pdev, dev); 1343 SET_NETDEV_DEV(dev, &pdev->dev); 1344 1345 err = register_candev(dev); 1346 if (err) { 1347 dev_err(&pdev->dev, "registering netdev failed\n"); 1348 goto exit_free; 1349 } 1350 1351 devm_can_led_init(dev); 1352 1353 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1354 priv->reg_base, dev->irq); 1355 1356 return 0; 1357 1358 exit_free: 1359 free_candev(dev); 1360 exit_iounmap: 1361 iounmap(addr); 1362 exit_release: 1363 release_mem_region(res->start, resource_size(res)); 1364 exit_put: 1365 clk_put(clk); 1366 exit: 1367 return err; 1368} 1369 1370static int at91_can_remove(struct platform_device *pdev) 1371{ 1372 struct net_device *dev = platform_get_drvdata(pdev); 1373 struct at91_priv *priv = netdev_priv(dev); 1374 struct resource *res; 1375 1376 unregister_netdev(dev); 1377 1378 iounmap(priv->reg_base); 1379 1380 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1381 release_mem_region(res->start, resource_size(res)); 1382 1383 clk_put(priv->clk); 1384 1385 free_candev(dev); 1386 1387 return 0; 1388} 1389 1390static const struct platform_device_id at91_can_id_table[] = { 1391 { 1392 .name = "at91sam9x5_can", 1393 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1394 }, { 1395 .name = "at91_can", 1396 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1397 }, { 1398 /* sentinel */ 1399 } 1400}; 1401MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1402 1403static struct platform_driver at91_can_driver = { 1404 .probe = at91_can_probe, 1405 .remove = at91_can_remove, 1406 .driver = { 1407 .name = KBUILD_MODNAME, 1408 .of_match_table = of_match_ptr(at91_can_dt_ids), 1409 }, 1410 .id_table = at91_can_id_table, 1411}; 1412 1413module_platform_driver(at91_can_driver); 1414 1415MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1416MODULE_LICENSE("GPL v2"); 1417MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1418