1/*
2 * Freescale UPM NAND driver.
3 *
4 * Copyright �� 2007-2008  MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/nand_ecc.h>
19#include <linux/mtd/partitions.h>
20#include <linux/mtd/mtd.h>
21#include <linux/of_address.h>
22#include <linux/of_platform.h>
23#include <linux/of_gpio.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <asm/fsl_lbc.h>
27
28#define FSL_UPM_WAIT_RUN_PATTERN  0x1
29#define FSL_UPM_WAIT_WRITE_BYTE   0x2
30#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
31
32struct fsl_upm_nand {
33	struct device *dev;
34	struct mtd_info mtd;
35	struct nand_chip chip;
36	int last_ctrl;
37	struct mtd_partition *parts;
38	struct fsl_upm upm;
39	uint8_t upm_addr_offset;
40	uint8_t upm_cmd_offset;
41	void __iomem *io_base;
42	int rnb_gpio[NAND_MAX_CHIPS];
43	uint32_t mchip_offsets[NAND_MAX_CHIPS];
44	uint32_t mchip_count;
45	uint32_t mchip_number;
46	int chip_delay;
47	uint32_t wait_flags;
48};
49
50static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
51{
52	return container_of(mtdinfo, struct fsl_upm_nand, mtd);
53}
54
55static int fun_chip_ready(struct mtd_info *mtd)
56{
57	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
58
59	if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
60		return 1;
61
62	dev_vdbg(fun->dev, "busy\n");
63	return 0;
64}
65
66static void fun_wait_rnb(struct fsl_upm_nand *fun)
67{
68	if (fun->rnb_gpio[fun->mchip_number] >= 0) {
69		int cnt = 1000000;
70
71		while (--cnt && !fun_chip_ready(&fun->mtd))
72			cpu_relax();
73		if (!cnt)
74			dev_err(fun->dev, "tired waiting for RNB\n");
75	} else {
76		ndelay(100);
77	}
78}
79
80static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
81{
82	struct nand_chip *chip = mtd->priv;
83	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
84	u32 mar;
85
86	if (!(ctrl & fun->last_ctrl)) {
87		fsl_upm_end_pattern(&fun->upm);
88
89		if (cmd == NAND_CMD_NONE)
90			return;
91
92		fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
93	}
94
95	if (ctrl & NAND_CTRL_CHANGE) {
96		if (ctrl & NAND_ALE)
97			fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
98		else if (ctrl & NAND_CLE)
99			fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
100	}
101
102	mar = (cmd << (32 - fun->upm.width)) |
103		fun->mchip_offsets[fun->mchip_number];
104	fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
105
106	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
107		fun_wait_rnb(fun);
108}
109
110static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
111{
112	struct nand_chip *chip = mtd->priv;
113	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
114
115	if (mchip_nr == -1) {
116		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
117	} else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
118		fun->mchip_number = mchip_nr;
119		chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
120		chip->IO_ADDR_W = chip->IO_ADDR_R;
121	} else {
122		BUG();
123	}
124}
125
126static uint8_t fun_read_byte(struct mtd_info *mtd)
127{
128	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
129
130	return in_8(fun->chip.IO_ADDR_R);
131}
132
133static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
134{
135	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
136	int i;
137
138	for (i = 0; i < len; i++)
139		buf[i] = in_8(fun->chip.IO_ADDR_R);
140}
141
142static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
143{
144	struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
145	int i;
146
147	for (i = 0; i < len; i++) {
148		out_8(fun->chip.IO_ADDR_W, buf[i]);
149		if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
150			fun_wait_rnb(fun);
151	}
152	if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
153		fun_wait_rnb(fun);
154}
155
156static int fun_chip_init(struct fsl_upm_nand *fun,
157			 const struct device_node *upm_np,
158			 const struct resource *io_res)
159{
160	int ret;
161	struct device_node *flash_np;
162	struct mtd_part_parser_data ppdata;
163
164	fun->chip.IO_ADDR_R = fun->io_base;
165	fun->chip.IO_ADDR_W = fun->io_base;
166	fun->chip.cmd_ctrl = fun_cmd_ctrl;
167	fun->chip.chip_delay = fun->chip_delay;
168	fun->chip.read_byte = fun_read_byte;
169	fun->chip.read_buf = fun_read_buf;
170	fun->chip.write_buf = fun_write_buf;
171	fun->chip.ecc.mode = NAND_ECC_SOFT;
172	if (fun->mchip_count > 1)
173		fun->chip.select_chip = fun_select_chip;
174
175	if (fun->rnb_gpio[0] >= 0)
176		fun->chip.dev_ready = fun_chip_ready;
177
178	fun->mtd.priv = &fun->chip;
179	fun->mtd.dev.parent = fun->dev;
180
181	flash_np = of_get_next_child(upm_np, NULL);
182	if (!flash_np)
183		return -ENODEV;
184
185	fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
186				  flash_np->name);
187	if (!fun->mtd.name) {
188		ret = -ENOMEM;
189		goto err;
190	}
191
192	ret = nand_scan(&fun->mtd, fun->mchip_count);
193	if (ret)
194		goto err;
195
196	ppdata.of_node = flash_np;
197	ret = mtd_device_parse_register(&fun->mtd, NULL, &ppdata, NULL, 0);
198err:
199	of_node_put(flash_np);
200	if (ret)
201		kfree(fun->mtd.name);
202	return ret;
203}
204
205static int fun_probe(struct platform_device *ofdev)
206{
207	struct fsl_upm_nand *fun;
208	struct resource io_res;
209	const __be32 *prop;
210	int rnb_gpio;
211	int ret;
212	int size;
213	int i;
214
215	fun = kzalloc(sizeof(*fun), GFP_KERNEL);
216	if (!fun)
217		return -ENOMEM;
218
219	ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
220	if (ret) {
221		dev_err(&ofdev->dev, "can't get IO base\n");
222		goto err1;
223	}
224
225	ret = fsl_upm_find(io_res.start, &fun->upm);
226	if (ret) {
227		dev_err(&ofdev->dev, "can't find UPM\n");
228		goto err1;
229	}
230
231	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
232			       &size);
233	if (!prop || size != sizeof(uint32_t)) {
234		dev_err(&ofdev->dev, "can't get UPM address offset\n");
235		ret = -EINVAL;
236		goto err1;
237	}
238	fun->upm_addr_offset = *prop;
239
240	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
241	if (!prop || size != sizeof(uint32_t)) {
242		dev_err(&ofdev->dev, "can't get UPM command offset\n");
243		ret = -EINVAL;
244		goto err1;
245	}
246	fun->upm_cmd_offset = *prop;
247
248	prop = of_get_property(ofdev->dev.of_node,
249			       "fsl,upm-addr-line-cs-offsets", &size);
250	if (prop && (size / sizeof(uint32_t)) > 0) {
251		fun->mchip_count = size / sizeof(uint32_t);
252		if (fun->mchip_count >= NAND_MAX_CHIPS) {
253			dev_err(&ofdev->dev, "too much multiple chips\n");
254			goto err1;
255		}
256		for (i = 0; i < fun->mchip_count; i++)
257			fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
258	} else {
259		fun->mchip_count = 1;
260	}
261
262	for (i = 0; i < fun->mchip_count; i++) {
263		fun->rnb_gpio[i] = -1;
264		rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
265		if (rnb_gpio >= 0) {
266			ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
267			if (ret) {
268				dev_err(&ofdev->dev,
269					"can't request RNB gpio #%d\n", i);
270				goto err2;
271			}
272			gpio_direction_input(rnb_gpio);
273			fun->rnb_gpio[i] = rnb_gpio;
274		} else if (rnb_gpio == -EINVAL) {
275			dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
276			goto err2;
277		}
278	}
279
280	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
281	if (prop)
282		fun->chip_delay = be32_to_cpup(prop);
283	else
284		fun->chip_delay = 50;
285
286	prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
287	if (prop && size == sizeof(uint32_t))
288		fun->wait_flags = be32_to_cpup(prop);
289	else
290		fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
291				  FSL_UPM_WAIT_WRITE_BYTE;
292
293	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
294					    resource_size(&io_res));
295	if (!fun->io_base) {
296		ret = -ENOMEM;
297		goto err2;
298	}
299
300	fun->dev = &ofdev->dev;
301	fun->last_ctrl = NAND_CLE;
302
303	ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
304	if (ret)
305		goto err2;
306
307	dev_set_drvdata(&ofdev->dev, fun);
308
309	return 0;
310err2:
311	for (i = 0; i < fun->mchip_count; i++) {
312		if (fun->rnb_gpio[i] < 0)
313			break;
314		gpio_free(fun->rnb_gpio[i]);
315	}
316err1:
317	kfree(fun);
318
319	return ret;
320}
321
322static int fun_remove(struct platform_device *ofdev)
323{
324	struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
325	int i;
326
327	nand_release(&fun->mtd);
328	kfree(fun->mtd.name);
329
330	for (i = 0; i < fun->mchip_count; i++) {
331		if (fun->rnb_gpio[i] < 0)
332			break;
333		gpio_free(fun->rnb_gpio[i]);
334	}
335
336	kfree(fun);
337
338	return 0;
339}
340
341static const struct of_device_id of_fun_match[] = {
342	{ .compatible = "fsl,upm-nand" },
343	{},
344};
345MODULE_DEVICE_TABLE(of, of_fun_match);
346
347static struct platform_driver of_fun_driver = {
348	.driver = {
349		.name = "fsl,upm-nand",
350		.of_match_table = of_fun_match,
351	},
352	.probe		= fun_probe,
353	.remove		= fun_remove,
354};
355
356module_platform_driver(of_fun_driver);
357
358MODULE_LICENSE("GPL");
359MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
360MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
361		   "LocalBus User-Programmable Machine");
362