1/* 2 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver 3 * 4 * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12#ifndef _DW_MMC_EXYNOS_H_ 13#define _DW_MMC_EXYNOS_H_ 14 15#define SDMMC_CLKSEL 0x09C 16#define SDMMC_CLKSEL64 0x0A8 17 18/* Extended Register's Offset */ 19#define SDMMC_HS400_DQS_EN 0x180 20#define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184 21#define SDMMC_HS400_DLINE_CTRL 0x188 22 23/* CLKSEL register defines */ 24#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) 25#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) 26#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) 27#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) 28#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7) 29#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\ 30 SDMMC_CLKSEL_CCLK_SAMPLE(y)) 31#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ 32 SDMMC_CLKSEL_CCLK_DRIVE(y) | \ 33 SDMMC_CLKSEL_CCLK_DIVIDER(z)) 34#define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) 35#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) 36 37/* RCLK_EN register defines */ 38#define DATA_STROBE_EN BIT(0) 39#define AXI_NON_BLOCKING_WR BIT(7) 40 41/* DLINE_CTRL register defines */ 42#define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF)) 43#define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF) 44 45/* Protector Register */ 46#define SDMMC_EMMCP_BASE 0x1000 47#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) 48#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) 49#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) 50#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) 51 52/* SMU control defines */ 53#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) 54#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) 55#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) 56#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) 57#define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) 58#define SDMMC_MPSCTRL_ECB_MODE BIT(2) 59#define SDMMC_MPSCTRL_ENCRYPTION BIT(1) 60#define SDMMC_MPSCTRL_VALID BIT(0) 61 62/* Maximum number of Ending sector */ 63#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF 64 65/* Fixed clock divider */ 66#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 67#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 68#define HS400_FIXED_CIU_CLK_DIV 1 69 70/* Minimal required clock frequency for cclkin, unit: HZ */ 71#define EXYNOS_CCLKIN_MIN 50000000 72 73#endif /* _DW_MMC_EXYNOS_H_ */ 74