1/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
2 * Copyright (c) 2010, Google Inc.
3 *
4 * Original authors: Code Aurora Forum
5 *
6 * Author: Dima Zavin <dima@android.com>
7 *  - Largely rewritten from original to not be an i2c driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 and
11 * only version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 */
18
19#define pr_fmt(fmt) "%s: " fmt, __func__
20
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/ssbi.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31
32/* SSBI 2.0 controller registers */
33#define SSBI2_CMD			0x0008
34#define SSBI2_RD			0x0010
35#define SSBI2_STATUS			0x0014
36#define SSBI2_MODE2			0x001C
37
38/* SSBI_CMD fields */
39#define SSBI_CMD_RDWRN			(1 << 24)
40
41/* SSBI_STATUS fields */
42#define SSBI_STATUS_RD_READY		(1 << 2)
43#define SSBI_STATUS_READY		(1 << 1)
44#define SSBI_STATUS_MCHN_BUSY		(1 << 0)
45
46/* SSBI_MODE2 fields */
47#define SSBI_MODE2_REG_ADDR_15_8_SHFT	0x04
48#define SSBI_MODE2_REG_ADDR_15_8_MASK	(0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
49
50#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
51	(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
52	SSBI_MODE2_REG_ADDR_15_8_MASK))
53
54/* SSBI PMIC Arbiter command registers */
55#define SSBI_PA_CMD			0x0000
56#define SSBI_PA_RD_STATUS		0x0004
57
58/* SSBI_PA_CMD fields */
59#define SSBI_PA_CMD_RDWRN		(1 << 24)
60#define SSBI_PA_CMD_ADDR_MASK		0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
61
62/* SSBI_PA_RD_STATUS fields */
63#define SSBI_PA_RD_STATUS_TRANS_DONE	(1 << 27)
64#define SSBI_PA_RD_STATUS_TRANS_DENIED	(1 << 26)
65
66#define SSBI_TIMEOUT_US			100
67
68enum ssbi_controller_type {
69	MSM_SBI_CTRL_SSBI = 0,
70	MSM_SBI_CTRL_SSBI2,
71	MSM_SBI_CTRL_PMIC_ARBITER,
72};
73
74struct ssbi {
75	struct device		*slave;
76	void __iomem		*base;
77	spinlock_t		lock;
78	enum ssbi_controller_type controller_type;
79	int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
80	int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
81};
82
83#define to_ssbi(dev)	platform_get_drvdata(to_platform_device(dev))
84
85static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
86{
87	return readl(ssbi->base + reg);
88}
89
90static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
91{
92	writel(val, ssbi->base + reg);
93}
94
95/*
96 * Via private exchange with one of the original authors, the hardware
97 * should generally finish a transaction in about 5us.  The worst
98 * case, is when using the arbiter and both other CPUs have just
99 * started trying to use the SSBI bus will result in a time of about
100 * 20us.  It should never take longer than this.
101 *
102 * As such, this wait merely spins, with a udelay.
103 */
104static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
105{
106	u32 timeout = SSBI_TIMEOUT_US;
107	u32 val;
108
109	while (timeout--) {
110		val = ssbi_readl(ssbi, SSBI2_STATUS);
111		if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
112			return 0;
113		udelay(1);
114	}
115
116	return -ETIMEDOUT;
117}
118
119static int
120ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
121{
122	u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
123	int ret = 0;
124
125	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
126		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
127		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
128		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
129	}
130
131	while (len) {
132		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
133		if (ret)
134			goto err;
135
136		ssbi_writel(ssbi, cmd, SSBI2_CMD);
137		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
138		if (ret)
139			goto err;
140		*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
141		len--;
142	}
143
144err:
145	return ret;
146}
147
148static int
149ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
150{
151	int ret = 0;
152
153	if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
154		u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
155		mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
156		ssbi_writel(ssbi, mode2, SSBI2_MODE2);
157	}
158
159	while (len) {
160		ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
161		if (ret)
162			goto err;
163
164		ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
165		ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
166		if (ret)
167			goto err;
168		buf++;
169		len--;
170	}
171
172err:
173	return ret;
174}
175
176/*
177 * See ssbi_wait_mask for an explanation of the time and the
178 * busywait.
179 */
180static inline int
181ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
182{
183	u32 timeout = SSBI_TIMEOUT_US;
184	u32 rd_status = 0;
185
186	ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
187
188	while (timeout--) {
189		rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
190
191		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
192			return -EPERM;
193
194		if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
195			if (data)
196				*data = rd_status & 0xff;
197			return 0;
198		}
199		udelay(1);
200	}
201
202	return -ETIMEDOUT;
203}
204
205static int
206ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
207{
208	u32 cmd;
209	int ret = 0;
210
211	cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
212
213	while (len) {
214		ret = ssbi_pa_transfer(ssbi, cmd, buf);
215		if (ret)
216			goto err;
217		buf++;
218		len--;
219	}
220
221err:
222	return ret;
223}
224
225static int
226ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
227{
228	u32 cmd;
229	int ret = 0;
230
231	while (len) {
232		cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
233		ret = ssbi_pa_transfer(ssbi, cmd, NULL);
234		if (ret)
235			goto err;
236		buf++;
237		len--;
238	}
239
240err:
241	return ret;
242}
243
244int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
245{
246	struct ssbi *ssbi = to_ssbi(dev);
247	unsigned long flags;
248	int ret;
249
250	spin_lock_irqsave(&ssbi->lock, flags);
251	ret = ssbi->read(ssbi, addr, buf, len);
252	spin_unlock_irqrestore(&ssbi->lock, flags);
253
254	return ret;
255}
256EXPORT_SYMBOL_GPL(ssbi_read);
257
258int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
259{
260	struct ssbi *ssbi = to_ssbi(dev);
261	unsigned long flags;
262	int ret;
263
264	spin_lock_irqsave(&ssbi->lock, flags);
265	ret = ssbi->write(ssbi, addr, buf, len);
266	spin_unlock_irqrestore(&ssbi->lock, flags);
267
268	return ret;
269}
270EXPORT_SYMBOL_GPL(ssbi_write);
271
272static int ssbi_probe(struct platform_device *pdev)
273{
274	struct device_node *np = pdev->dev.of_node;
275	struct resource *mem_res;
276	struct ssbi *ssbi;
277	const char *type;
278
279	ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
280	if (!ssbi)
281		return -ENOMEM;
282
283	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284	ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
285	if (IS_ERR(ssbi->base))
286		return PTR_ERR(ssbi->base);
287
288	platform_set_drvdata(pdev, ssbi);
289
290	type = of_get_property(np, "qcom,controller-type", NULL);
291	if (type == NULL) {
292		dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
293		return -EINVAL;
294	}
295	dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
296	if (strcmp(type, "ssbi") == 0)
297		ssbi->controller_type = MSM_SBI_CTRL_SSBI;
298	else if (strcmp(type, "ssbi2") == 0)
299		ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
300	else if (strcmp(type, "pmic-arbiter") == 0)
301		ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
302	else {
303		dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
304		return -EINVAL;
305	}
306
307	if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
308		ssbi->read = ssbi_pa_read_bytes;
309		ssbi->write = ssbi_pa_write_bytes;
310	} else {
311		ssbi->read = ssbi_read_bytes;
312		ssbi->write = ssbi_write_bytes;
313	}
314
315	spin_lock_init(&ssbi->lock);
316
317	return of_platform_populate(np, NULL, NULL, &pdev->dev);
318}
319
320static const struct of_device_id ssbi_match_table[] = {
321	{ .compatible = "qcom,ssbi" },
322	{}
323};
324MODULE_DEVICE_TABLE(of, ssbi_match_table);
325
326static struct platform_driver ssbi_driver = {
327	.probe		= ssbi_probe,
328	.driver		= {
329		.name	= "ssbi",
330		.of_match_table = ssbi_match_table,
331	},
332};
333module_platform_driver(ssbi_driver);
334
335MODULE_LICENSE("GPL v2");
336MODULE_VERSION("1.0");
337MODULE_ALIAS("platform:ssbi");
338MODULE_AUTHOR("Dima Zavin <dima@android.com>");
339