1/*
2 *  Driver for the Conexant CX25821 PCIe bridge
3 *
4 *  Copyright (C) 2009 Conexant Systems Inc.
5 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 *  This program is free software; you can redistribute it and/or modify
8 *  it under the terms of the GNU General Public License as published by
9 *  the Free Software Foundation; either version 2 of the License, or
10 *  (at your option) any later version.
11 *
12 *  This program is distributed in the hope that it will be useful,
13 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 *
16 *  GNU General Public License for more details.
17 *
18 *  You should have received a copy of the GNU General Public License
19 *  along with this program; if not, write to the Free Software
20 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __ATHENA_SRAM_H__
24#define __ATHENA_SRAM_H__
25
26/* #define RX_SRAM_START_SIZE        = 0;  //  Start of reserved SRAM */
27#define VID_CMDS_SIZE             80	/* Video CMDS size in bytes */
28#define AUDIO_CMDS_SIZE           80	/* AUDIO CMDS size in bytes */
29#define MBIF_CMDS_SIZE            80	/* MBIF  CMDS size in bytes */
30
31/* #define RX_SRAM_POOL_START_SIZE   = 0;  //  Start of useable RX SRAM for buffers */
32#define VID_IQ_SIZE               64	/* VID instruction queue size in bytes */
33#define MBIF_IQ_SIZE              64
34#define AUDIO_IQ_SIZE             64	/* AUD instruction queue size in bytes */
35
36#define VID_CDT_SIZE              64	/* VID cluster descriptor table size in bytes */
37#define MBIF_CDT_SIZE             64	/* MBIF/HBI cluster descriptor table size in bytes */
38#define AUDIO_CDT_SIZE            48	/* AUD cluster descriptor table size in bytes */
39
40/* #define RX_SRAM_POOL_FREE_SIZE    = 16; //  Start of available RX SRAM */
41/* #define RX_SRAM_END_SIZE          = 0;  //  End of RX SRAM */
42
43/* #define TX_SRAM_POOL_START_SIZE   = 0;  //  Start of transmit pool SRAM */
44/* #define MSI_DATA_SIZE             = 64; //  Reserved (MSI Data, RISC working stora */
45
46#define VID_CLUSTER_SIZE          1440	/* VID cluster data line */
47#define AUDIO_CLUSTER_SIZE        128	/* AUDIO cluster data line */
48#define MBIF_CLUSTER_SIZE         1440	/* MBIF/HBI cluster data line */
49
50/* #define TX_SRAM_POOL_FREE_SIZE    = 704;    //  Start of available TX SRAM */
51/* #define TX_SRAM_END_SIZE          = 0;      //  End of TX SRAM */
52
53/* Receive SRAM */
54#define RX_SRAM_START             0x10000
55#define VID_A_DOWN_CMDS           0x10000
56#define VID_B_DOWN_CMDS           0x10050
57#define VID_C_DOWN_CMDS           0x100A0
58#define VID_D_DOWN_CMDS           0x100F0
59#define VID_E_DOWN_CMDS           0x10140
60#define VID_F_DOWN_CMDS           0x10190
61#define VID_G_DOWN_CMDS           0x101E0
62#define VID_H_DOWN_CMDS           0x10230
63#define VID_A_UP_CMDS             0x10280
64#define VID_B_UP_CMDS             0x102D0
65#define VID_C_UP_CMDS             0x10320
66#define VID_D_UP_CMDS             0x10370
67#define VID_E_UP_CMDS             0x103C0
68#define VID_F_UP_CMDS             0x10410
69#define VID_I_UP_CMDS             0x10460
70#define VID_J_UP_CMDS             0x104B0
71#define AUD_A_DOWN_CMDS           0x10500
72#define AUD_B_DOWN_CMDS           0x10550
73#define AUD_C_DOWN_CMDS           0x105A0
74#define AUD_D_DOWN_CMDS           0x105F0
75#define AUD_A_UP_CMDS             0x10640
76#define AUD_B_UP_CMDS             0x10690
77#define AUD_C_UP_CMDS             0x106E0
78#define AUD_E_UP_CMDS             0x10730
79#define MBIF_A_DOWN_CMDS          0x10780
80#define MBIF_B_DOWN_CMDS          0x107D0
81#define DMA_SCRATCH_PAD           0x10820	/* Scratch pad area from 0x10820 to 0x10B40 */
82
83/* #define RX_SRAM_POOL_START        = 0x105B0; */
84
85#define VID_A_IQ                  0x11000
86#define VID_B_IQ                  0x11040
87#define VID_C_IQ                  0x11080
88#define VID_D_IQ                  0x110C0
89#define VID_E_IQ                  0x11100
90#define VID_F_IQ                  0x11140
91#define VID_G_IQ                  0x11180
92#define VID_H_IQ                  0x111C0
93#define VID_I_IQ                  0x11200
94#define VID_J_IQ                  0x11240
95#define AUD_A_IQ                  0x11280
96#define AUD_B_IQ                  0x112C0
97#define AUD_C_IQ                  0x11300
98#define AUD_D_IQ                  0x11340
99#define AUD_E_IQ                  0x11380
100#define MBIF_A_IQ                 0x11000
101#define MBIF_B_IQ                 0x110C0
102
103#define VID_A_CDT                 0x10C00
104#define VID_B_CDT                 0x10C40
105#define VID_C_CDT                 0x10C80
106#define VID_D_CDT                 0x10CC0
107#define VID_E_CDT                 0x10D00
108#define VID_F_CDT                 0x10D40
109#define VID_G_CDT                 0x10D80
110#define VID_H_CDT                 0x10DC0
111#define VID_I_CDT                 0x10E00
112#define VID_J_CDT                 0x10E40
113#define AUD_A_CDT                 0x10E80
114#define AUD_B_CDT                 0x10EB0
115#define AUD_C_CDT                 0x10EE0
116#define AUD_D_CDT                 0x10F10
117#define AUD_E_CDT                 0x10F40
118#define MBIF_A_CDT                0x10C00
119#define MBIF_B_CDT                0x10CC0
120
121/* Cluster Buffer for RX */
122#define VID_A_UP_CLUSTER_1        0x11400
123#define VID_A_UP_CLUSTER_2        0x119A0
124#define VID_A_UP_CLUSTER_3        0x11F40
125#define VID_A_UP_CLUSTER_4        0x124E0
126
127#define VID_B_UP_CLUSTER_1        0x12A80
128#define VID_B_UP_CLUSTER_2        0x13020
129#define VID_B_UP_CLUSTER_3        0x135C0
130#define VID_B_UP_CLUSTER_4        0x13B60
131
132#define VID_C_UP_CLUSTER_1        0x14100
133#define VID_C_UP_CLUSTER_2        0x146A0
134#define VID_C_UP_CLUSTER_3        0x14C40
135#define VID_C_UP_CLUSTER_4        0x151E0
136
137#define VID_D_UP_CLUSTER_1        0x15780
138#define VID_D_UP_CLUSTER_2        0x15D20
139#define VID_D_UP_CLUSTER_3        0x162C0
140#define VID_D_UP_CLUSTER_4        0x16860
141
142#define VID_E_UP_CLUSTER_1        0x16E00
143#define VID_E_UP_CLUSTER_2        0x173A0
144#define VID_E_UP_CLUSTER_3        0x17940
145#define VID_E_UP_CLUSTER_4        0x17EE0
146
147#define VID_F_UP_CLUSTER_1        0x18480
148#define VID_F_UP_CLUSTER_2        0x18A20
149#define VID_F_UP_CLUSTER_3        0x18FC0
150#define VID_F_UP_CLUSTER_4        0x19560
151
152#define VID_I_UP_CLUSTER_1        0x19B00
153#define VID_I_UP_CLUSTER_2        0x1A0A0
154#define VID_I_UP_CLUSTER_3        0x1A640
155#define VID_I_UP_CLUSTER_4        0x1ABE0
156
157#define VID_J_UP_CLUSTER_1        0x1B180
158#define VID_J_UP_CLUSTER_2        0x1B720
159#define VID_J_UP_CLUSTER_3        0x1BCC0
160#define VID_J_UP_CLUSTER_4        0x1C260
161
162#define AUD_A_UP_CLUSTER_1        0x1C800
163#define AUD_A_UP_CLUSTER_2        0x1C880
164#define AUD_A_UP_CLUSTER_3        0x1C900
165
166#define AUD_B_UP_CLUSTER_1        0x1C980
167#define AUD_B_UP_CLUSTER_2        0x1CA00
168#define AUD_B_UP_CLUSTER_3        0x1CA80
169
170#define AUD_C_UP_CLUSTER_1        0x1CB00
171#define AUD_C_UP_CLUSTER_2        0x1CB80
172#define AUD_C_UP_CLUSTER_3        0x1CC00
173
174#define AUD_E_UP_CLUSTER_1        0x1CC80
175#define AUD_E_UP_CLUSTER_2        0x1CD00
176#define AUD_E_UP_CLUSTER_3        0x1CD80
177
178#define RX_SRAM_POOL_FREE         0x1CE00
179#define RX_SRAM_END               0x1D000
180
181/* Free Receive SRAM    144 Bytes */
182
183/* Transmit SRAM */
184#define TX_SRAM_POOL_START        0x00000
185
186#define VID_A_DOWN_CLUSTER_1      0x00040
187#define VID_A_DOWN_CLUSTER_2      0x005E0
188#define VID_A_DOWN_CLUSTER_3      0x00B80
189#define VID_A_DOWN_CLUSTER_4      0x01120
190
191#define VID_B_DOWN_CLUSTER_1      0x016C0
192#define VID_B_DOWN_CLUSTER_2      0x01C60
193#define VID_B_DOWN_CLUSTER_3      0x02200
194#define VID_B_DOWN_CLUSTER_4      0x027A0
195
196#define VID_C_DOWN_CLUSTER_1      0x02D40
197#define VID_C_DOWN_CLUSTER_2      0x032E0
198#define VID_C_DOWN_CLUSTER_3      0x03880
199#define VID_C_DOWN_CLUSTER_4      0x03E20
200
201#define VID_D_DOWN_CLUSTER_1      0x043C0
202#define VID_D_DOWN_CLUSTER_2      0x04960
203#define VID_D_DOWN_CLUSTER_3      0x04F00
204#define VID_D_DOWN_CLUSTER_4      0x054A0
205
206#define VID_E_DOWN_CLUSTER_1      0x05a40
207#define VID_E_DOWN_CLUSTER_2      0x05FE0
208#define VID_E_DOWN_CLUSTER_3      0x06580
209#define VID_E_DOWN_CLUSTER_4      0x06B20
210
211#define VID_F_DOWN_CLUSTER_1      0x070C0
212#define VID_F_DOWN_CLUSTER_2      0x07660
213#define VID_F_DOWN_CLUSTER_3      0x07C00
214#define VID_F_DOWN_CLUSTER_4      0x081A0
215
216#define VID_G_DOWN_CLUSTER_1      0x08740
217#define VID_G_DOWN_CLUSTER_2      0x08CE0
218#define VID_G_DOWN_CLUSTER_3      0x09280
219#define VID_G_DOWN_CLUSTER_4      0x09820
220
221#define VID_H_DOWN_CLUSTER_1      0x09DC0
222#define VID_H_DOWN_CLUSTER_2      0x0A360
223#define VID_H_DOWN_CLUSTER_3      0x0A900
224#define VID_H_DOWN_CLUSTER_4      0x0AEA0
225
226#define AUD_A_DOWN_CLUSTER_1      0x0B500
227#define AUD_A_DOWN_CLUSTER_2      0x0B580
228#define AUD_A_DOWN_CLUSTER_3      0x0B600
229
230#define AUD_B_DOWN_CLUSTER_1      0x0B680
231#define AUD_B_DOWN_CLUSTER_2      0x0B700
232#define AUD_B_DOWN_CLUSTER_3      0x0B780
233
234#define AUD_C_DOWN_CLUSTER_1      0x0B800
235#define AUD_C_DOWN_CLUSTER_2      0x0B880
236#define AUD_C_DOWN_CLUSTER_3      0x0B900
237
238#define AUD_D_DOWN_CLUSTER_1      0x0B980
239#define AUD_D_DOWN_CLUSTER_2      0x0BA00
240#define AUD_D_DOWN_CLUSTER_3      0x0BA80
241
242#define TX_SRAM_POOL_FREE         0x0BB00
243#define TX_SRAM_END               0x0C000
244
245#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)
246#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)
247#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)
248
249#define VID_IQ_SIZE_DW             BYTES_TO_DWORDS(VID_IQ_SIZE)
250#define VID_CDT_SIZE_QW            BYTES_TO_QWORDS(VID_CDT_SIZE)
251#define VID_CLUSTER_SIZE_OW        BYTES_TO_OWORDS(VID_CLUSTER_SIZE)
252
253#define AUDIO_IQ_SIZE_DW           BYTES_TO_DWORDS(AUDIO_IQ_SIZE)
254#define AUDIO_CDT_SIZE_QW          BYTES_TO_QWORDS(AUDIO_CDT_SIZE)
255#define AUDIO_CLUSTER_SIZE_QW      BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)
256
257#define MBIF_IQ_SIZE_DW            BYTES_TO_DWORDS(MBIF_IQ_SIZE)
258#define MBIF_CDT_SIZE_QW           BYTES_TO_QWORDS(MBIF_CDT_SIZE)
259#define MBIF_CLUSTER_SIZE_OW       BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
260
261#endif
262