1/* 2 * adv7180.c Analog Devices ADV7180 video decoder driver 3 * Copyright (c) 2009 Intel Corporation 4 * Copyright (C) 2013 Cogent Embedded, Inc. 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21#include <linux/module.h> 22#include <linux/init.h> 23#include <linux/errno.h> 24#include <linux/kernel.h> 25#include <linux/interrupt.h> 26#include <linux/i2c.h> 27#include <linux/slab.h> 28#include <linux/of.h> 29#include <media/v4l2-ioctl.h> 30#include <linux/videodev2.h> 31#include <media/v4l2-device.h> 32#include <media/v4l2-ctrls.h> 33#include <linux/mutex.h> 34#include <linux/delay.h> 35 36#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 37#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 38#define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 39#define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 40#define ADV7180_STD_NTSC_J 0x4 41#define ADV7180_STD_NTSC_M 0x5 42#define ADV7180_STD_PAL60 0x6 43#define ADV7180_STD_NTSC_443 0x7 44#define ADV7180_STD_PAL_BG 0x8 45#define ADV7180_STD_PAL_N 0x9 46#define ADV7180_STD_PAL_M 0xa 47#define ADV7180_STD_PAL_M_PED 0xb 48#define ADV7180_STD_PAL_COMB_N 0xc 49#define ADV7180_STD_PAL_COMB_N_PED 0xd 50#define ADV7180_STD_PAL_SECAM 0xe 51#define ADV7180_STD_PAL_SECAM_PED 0xf 52 53#define ADV7180_REG_INPUT_CONTROL 0x0000 54#define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 55 56#define ADV7182_REG_INPUT_VIDSEL 0x0002 57 58#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 59#define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 60 61#define ADV7180_REG_AUTODETECT_ENABLE 0x07 62#define ADV7180_AUTODETECT_DEFAULT 0x7f 63/* Contrast */ 64#define ADV7180_REG_CON 0x0008 /*Unsigned */ 65#define ADV7180_CON_MIN 0 66#define ADV7180_CON_DEF 128 67#define ADV7180_CON_MAX 255 68/* Brightness*/ 69#define ADV7180_REG_BRI 0x000a /*Signed */ 70#define ADV7180_BRI_MIN -128 71#define ADV7180_BRI_DEF 0 72#define ADV7180_BRI_MAX 127 73/* Hue */ 74#define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 75#define ADV7180_HUE_MIN -127 76#define ADV7180_HUE_DEF 0 77#define ADV7180_HUE_MAX 128 78 79#define ADV7180_REG_CTRL 0x000e 80#define ADV7180_CTRL_IRQ_SPACE 0x20 81 82#define ADV7180_REG_PWR_MAN 0x0f 83#define ADV7180_PWR_MAN_ON 0x04 84#define ADV7180_PWR_MAN_OFF 0x24 85#define ADV7180_PWR_MAN_RES 0x80 86 87#define ADV7180_REG_STATUS1 0x0010 88#define ADV7180_STATUS1_IN_LOCK 0x01 89#define ADV7180_STATUS1_AUTOD_MASK 0x70 90#define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 91#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 92#define ADV7180_STATUS1_AUTOD_PAL_M 0x20 93#define ADV7180_STATUS1_AUTOD_PAL_60 0x30 94#define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 95#define ADV7180_STATUS1_AUTOD_SECAM 0x50 96#define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 97#define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 98 99#define ADV7180_REG_IDENT 0x0011 100#define ADV7180_ID_7180 0x18 101 102#define ADV7180_REG_ICONF1 0x0040 103#define ADV7180_ICONF1_ACTIVE_LOW 0x01 104#define ADV7180_ICONF1_PSYNC_ONLY 0x10 105#define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 106/* Saturation */ 107#define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 108#define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 109#define ADV7180_SAT_MIN 0 110#define ADV7180_SAT_DEF 128 111#define ADV7180_SAT_MAX 255 112 113#define ADV7180_IRQ1_LOCK 0x01 114#define ADV7180_IRQ1_UNLOCK 0x02 115#define ADV7180_REG_ISR1 0x0042 116#define ADV7180_REG_ICR1 0x0043 117#define ADV7180_REG_IMR1 0x0044 118#define ADV7180_REG_IMR2 0x0048 119#define ADV7180_IRQ3_AD_CHANGE 0x08 120#define ADV7180_REG_ISR3 0x004A 121#define ADV7180_REG_ICR3 0x004B 122#define ADV7180_REG_IMR3 0x004C 123#define ADV7180_REG_IMR4 0x50 124 125#define ADV7180_REG_NTSC_V_BIT_END 0x00E6 126#define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 127 128#define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 129#define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 130 131#define ADV7180_REG_FLCONTROL 0x40e0 132#define ADV7180_FLCONTROL_FL_ENABLE 0x1 133 134#define ADV7180_CSI_REG_PWRDN 0x00 135#define ADV7180_CSI_PWRDN 0x80 136 137#define ADV7180_INPUT_CVBS_AIN1 0x00 138#define ADV7180_INPUT_CVBS_AIN2 0x01 139#define ADV7180_INPUT_CVBS_AIN3 0x02 140#define ADV7180_INPUT_CVBS_AIN4 0x03 141#define ADV7180_INPUT_CVBS_AIN5 0x04 142#define ADV7180_INPUT_CVBS_AIN6 0x05 143#define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 144#define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 145#define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 146#define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 147#define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 148 149#define ADV7182_INPUT_CVBS_AIN1 0x00 150#define ADV7182_INPUT_CVBS_AIN2 0x01 151#define ADV7182_INPUT_CVBS_AIN3 0x02 152#define ADV7182_INPUT_CVBS_AIN4 0x03 153#define ADV7182_INPUT_CVBS_AIN5 0x04 154#define ADV7182_INPUT_CVBS_AIN6 0x05 155#define ADV7182_INPUT_CVBS_AIN7 0x06 156#define ADV7182_INPUT_CVBS_AIN8 0x07 157#define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 158#define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 159#define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 160#define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 161#define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 162#define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 163#define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 164#define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 165#define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 166#define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 167 168#define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 169#define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 170 171#define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 172 173struct adv7180_state; 174 175#define ADV7180_FLAG_RESET_POWERED BIT(0) 176#define ADV7180_FLAG_V2 BIT(1) 177#define ADV7180_FLAG_MIPI_CSI2 BIT(2) 178#define ADV7180_FLAG_I2P BIT(3) 179 180struct adv7180_chip_info { 181 unsigned int flags; 182 unsigned int valid_input_mask; 183 int (*set_std)(struct adv7180_state *st, unsigned int std); 184 int (*select_input)(struct adv7180_state *st, unsigned int input); 185 int (*init)(struct adv7180_state *state); 186}; 187 188struct adv7180_state { 189 struct v4l2_ctrl_handler ctrl_hdl; 190 struct v4l2_subdev sd; 191 struct media_pad pad; 192 struct mutex mutex; /* mutual excl. when accessing chip */ 193 int irq; 194 v4l2_std_id curr_norm; 195 bool autodetect; 196 bool powered; 197 u8 input; 198 199 struct i2c_client *client; 200 unsigned int register_page; 201 struct i2c_client *csi_client; 202 struct i2c_client *vpp_client; 203 const struct adv7180_chip_info *chip_info; 204 enum v4l2_field field; 205}; 206#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 207 struct adv7180_state, \ 208 ctrl_hdl)->sd) 209 210static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 211{ 212 if (state->register_page != page) { 213 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 214 page); 215 state->register_page = page; 216 } 217 218 return 0; 219} 220 221static int adv7180_write(struct adv7180_state *state, unsigned int reg, 222 unsigned int value) 223{ 224 lockdep_assert_held(&state->mutex); 225 adv7180_select_page(state, reg >> 8); 226 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 227} 228 229static int adv7180_read(struct adv7180_state *state, unsigned int reg) 230{ 231 lockdep_assert_held(&state->mutex); 232 adv7180_select_page(state, reg >> 8); 233 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 234} 235 236static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 237 unsigned int value) 238{ 239 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 240} 241 242static int adv7180_set_video_standard(struct adv7180_state *state, 243 unsigned int std) 244{ 245 return state->chip_info->set_std(state, std); 246} 247 248static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 249 unsigned int value) 250{ 251 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 252} 253 254static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 255{ 256 /* in case V4L2_IN_ST_NO_SIGNAL */ 257 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 258 return V4L2_STD_UNKNOWN; 259 260 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 261 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 262 return V4L2_STD_NTSC; 263 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 264 return V4L2_STD_NTSC_443; 265 case ADV7180_STATUS1_AUTOD_PAL_M: 266 return V4L2_STD_PAL_M; 267 case ADV7180_STATUS1_AUTOD_PAL_60: 268 return V4L2_STD_PAL_60; 269 case ADV7180_STATUS1_AUTOD_PAL_B_G: 270 return V4L2_STD_PAL; 271 case ADV7180_STATUS1_AUTOD_SECAM: 272 return V4L2_STD_SECAM; 273 case ADV7180_STATUS1_AUTOD_PAL_COMB: 274 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 275 case ADV7180_STATUS1_AUTOD_SECAM_525: 276 return V4L2_STD_SECAM; 277 default: 278 return V4L2_STD_UNKNOWN; 279 } 280} 281 282static int v4l2_std_to_adv7180(v4l2_std_id std) 283{ 284 if (std == V4L2_STD_PAL_60) 285 return ADV7180_STD_PAL60; 286 if (std == V4L2_STD_NTSC_443) 287 return ADV7180_STD_NTSC_443; 288 if (std == V4L2_STD_PAL_N) 289 return ADV7180_STD_PAL_N; 290 if (std == V4L2_STD_PAL_M) 291 return ADV7180_STD_PAL_M; 292 if (std == V4L2_STD_PAL_Nc) 293 return ADV7180_STD_PAL_COMB_N; 294 295 if (std & V4L2_STD_PAL) 296 return ADV7180_STD_PAL_BG; 297 if (std & V4L2_STD_NTSC) 298 return ADV7180_STD_NTSC_M; 299 if (std & V4L2_STD_SECAM) 300 return ADV7180_STD_PAL_SECAM; 301 302 return -EINVAL; 303} 304 305static u32 adv7180_status_to_v4l2(u8 status1) 306{ 307 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 308 return V4L2_IN_ST_NO_SIGNAL; 309 310 return 0; 311} 312 313static int __adv7180_status(struct adv7180_state *state, u32 *status, 314 v4l2_std_id *std) 315{ 316 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 317 318 if (status1 < 0) 319 return status1; 320 321 if (status) 322 *status = adv7180_status_to_v4l2(status1); 323 if (std) 324 *std = adv7180_std_to_v4l2(status1); 325 326 return 0; 327} 328 329static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 330{ 331 return container_of(sd, struct adv7180_state, sd); 332} 333 334static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 335{ 336 struct adv7180_state *state = to_state(sd); 337 int err = mutex_lock_interruptible(&state->mutex); 338 if (err) 339 return err; 340 341 /* when we are interrupt driven we know the state */ 342 if (!state->autodetect || state->irq > 0) 343 *std = state->curr_norm; 344 else 345 err = __adv7180_status(state, NULL, std); 346 347 mutex_unlock(&state->mutex); 348 return err; 349} 350 351static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 352 u32 output, u32 config) 353{ 354 struct adv7180_state *state = to_state(sd); 355 int ret = mutex_lock_interruptible(&state->mutex); 356 357 if (ret) 358 return ret; 359 360 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 361 ret = -EINVAL; 362 goto out; 363 } 364 365 ret = state->chip_info->select_input(state, input); 366 367 if (ret == 0) 368 state->input = input; 369out: 370 mutex_unlock(&state->mutex); 371 return ret; 372} 373 374static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 375{ 376 struct adv7180_state *state = to_state(sd); 377 int ret = mutex_lock_interruptible(&state->mutex); 378 if (ret) 379 return ret; 380 381 ret = __adv7180_status(state, status, NULL); 382 mutex_unlock(&state->mutex); 383 return ret; 384} 385 386static int adv7180_program_std(struct adv7180_state *state) 387{ 388 int ret; 389 390 if (state->autodetect) { 391 ret = adv7180_set_video_standard(state, 392 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 393 if (ret < 0) 394 return ret; 395 396 __adv7180_status(state, NULL, &state->curr_norm); 397 } else { 398 ret = v4l2_std_to_adv7180(state->curr_norm); 399 if (ret < 0) 400 return ret; 401 402 ret = adv7180_set_video_standard(state, ret); 403 if (ret < 0) 404 return ret; 405 } 406 407 return 0; 408} 409 410static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 411{ 412 struct adv7180_state *state = to_state(sd); 413 int ret = mutex_lock_interruptible(&state->mutex); 414 415 if (ret) 416 return ret; 417 418 /* all standards -> autodetect */ 419 if (std == V4L2_STD_ALL) { 420 state->autodetect = true; 421 } else { 422 /* Make sure we can support this std */ 423 ret = v4l2_std_to_adv7180(std); 424 if (ret < 0) 425 goto out; 426 427 state->curr_norm = std; 428 state->autodetect = false; 429 } 430 431 ret = adv7180_program_std(state); 432out: 433 mutex_unlock(&state->mutex); 434 return ret; 435} 436 437static int adv7180_set_power(struct adv7180_state *state, bool on) 438{ 439 u8 val; 440 int ret; 441 442 if (on) 443 val = ADV7180_PWR_MAN_ON; 444 else 445 val = ADV7180_PWR_MAN_OFF; 446 447 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 448 if (ret) 449 return ret; 450 451 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 452 if (on) { 453 adv7180_csi_write(state, 0xDE, 0x02); 454 adv7180_csi_write(state, 0xD2, 0xF7); 455 adv7180_csi_write(state, 0xD8, 0x65); 456 adv7180_csi_write(state, 0xE0, 0x09); 457 adv7180_csi_write(state, 0x2C, 0x00); 458 if (state->field == V4L2_FIELD_NONE) 459 adv7180_csi_write(state, 0x1D, 0x80); 460 adv7180_csi_write(state, 0x00, 0x00); 461 } else { 462 adv7180_csi_write(state, 0x00, 0x80); 463 } 464 } 465 466 return 0; 467} 468 469static int adv7180_s_power(struct v4l2_subdev *sd, int on) 470{ 471 struct adv7180_state *state = to_state(sd); 472 int ret; 473 474 ret = mutex_lock_interruptible(&state->mutex); 475 if (ret) 476 return ret; 477 478 ret = adv7180_set_power(state, on); 479 if (ret == 0) 480 state->powered = on; 481 482 mutex_unlock(&state->mutex); 483 return ret; 484} 485 486static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 487{ 488 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 489 struct adv7180_state *state = to_state(sd); 490 int ret = mutex_lock_interruptible(&state->mutex); 491 int val; 492 493 if (ret) 494 return ret; 495 val = ctrl->val; 496 switch (ctrl->id) { 497 case V4L2_CID_BRIGHTNESS: 498 ret = adv7180_write(state, ADV7180_REG_BRI, val); 499 break; 500 case V4L2_CID_HUE: 501 /*Hue is inverted according to HSL chart */ 502 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 503 break; 504 case V4L2_CID_CONTRAST: 505 ret = adv7180_write(state, ADV7180_REG_CON, val); 506 break; 507 case V4L2_CID_SATURATION: 508 /* 509 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 510 *Let's not confuse the user, everybody understands saturation 511 */ 512 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 513 if (ret < 0) 514 break; 515 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 516 break; 517 case V4L2_CID_ADV_FAST_SWITCH: 518 if (ctrl->val) { 519 /* ADI required write */ 520 adv7180_write(state, 0x80d9, 0x44); 521 adv7180_write(state, ADV7180_REG_FLCONTROL, 522 ADV7180_FLCONTROL_FL_ENABLE); 523 } else { 524 /* ADI required write */ 525 adv7180_write(state, 0x80d9, 0xc4); 526 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 527 } 528 break; 529 default: 530 ret = -EINVAL; 531 } 532 533 mutex_unlock(&state->mutex); 534 return ret; 535} 536 537static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 538 .s_ctrl = adv7180_s_ctrl, 539}; 540 541static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 542 .ops = &adv7180_ctrl_ops, 543 .id = V4L2_CID_ADV_FAST_SWITCH, 544 .name = "Fast Switching", 545 .type = V4L2_CTRL_TYPE_BOOLEAN, 546 .min = 0, 547 .max = 1, 548 .step = 1, 549}; 550 551static int adv7180_init_controls(struct adv7180_state *state) 552{ 553 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 554 555 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 556 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 557 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 558 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 559 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 560 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 561 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 562 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 563 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 564 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 565 V4L2_CID_HUE, ADV7180_HUE_MIN, 566 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 567 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 568 569 state->sd.ctrl_handler = &state->ctrl_hdl; 570 if (state->ctrl_hdl.error) { 571 int err = state->ctrl_hdl.error; 572 573 v4l2_ctrl_handler_free(&state->ctrl_hdl); 574 return err; 575 } 576 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 577 578 return 0; 579} 580static void adv7180_exit_controls(struct adv7180_state *state) 581{ 582 v4l2_ctrl_handler_free(&state->ctrl_hdl); 583} 584 585static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 586 struct v4l2_subdev_pad_config *cfg, 587 struct v4l2_subdev_mbus_code_enum *code) 588{ 589 if (code->index != 0) 590 return -EINVAL; 591 592 code->code = MEDIA_BUS_FMT_YUYV8_2X8; 593 594 return 0; 595} 596 597static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 598 struct v4l2_mbus_framefmt *fmt) 599{ 600 struct adv7180_state *state = to_state(sd); 601 602 fmt->code = MEDIA_BUS_FMT_YUYV8_2X8; 603 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 604 fmt->width = 720; 605 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 606 607 return 0; 608} 609 610static int adv7180_set_field_mode(struct adv7180_state *state) 611{ 612 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 613 return 0; 614 615 if (state->field == V4L2_FIELD_NONE) { 616 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 617 adv7180_csi_write(state, 0x01, 0x20); 618 adv7180_csi_write(state, 0x02, 0x28); 619 adv7180_csi_write(state, 0x03, 0x38); 620 adv7180_csi_write(state, 0x04, 0x30); 621 adv7180_csi_write(state, 0x05, 0x30); 622 adv7180_csi_write(state, 0x06, 0x80); 623 adv7180_csi_write(state, 0x07, 0x70); 624 adv7180_csi_write(state, 0x08, 0x50); 625 } 626 adv7180_vpp_write(state, 0xa3, 0x00); 627 adv7180_vpp_write(state, 0x5b, 0x00); 628 adv7180_vpp_write(state, 0x55, 0x80); 629 } else { 630 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 631 adv7180_csi_write(state, 0x01, 0x18); 632 adv7180_csi_write(state, 0x02, 0x18); 633 adv7180_csi_write(state, 0x03, 0x30); 634 adv7180_csi_write(state, 0x04, 0x20); 635 adv7180_csi_write(state, 0x05, 0x28); 636 adv7180_csi_write(state, 0x06, 0x40); 637 adv7180_csi_write(state, 0x07, 0x58); 638 adv7180_csi_write(state, 0x08, 0x30); 639 } 640 adv7180_vpp_write(state, 0xa3, 0x70); 641 adv7180_vpp_write(state, 0x5b, 0x80); 642 adv7180_vpp_write(state, 0x55, 0x00); 643 } 644 645 return 0; 646} 647 648static int adv7180_get_pad_format(struct v4l2_subdev *sd, 649 struct v4l2_subdev_pad_config *cfg, 650 struct v4l2_subdev_format *format) 651{ 652 struct adv7180_state *state = to_state(sd); 653 654 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 655 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0); 656 } else { 657 adv7180_mbus_fmt(sd, &format->format); 658 format->format.field = state->field; 659 } 660 661 return 0; 662} 663 664static int adv7180_set_pad_format(struct v4l2_subdev *sd, 665 struct v4l2_subdev_pad_config *cfg, 666 struct v4l2_subdev_format *format) 667{ 668 struct adv7180_state *state = to_state(sd); 669 struct v4l2_mbus_framefmt *framefmt; 670 671 switch (format->format.field) { 672 case V4L2_FIELD_NONE: 673 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 674 format->format.field = V4L2_FIELD_INTERLACED; 675 break; 676 default: 677 format->format.field = V4L2_FIELD_INTERLACED; 678 break; 679 } 680 681 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 682 framefmt = &format->format; 683 if (state->field != format->format.field) { 684 state->field = format->format.field; 685 adv7180_set_power(state, false); 686 adv7180_set_field_mode(state); 687 adv7180_set_power(state, true); 688 } 689 } else { 690 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0); 691 *framefmt = format->format; 692 } 693 694 return adv7180_mbus_fmt(sd, framefmt); 695} 696 697static int adv7180_g_mbus_config(struct v4l2_subdev *sd, 698 struct v4l2_mbus_config *cfg) 699{ 700 struct adv7180_state *state = to_state(sd); 701 702 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 703 cfg->type = V4L2_MBUS_CSI2; 704 cfg->flags = V4L2_MBUS_CSI2_1_LANE | 705 V4L2_MBUS_CSI2_CHANNEL_0 | 706 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 707 } else { 708 /* 709 * The ADV7180 sensor supports BT.601/656 output modes. 710 * The BT.656 is default and not yet configurable by s/w. 711 */ 712 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | 713 V4L2_MBUS_DATA_ACTIVE_HIGH; 714 cfg->type = V4L2_MBUS_BT656; 715 } 716 717 return 0; 718} 719 720static const struct v4l2_subdev_video_ops adv7180_video_ops = { 721 .s_std = adv7180_s_std, 722 .querystd = adv7180_querystd, 723 .g_input_status = adv7180_g_input_status, 724 .s_routing = adv7180_s_routing, 725 .g_mbus_config = adv7180_g_mbus_config, 726}; 727 728 729static const struct v4l2_subdev_core_ops adv7180_core_ops = { 730 .s_power = adv7180_s_power, 731}; 732 733static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 734 .enum_mbus_code = adv7180_enum_mbus_code, 735 .set_fmt = adv7180_set_pad_format, 736 .get_fmt = adv7180_get_pad_format, 737}; 738 739static const struct v4l2_subdev_ops adv7180_ops = { 740 .core = &adv7180_core_ops, 741 .video = &adv7180_video_ops, 742 .pad = &adv7180_pad_ops, 743}; 744 745static irqreturn_t adv7180_irq(int irq, void *devid) 746{ 747 struct adv7180_state *state = devid; 748 u8 isr3; 749 750 mutex_lock(&state->mutex); 751 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 752 /* clear */ 753 adv7180_write(state, ADV7180_REG_ICR3, isr3); 754 755 if (isr3 & ADV7180_IRQ3_AD_CHANGE && state->autodetect) 756 __adv7180_status(state, NULL, &state->curr_norm); 757 mutex_unlock(&state->mutex); 758 759 return IRQ_HANDLED; 760} 761 762static int adv7180_init(struct adv7180_state *state) 763{ 764 int ret; 765 766 /* ITU-R BT.656-4 compatible */ 767 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 768 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 769 if (ret < 0) 770 return ret; 771 772 /* Manually set V bit end position in NTSC mode */ 773 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 774 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 775} 776 777static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 778{ 779 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 780 (std << 4) | state->input); 781} 782 783static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 784{ 785 int ret; 786 787 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 788 if (ret < 0) 789 return ret; 790 791 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 792 ret |= input; 793 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 794} 795 796static int adv7182_init(struct adv7180_state *state) 797{ 798 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 799 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 800 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 801 802 if (state->chip_info->flags & ADV7180_FLAG_I2P) 803 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 804 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 805 806 if (state->chip_info->flags & ADV7180_FLAG_V2) { 807 /* ADI recommended writes for improved video quality */ 808 adv7180_write(state, 0x0080, 0x51); 809 adv7180_write(state, 0x0081, 0x51); 810 adv7180_write(state, 0x0082, 0x68); 811 } 812 813 /* ADI required writes */ 814 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 815 adv7180_write(state, 0x0003, 0x4e); 816 adv7180_write(state, 0x0004, 0x57); 817 adv7180_write(state, 0x001d, 0xc0); 818 } else { 819 if (state->chip_info->flags & ADV7180_FLAG_V2) 820 adv7180_write(state, 0x0004, 0x17); 821 else 822 adv7180_write(state, 0x0004, 0x07); 823 adv7180_write(state, 0x0003, 0x0c); 824 adv7180_write(state, 0x001d, 0x40); 825 } 826 827 adv7180_write(state, 0x0013, 0x00); 828 829 return 0; 830} 831 832static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 833{ 834 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); 835} 836 837enum adv7182_input_type { 838 ADV7182_INPUT_TYPE_CVBS, 839 ADV7182_INPUT_TYPE_DIFF_CVBS, 840 ADV7182_INPUT_TYPE_SVIDEO, 841 ADV7182_INPUT_TYPE_YPBPR, 842}; 843 844static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 845{ 846 switch (input) { 847 case ADV7182_INPUT_CVBS_AIN1: 848 case ADV7182_INPUT_CVBS_AIN2: 849 case ADV7182_INPUT_CVBS_AIN3: 850 case ADV7182_INPUT_CVBS_AIN4: 851 case ADV7182_INPUT_CVBS_AIN5: 852 case ADV7182_INPUT_CVBS_AIN6: 853 case ADV7182_INPUT_CVBS_AIN7: 854 case ADV7182_INPUT_CVBS_AIN8: 855 return ADV7182_INPUT_TYPE_CVBS; 856 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 857 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 858 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 859 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 860 return ADV7182_INPUT_TYPE_SVIDEO; 861 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 862 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 863 return ADV7182_INPUT_TYPE_YPBPR; 864 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 865 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 866 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 867 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 868 return ADV7182_INPUT_TYPE_DIFF_CVBS; 869 default: /* Will never happen */ 870 return 0; 871 } 872} 873 874/* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 875static unsigned int adv7182_lbias_settings[][3] = { 876 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 877 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 878 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 879 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 880}; 881 882static unsigned int adv7280_lbias_settings[][3] = { 883 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 884 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 885 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 886 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 887}; 888 889static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 890{ 891 enum adv7182_input_type input_type; 892 unsigned int *lbias; 893 unsigned int i; 894 int ret; 895 896 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 897 if (ret) 898 return ret; 899 900 /* Reset clamp circuitry - ADI recommended writes */ 901 adv7180_write(state, 0x809c, 0x00); 902 adv7180_write(state, 0x809c, 0xff); 903 904 input_type = adv7182_get_input_type(input); 905 906 switch (input_type) { 907 case ADV7182_INPUT_TYPE_CVBS: 908 case ADV7182_INPUT_TYPE_DIFF_CVBS: 909 /* ADI recommends to use the SH1 filter */ 910 adv7180_write(state, 0x0017, 0x41); 911 break; 912 default: 913 adv7180_write(state, 0x0017, 0x01); 914 break; 915 } 916 917 if (state->chip_info->flags & ADV7180_FLAG_V2) 918 lbias = adv7280_lbias_settings[input_type]; 919 else 920 lbias = adv7182_lbias_settings[input_type]; 921 922 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 923 adv7180_write(state, 0x0052 + i, lbias[i]); 924 925 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 926 /* ADI required writes to make differential CVBS work */ 927 adv7180_write(state, 0x005f, 0xa8); 928 adv7180_write(state, 0x005a, 0x90); 929 adv7180_write(state, 0x0060, 0xb0); 930 adv7180_write(state, 0x80b6, 0x08); 931 adv7180_write(state, 0x80c0, 0xa0); 932 } else { 933 adv7180_write(state, 0x005f, 0xf0); 934 adv7180_write(state, 0x005a, 0xd0); 935 adv7180_write(state, 0x0060, 0x10); 936 adv7180_write(state, 0x80b6, 0x9c); 937 adv7180_write(state, 0x80c0, 0x00); 938 } 939 940 return 0; 941} 942 943static const struct adv7180_chip_info adv7180_info = { 944 .flags = ADV7180_FLAG_RESET_POWERED, 945 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 946 * all inputs and let the card driver take care of validation 947 */ 948 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 949 BIT(ADV7180_INPUT_CVBS_AIN2) | 950 BIT(ADV7180_INPUT_CVBS_AIN3) | 951 BIT(ADV7180_INPUT_CVBS_AIN4) | 952 BIT(ADV7180_INPUT_CVBS_AIN5) | 953 BIT(ADV7180_INPUT_CVBS_AIN6) | 954 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 955 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 956 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 957 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 958 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 959 .init = adv7180_init, 960 .set_std = adv7180_set_std, 961 .select_input = adv7180_select_input, 962}; 963 964static const struct adv7180_chip_info adv7182_info = { 965 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 966 BIT(ADV7182_INPUT_CVBS_AIN2) | 967 BIT(ADV7182_INPUT_CVBS_AIN3) | 968 BIT(ADV7182_INPUT_CVBS_AIN4) | 969 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 970 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 971 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 972 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 973 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 974 .init = adv7182_init, 975 .set_std = adv7182_set_std, 976 .select_input = adv7182_select_input, 977}; 978 979static const struct adv7180_chip_info adv7280_info = { 980 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 981 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 982 BIT(ADV7182_INPUT_CVBS_AIN2) | 983 BIT(ADV7182_INPUT_CVBS_AIN3) | 984 BIT(ADV7182_INPUT_CVBS_AIN4) | 985 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 986 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 987 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 988 .init = adv7182_init, 989 .set_std = adv7182_set_std, 990 .select_input = adv7182_select_input, 991}; 992 993static const struct adv7180_chip_info adv7280_m_info = { 994 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 995 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 996 BIT(ADV7182_INPUT_CVBS_AIN2) | 997 BIT(ADV7182_INPUT_CVBS_AIN3) | 998 BIT(ADV7182_INPUT_CVBS_AIN4) | 999 BIT(ADV7182_INPUT_CVBS_AIN5) | 1000 BIT(ADV7182_INPUT_CVBS_AIN6) | 1001 BIT(ADV7182_INPUT_CVBS_AIN7) | 1002 BIT(ADV7182_INPUT_CVBS_AIN8) | 1003 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1004 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1005 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1006 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1007 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1008 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1009 .init = adv7182_init, 1010 .set_std = adv7182_set_std, 1011 .select_input = adv7182_select_input, 1012}; 1013 1014static const struct adv7180_chip_info adv7281_info = { 1015 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1016 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1017 BIT(ADV7182_INPUT_CVBS_AIN2) | 1018 BIT(ADV7182_INPUT_CVBS_AIN7) | 1019 BIT(ADV7182_INPUT_CVBS_AIN8) | 1020 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1021 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1022 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1023 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1024 .init = adv7182_init, 1025 .set_std = adv7182_set_std, 1026 .select_input = adv7182_select_input, 1027}; 1028 1029static const struct adv7180_chip_info adv7281_m_info = { 1030 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1031 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1032 BIT(ADV7182_INPUT_CVBS_AIN2) | 1033 BIT(ADV7182_INPUT_CVBS_AIN3) | 1034 BIT(ADV7182_INPUT_CVBS_AIN4) | 1035 BIT(ADV7182_INPUT_CVBS_AIN7) | 1036 BIT(ADV7182_INPUT_CVBS_AIN8) | 1037 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1038 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1039 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1040 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1041 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1042 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1043 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1044 .init = adv7182_init, 1045 .set_std = adv7182_set_std, 1046 .select_input = adv7182_select_input, 1047}; 1048 1049static const struct adv7180_chip_info adv7281_ma_info = { 1050 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1051 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1052 BIT(ADV7182_INPUT_CVBS_AIN2) | 1053 BIT(ADV7182_INPUT_CVBS_AIN3) | 1054 BIT(ADV7182_INPUT_CVBS_AIN4) | 1055 BIT(ADV7182_INPUT_CVBS_AIN5) | 1056 BIT(ADV7182_INPUT_CVBS_AIN6) | 1057 BIT(ADV7182_INPUT_CVBS_AIN7) | 1058 BIT(ADV7182_INPUT_CVBS_AIN8) | 1059 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1060 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1061 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1062 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1063 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1064 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1065 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1066 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1067 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1068 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1069 .init = adv7182_init, 1070 .set_std = adv7182_set_std, 1071 .select_input = adv7182_select_input, 1072}; 1073 1074static const struct adv7180_chip_info adv7282_info = { 1075 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1076 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1077 BIT(ADV7182_INPUT_CVBS_AIN2) | 1078 BIT(ADV7182_INPUT_CVBS_AIN7) | 1079 BIT(ADV7182_INPUT_CVBS_AIN8) | 1080 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1081 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1082 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1083 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1084 .init = adv7182_init, 1085 .set_std = adv7182_set_std, 1086 .select_input = adv7182_select_input, 1087}; 1088 1089static const struct adv7180_chip_info adv7282_m_info = { 1090 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1091 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1092 BIT(ADV7182_INPUT_CVBS_AIN2) | 1093 BIT(ADV7182_INPUT_CVBS_AIN3) | 1094 BIT(ADV7182_INPUT_CVBS_AIN4) | 1095 BIT(ADV7182_INPUT_CVBS_AIN7) | 1096 BIT(ADV7182_INPUT_CVBS_AIN8) | 1097 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1098 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1099 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1100 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1101 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1102 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1103 .init = adv7182_init, 1104 .set_std = adv7182_set_std, 1105 .select_input = adv7182_select_input, 1106}; 1107 1108static int init_device(struct adv7180_state *state) 1109{ 1110 int ret; 1111 1112 mutex_lock(&state->mutex); 1113 1114 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1115 usleep_range(2000, 10000); 1116 1117 ret = state->chip_info->init(state); 1118 if (ret) 1119 goto out_unlock; 1120 1121 ret = adv7180_program_std(state); 1122 if (ret) 1123 goto out_unlock; 1124 1125 adv7180_set_field_mode(state); 1126 1127 /* register for interrupts */ 1128 if (state->irq > 0) { 1129 /* config the Interrupt pin to be active low */ 1130 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1131 ADV7180_ICONF1_ACTIVE_LOW | 1132 ADV7180_ICONF1_PSYNC_ONLY); 1133 if (ret < 0) 1134 goto out_unlock; 1135 1136 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1137 if (ret < 0) 1138 goto out_unlock; 1139 1140 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1141 if (ret < 0) 1142 goto out_unlock; 1143 1144 /* enable AD change interrupts interrupts */ 1145 ret = adv7180_write(state, ADV7180_REG_IMR3, 1146 ADV7180_IRQ3_AD_CHANGE); 1147 if (ret < 0) 1148 goto out_unlock; 1149 1150 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1151 if (ret < 0) 1152 goto out_unlock; 1153 } 1154 1155out_unlock: 1156 mutex_unlock(&state->mutex); 1157 1158 return ret; 1159} 1160 1161static int adv7180_probe(struct i2c_client *client, 1162 const struct i2c_device_id *id) 1163{ 1164 struct adv7180_state *state; 1165 struct v4l2_subdev *sd; 1166 int ret; 1167 1168 /* Check if the adapter supports the needed features */ 1169 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1170 return -EIO; 1171 1172 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1173 client->addr, client->adapter->name); 1174 1175 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1176 if (state == NULL) 1177 return -ENOMEM; 1178 1179 state->client = client; 1180 state->field = V4L2_FIELD_INTERLACED; 1181 state->chip_info = (struct adv7180_chip_info *)id->driver_data; 1182 1183 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1184 state->csi_client = i2c_new_dummy(client->adapter, 1185 ADV7180_DEFAULT_CSI_I2C_ADDR); 1186 if (!state->csi_client) 1187 return -ENOMEM; 1188 } 1189 1190 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1191 state->vpp_client = i2c_new_dummy(client->adapter, 1192 ADV7180_DEFAULT_VPP_I2C_ADDR); 1193 if (!state->vpp_client) { 1194 ret = -ENOMEM; 1195 goto err_unregister_csi_client; 1196 } 1197 } 1198 1199 state->irq = client->irq; 1200 mutex_init(&state->mutex); 1201 state->autodetect = true; 1202 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1203 state->powered = true; 1204 else 1205 state->powered = false; 1206 state->input = 0; 1207 sd = &state->sd; 1208 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1209 sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 1210 1211 ret = adv7180_init_controls(state); 1212 if (ret) 1213 goto err_unregister_vpp_client; 1214 1215 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1216 sd->entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER; 1217 ret = media_entity_init(&sd->entity, 1, &state->pad, 0); 1218 if (ret) 1219 goto err_free_ctrl; 1220 1221 ret = init_device(state); 1222 if (ret) 1223 goto err_media_entity_cleanup; 1224 1225 if (state->irq) { 1226 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1227 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1228 KBUILD_MODNAME, state); 1229 if (ret) 1230 goto err_media_entity_cleanup; 1231 } 1232 1233 ret = v4l2_async_register_subdev(sd); 1234 if (ret) 1235 goto err_free_irq; 1236 1237 return 0; 1238 1239err_free_irq: 1240 if (state->irq > 0) 1241 free_irq(client->irq, state); 1242err_media_entity_cleanup: 1243 media_entity_cleanup(&sd->entity); 1244err_free_ctrl: 1245 adv7180_exit_controls(state); 1246err_unregister_vpp_client: 1247 if (state->chip_info->flags & ADV7180_FLAG_I2P) 1248 i2c_unregister_device(state->vpp_client); 1249err_unregister_csi_client: 1250 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 1251 i2c_unregister_device(state->csi_client); 1252 mutex_destroy(&state->mutex); 1253 return ret; 1254} 1255 1256static int adv7180_remove(struct i2c_client *client) 1257{ 1258 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1259 struct adv7180_state *state = to_state(sd); 1260 1261 v4l2_async_unregister_subdev(sd); 1262 1263 if (state->irq > 0) 1264 free_irq(client->irq, state); 1265 1266 media_entity_cleanup(&sd->entity); 1267 adv7180_exit_controls(state); 1268 1269 if (state->chip_info->flags & ADV7180_FLAG_I2P) 1270 i2c_unregister_device(state->vpp_client); 1271 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 1272 i2c_unregister_device(state->csi_client); 1273 1274 mutex_destroy(&state->mutex); 1275 1276 return 0; 1277} 1278 1279static const struct i2c_device_id adv7180_id[] = { 1280 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1281 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1282 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1283 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1284 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1285 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1286 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1287 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1288 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1289 {}, 1290}; 1291MODULE_DEVICE_TABLE(i2c, adv7180_id); 1292 1293#ifdef CONFIG_PM_SLEEP 1294static int adv7180_suspend(struct device *dev) 1295{ 1296 struct i2c_client *client = to_i2c_client(dev); 1297 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1298 struct adv7180_state *state = to_state(sd); 1299 1300 return adv7180_set_power(state, false); 1301} 1302 1303static int adv7180_resume(struct device *dev) 1304{ 1305 struct i2c_client *client = to_i2c_client(dev); 1306 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1307 struct adv7180_state *state = to_state(sd); 1308 int ret; 1309 1310 ret = init_device(state); 1311 if (ret < 0) 1312 return ret; 1313 1314 ret = adv7180_set_power(state, state->powered); 1315 if (ret) 1316 return ret; 1317 1318 return 0; 1319} 1320 1321static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1322#define ADV7180_PM_OPS (&adv7180_pm_ops) 1323 1324#else 1325#define ADV7180_PM_OPS NULL 1326#endif 1327 1328#ifdef CONFIG_OF 1329static const struct of_device_id adv7180_of_id[] = { 1330 { .compatible = "adi,adv7180", }, 1331 { }, 1332}; 1333 1334MODULE_DEVICE_TABLE(of, adv7180_of_id); 1335#endif 1336 1337static struct i2c_driver adv7180_driver = { 1338 .driver = { 1339 .name = KBUILD_MODNAME, 1340 .pm = ADV7180_PM_OPS, 1341 .of_match_table = of_match_ptr(adv7180_of_id), 1342 }, 1343 .probe = adv7180_probe, 1344 .remove = adv7180_remove, 1345 .id_table = adv7180_id, 1346}; 1347 1348module_i2c_driver(adv7180_driver); 1349 1350MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1351MODULE_AUTHOR("Mocean Laboratories"); 1352MODULE_LICENSE("GPL v2"); 1353