1/* 2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix 3 * keyboard controller 4 * 5 * Copyright (c) 2009-2011, NVIDIA Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 */ 21 22#include <linux/kernel.h> 23#include <linux/module.h> 24#include <linux/input.h> 25#include <linux/platform_device.h> 26#include <linux/delay.h> 27#include <linux/io.h> 28#include <linux/interrupt.h> 29#include <linux/of.h> 30#include <linux/of_device.h> 31#include <linux/clk.h> 32#include <linux/slab.h> 33#include <linux/input/matrix_keypad.h> 34#include <linux/reset.h> 35#include <linux/err.h> 36 37#define KBC_MAX_KPENT 8 38 39/* Maximum row/column supported by Tegra KBC yet is 16x8 */ 40#define KBC_MAX_GPIO 24 41/* Maximum keys supported by Tegra KBC yet is 16 x 8*/ 42#define KBC_MAX_KEY (16 * 8) 43 44#define KBC_MAX_DEBOUNCE_CNT 0x3ffu 45 46/* KBC row scan time and delay for beginning the row scan. */ 47#define KBC_ROW_SCAN_TIME 16 48#define KBC_ROW_SCAN_DLY 5 49 50/* KBC uses a 32KHz clock so a cycle = 1/32Khz */ 51#define KBC_CYCLE_MS 32 52 53/* KBC Registers */ 54 55/* KBC Control Register */ 56#define KBC_CONTROL_0 0x0 57#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) 58#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) 59#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) 60#define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) 61#define KBC_CONTROL_KBC_EN (1 << 0) 62 63/* KBC Interrupt Register */ 64#define KBC_INT_0 0x4 65#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) 66#define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) 67 68#define KBC_ROW_CFG0_0 0x8 69#define KBC_COL_CFG0_0 0x18 70#define KBC_TO_CNT_0 0x24 71#define KBC_INIT_DLY_0 0x28 72#define KBC_RPT_DLY_0 0x2c 73#define KBC_KP_ENT0_0 0x30 74#define KBC_KP_ENT1_0 0x34 75#define KBC_ROW0_MASK_0 0x38 76 77#define KBC_ROW_SHIFT 3 78 79enum tegra_pin_type { 80 PIN_CFG_IGNORE, 81 PIN_CFG_COL, 82 PIN_CFG_ROW, 83}; 84 85/* Tegra KBC hw support */ 86struct tegra_kbc_hw_support { 87 int max_rows; 88 int max_columns; 89}; 90 91struct tegra_kbc_pin_cfg { 92 enum tegra_pin_type type; 93 unsigned char num; 94}; 95 96struct tegra_kbc { 97 struct device *dev; 98 unsigned int debounce_cnt; 99 unsigned int repeat_cnt; 100 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; 101 const struct matrix_keymap_data *keymap_data; 102 bool wakeup; 103 void __iomem *mmio; 104 struct input_dev *idev; 105 int irq; 106 spinlock_t lock; 107 unsigned int repoll_dly; 108 unsigned long cp_dly_jiffies; 109 unsigned int cp_to_wkup_dly; 110 bool use_fn_map; 111 bool use_ghost_filter; 112 bool keypress_caused_wake; 113 unsigned short keycode[KBC_MAX_KEY * 2]; 114 unsigned short current_keys[KBC_MAX_KPENT]; 115 unsigned int num_pressed_keys; 116 u32 wakeup_key; 117 struct timer_list timer; 118 struct clk *clk; 119 struct reset_control *rst; 120 const struct tegra_kbc_hw_support *hw_support; 121 int max_keys; 122 int num_rows_and_columns; 123}; 124 125static void tegra_kbc_report_released_keys(struct input_dev *input, 126 unsigned short old_keycodes[], 127 unsigned int old_num_keys, 128 unsigned short new_keycodes[], 129 unsigned int new_num_keys) 130{ 131 unsigned int i, j; 132 133 for (i = 0; i < old_num_keys; i++) { 134 for (j = 0; j < new_num_keys; j++) 135 if (old_keycodes[i] == new_keycodes[j]) 136 break; 137 138 if (j == new_num_keys) 139 input_report_key(input, old_keycodes[i], 0); 140 } 141} 142 143static void tegra_kbc_report_pressed_keys(struct input_dev *input, 144 unsigned char scancodes[], 145 unsigned short keycodes[], 146 unsigned int num_pressed_keys) 147{ 148 unsigned int i; 149 150 for (i = 0; i < num_pressed_keys; i++) { 151 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); 152 input_report_key(input, keycodes[i], 1); 153 } 154} 155 156static void tegra_kbc_report_keys(struct tegra_kbc *kbc) 157{ 158 unsigned char scancodes[KBC_MAX_KPENT]; 159 unsigned short keycodes[KBC_MAX_KPENT]; 160 u32 val = 0; 161 unsigned int i; 162 unsigned int num_down = 0; 163 bool fn_keypress = false; 164 bool key_in_same_row = false; 165 bool key_in_same_col = false; 166 167 for (i = 0; i < KBC_MAX_KPENT; i++) { 168 if ((i % 4) == 0) 169 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); 170 171 if (val & 0x80) { 172 unsigned int col = val & 0x07; 173 unsigned int row = (val >> 3) & 0x0f; 174 unsigned char scancode = 175 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); 176 177 scancodes[num_down] = scancode; 178 keycodes[num_down] = kbc->keycode[scancode]; 179 /* If driver uses Fn map, do not report the Fn key. */ 180 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) 181 fn_keypress = true; 182 else 183 num_down++; 184 } 185 186 val >>= 8; 187 } 188 189 /* 190 * Matrix keyboard designs are prone to keyboard ghosting. 191 * Ghosting occurs if there are 3 keys such that - 192 * any 2 of the 3 keys share a row, and any 2 of them share a column. 193 * If so ignore the key presses for this iteration. 194 */ 195 if (kbc->use_ghost_filter && num_down >= 3) { 196 for (i = 0; i < num_down; i++) { 197 unsigned int j; 198 u8 curr_col = scancodes[i] & 0x07; 199 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; 200 201 /* 202 * Find 2 keys such that one key is in the same row 203 * and the other is in the same column as the i-th key. 204 */ 205 for (j = i + 1; j < num_down; j++) { 206 u8 col = scancodes[j] & 0x07; 207 u8 row = scancodes[j] >> KBC_ROW_SHIFT; 208 209 if (col == curr_col) 210 key_in_same_col = true; 211 if (row == curr_row) 212 key_in_same_row = true; 213 } 214 } 215 } 216 217 /* 218 * If the platform uses Fn keymaps, translate keys on a Fn keypress. 219 * Function keycodes are max_keys apart from the plain keycodes. 220 */ 221 if (fn_keypress) { 222 for (i = 0; i < num_down; i++) { 223 scancodes[i] += kbc->max_keys; 224 keycodes[i] = kbc->keycode[scancodes[i]]; 225 } 226 } 227 228 /* Ignore the key presses for this iteration? */ 229 if (key_in_same_col && key_in_same_row) 230 return; 231 232 tegra_kbc_report_released_keys(kbc->idev, 233 kbc->current_keys, kbc->num_pressed_keys, 234 keycodes, num_down); 235 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); 236 input_sync(kbc->idev); 237 238 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); 239 kbc->num_pressed_keys = num_down; 240} 241 242static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) 243{ 244 u32 val; 245 246 val = readl(kbc->mmio + KBC_CONTROL_0); 247 if (enable) 248 val |= KBC_CONTROL_FIFO_CNT_INT_EN; 249 else 250 val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; 251 writel(val, kbc->mmio + KBC_CONTROL_0); 252} 253 254static void tegra_kbc_keypress_timer(unsigned long data) 255{ 256 struct tegra_kbc *kbc = (struct tegra_kbc *)data; 257 unsigned long flags; 258 u32 val; 259 unsigned int i; 260 261 spin_lock_irqsave(&kbc->lock, flags); 262 263 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; 264 if (val) { 265 unsigned long dly; 266 267 tegra_kbc_report_keys(kbc); 268 269 /* 270 * If more than one keys are pressed we need not wait 271 * for the repoll delay. 272 */ 273 dly = (val == 1) ? kbc->repoll_dly : 1; 274 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); 275 } else { 276 /* Release any pressed keys and exit the polling loop */ 277 for (i = 0; i < kbc->num_pressed_keys; i++) 278 input_report_key(kbc->idev, kbc->current_keys[i], 0); 279 input_sync(kbc->idev); 280 281 kbc->num_pressed_keys = 0; 282 283 /* All keys are released so enable the keypress interrupt */ 284 tegra_kbc_set_fifo_interrupt(kbc, true); 285 } 286 287 spin_unlock_irqrestore(&kbc->lock, flags); 288} 289 290static irqreturn_t tegra_kbc_isr(int irq, void *args) 291{ 292 struct tegra_kbc *kbc = args; 293 unsigned long flags; 294 u32 val; 295 296 spin_lock_irqsave(&kbc->lock, flags); 297 298 /* 299 * Quickly bail out & reenable interrupts if the fifo threshold 300 * count interrupt wasn't the interrupt source 301 */ 302 val = readl(kbc->mmio + KBC_INT_0); 303 writel(val, kbc->mmio + KBC_INT_0); 304 305 if (val & KBC_INT_FIFO_CNT_INT_STATUS) { 306 /* 307 * Until all keys are released, defer further processing to 308 * the polling loop in tegra_kbc_keypress_timer. 309 */ 310 tegra_kbc_set_fifo_interrupt(kbc, false); 311 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); 312 } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { 313 /* We can be here only through system resume path */ 314 kbc->keypress_caused_wake = true; 315 } 316 317 spin_unlock_irqrestore(&kbc->lock, flags); 318 319 return IRQ_HANDLED; 320} 321 322static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) 323{ 324 int i; 325 unsigned int rst_val; 326 327 /* Either mask all keys or none. */ 328 rst_val = (filter && !kbc->wakeup) ? ~0 : 0; 329 330 for (i = 0; i < kbc->hw_support->max_rows; i++) 331 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); 332} 333 334static void tegra_kbc_config_pins(struct tegra_kbc *kbc) 335{ 336 int i; 337 338 for (i = 0; i < KBC_MAX_GPIO; i++) { 339 u32 r_shft = 5 * (i % 6); 340 u32 c_shft = 4 * (i % 8); 341 u32 r_mask = 0x1f << r_shft; 342 u32 c_mask = 0x0f << c_shft; 343 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; 344 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; 345 u32 row_cfg = readl(kbc->mmio + r_offs); 346 u32 col_cfg = readl(kbc->mmio + c_offs); 347 348 row_cfg &= ~r_mask; 349 col_cfg &= ~c_mask; 350 351 switch (kbc->pin_cfg[i].type) { 352 case PIN_CFG_ROW: 353 row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; 354 break; 355 356 case PIN_CFG_COL: 357 col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; 358 break; 359 360 case PIN_CFG_IGNORE: 361 break; 362 } 363 364 writel(row_cfg, kbc->mmio + r_offs); 365 writel(col_cfg, kbc->mmio + c_offs); 366 } 367} 368 369static int tegra_kbc_start(struct tegra_kbc *kbc) 370{ 371 unsigned int debounce_cnt; 372 u32 val = 0; 373 374 clk_prepare_enable(kbc->clk); 375 376 /* Reset the KBC controller to clear all previous status.*/ 377 reset_control_assert(kbc->rst); 378 udelay(100); 379 reset_control_assert(kbc->rst); 380 udelay(100); 381 382 tegra_kbc_config_pins(kbc); 383 tegra_kbc_setup_wakekeys(kbc, false); 384 385 writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); 386 387 /* Keyboard debounce count is maximum of 12 bits. */ 388 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 389 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); 390 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ 391 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ 392 val |= KBC_CONTROL_KBC_EN; /* enable */ 393 writel(val, kbc->mmio + KBC_CONTROL_0); 394 395 /* 396 * Compute the delay(ns) from interrupt mode to continuous polling 397 * mode so the timer routine is scheduled appropriately. 398 */ 399 val = readl(kbc->mmio + KBC_INIT_DLY_0); 400 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); 401 402 kbc->num_pressed_keys = 0; 403 404 /* 405 * Atomically clear out any remaining entries in the key FIFO 406 * and enable keyboard interrupts. 407 */ 408 while (1) { 409 val = readl(kbc->mmio + KBC_INT_0); 410 val >>= 4; 411 if (!val) 412 break; 413 414 val = readl(kbc->mmio + KBC_KP_ENT0_0); 415 val = readl(kbc->mmio + KBC_KP_ENT1_0); 416 } 417 writel(0x7, kbc->mmio + KBC_INT_0); 418 419 enable_irq(kbc->irq); 420 421 return 0; 422} 423 424static void tegra_kbc_stop(struct tegra_kbc *kbc) 425{ 426 unsigned long flags; 427 u32 val; 428 429 spin_lock_irqsave(&kbc->lock, flags); 430 val = readl(kbc->mmio + KBC_CONTROL_0); 431 val &= ~1; 432 writel(val, kbc->mmio + KBC_CONTROL_0); 433 spin_unlock_irqrestore(&kbc->lock, flags); 434 435 disable_irq(kbc->irq); 436 del_timer_sync(&kbc->timer); 437 438 clk_disable_unprepare(kbc->clk); 439} 440 441static int tegra_kbc_open(struct input_dev *dev) 442{ 443 struct tegra_kbc *kbc = input_get_drvdata(dev); 444 445 return tegra_kbc_start(kbc); 446} 447 448static void tegra_kbc_close(struct input_dev *dev) 449{ 450 struct tegra_kbc *kbc = input_get_drvdata(dev); 451 452 return tegra_kbc_stop(kbc); 453} 454 455static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, 456 unsigned int *num_rows) 457{ 458 int i; 459 460 *num_rows = 0; 461 462 for (i = 0; i < KBC_MAX_GPIO; i++) { 463 const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; 464 465 switch (pin_cfg->type) { 466 case PIN_CFG_ROW: 467 if (pin_cfg->num >= kbc->hw_support->max_rows) { 468 dev_err(kbc->dev, 469 "pin_cfg[%d]: invalid row number %d\n", 470 i, pin_cfg->num); 471 return false; 472 } 473 (*num_rows)++; 474 break; 475 476 case PIN_CFG_COL: 477 if (pin_cfg->num >= kbc->hw_support->max_columns) { 478 dev_err(kbc->dev, 479 "pin_cfg[%d]: invalid column number %d\n", 480 i, pin_cfg->num); 481 return false; 482 } 483 break; 484 485 case PIN_CFG_IGNORE: 486 break; 487 488 default: 489 dev_err(kbc->dev, 490 "pin_cfg[%d]: invalid entry type %d\n", 491 pin_cfg->type, pin_cfg->num); 492 return false; 493 } 494 } 495 496 return true; 497} 498 499static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) 500{ 501 struct device_node *np = kbc->dev->of_node; 502 u32 prop; 503 int i; 504 u32 num_rows = 0; 505 u32 num_cols = 0; 506 u32 cols_cfg[KBC_MAX_GPIO]; 507 u32 rows_cfg[KBC_MAX_GPIO]; 508 int proplen; 509 int ret; 510 511 if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) 512 kbc->debounce_cnt = prop; 513 514 if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) 515 kbc->repeat_cnt = prop; 516 517 if (of_find_property(np, "nvidia,needs-ghost-filter", NULL)) 518 kbc->use_ghost_filter = true; 519 520 if (of_property_read_bool(np, "wakeup-source") || 521 of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */ 522 kbc->wakeup = true; 523 524 if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { 525 dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); 526 return -ENOENT; 527 } 528 num_rows = proplen / sizeof(u32); 529 530 if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { 531 dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); 532 return -ENOENT; 533 } 534 num_cols = proplen / sizeof(u32); 535 536 if (num_rows > kbc->hw_support->max_rows) { 537 dev_err(kbc->dev, 538 "Number of rows is more than supported by hardware\n"); 539 return -EINVAL; 540 } 541 542 if (num_cols > kbc->hw_support->max_columns) { 543 dev_err(kbc->dev, 544 "Number of cols is more than supported by hardware\n"); 545 return -EINVAL; 546 } 547 548 if (!of_get_property(np, "linux,keymap", &proplen)) { 549 dev_err(kbc->dev, "property linux,keymap not found\n"); 550 return -ENOENT; 551 } 552 553 if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { 554 dev_err(kbc->dev, 555 "keypad rows/columns not porperly specified\n"); 556 return -EINVAL; 557 } 558 559 /* Set all pins as non-configured */ 560 for (i = 0; i < kbc->num_rows_and_columns; i++) 561 kbc->pin_cfg[i].type = PIN_CFG_IGNORE; 562 563 ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", 564 rows_cfg, num_rows); 565 if (ret < 0) { 566 dev_err(kbc->dev, "Rows configurations are not proper\n"); 567 return -EINVAL; 568 } 569 570 ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", 571 cols_cfg, num_cols); 572 if (ret < 0) { 573 dev_err(kbc->dev, "Cols configurations are not proper\n"); 574 return -EINVAL; 575 } 576 577 for (i = 0; i < num_rows; i++) { 578 kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; 579 kbc->pin_cfg[rows_cfg[i]].num = i; 580 } 581 582 for (i = 0; i < num_cols; i++) { 583 kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; 584 kbc->pin_cfg[cols_cfg[i]].num = i; 585 } 586 587 return 0; 588} 589 590static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = { 591 .max_rows = 16, 592 .max_columns = 8, 593}; 594 595static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = { 596 .max_rows = 11, 597 .max_columns = 8, 598}; 599 600static const struct of_device_id tegra_kbc_of_match[] = { 601 { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support}, 602 { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support}, 603 { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support}, 604 { }, 605}; 606MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); 607 608static int tegra_kbc_probe(struct platform_device *pdev) 609{ 610 struct tegra_kbc *kbc; 611 struct resource *res; 612 int err; 613 int num_rows = 0; 614 unsigned int debounce_cnt; 615 unsigned int scan_time_rows; 616 unsigned int keymap_rows; 617 const struct of_device_id *match; 618 619 match = of_match_device(tegra_kbc_of_match, &pdev->dev); 620 621 kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); 622 if (!kbc) { 623 dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); 624 return -ENOMEM; 625 } 626 627 kbc->dev = &pdev->dev; 628 kbc->hw_support = match->data; 629 kbc->max_keys = kbc->hw_support->max_rows * 630 kbc->hw_support->max_columns; 631 kbc->num_rows_and_columns = kbc->hw_support->max_rows + 632 kbc->hw_support->max_columns; 633 keymap_rows = kbc->max_keys; 634 spin_lock_init(&kbc->lock); 635 636 err = tegra_kbc_parse_dt(kbc); 637 if (err) 638 return err; 639 640 if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) 641 return -EINVAL; 642 643 kbc->irq = platform_get_irq(pdev, 0); 644 if (kbc->irq < 0) { 645 dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); 646 return -ENXIO; 647 } 648 649 kbc->idev = devm_input_allocate_device(&pdev->dev); 650 if (!kbc->idev) { 651 dev_err(&pdev->dev, "failed to allocate input device\n"); 652 return -ENOMEM; 653 } 654 655 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc); 656 657 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 658 kbc->mmio = devm_ioremap_resource(&pdev->dev, res); 659 if (IS_ERR(kbc->mmio)) 660 return PTR_ERR(kbc->mmio); 661 662 kbc->clk = devm_clk_get(&pdev->dev, NULL); 663 if (IS_ERR(kbc->clk)) { 664 dev_err(&pdev->dev, "failed to get keyboard clock\n"); 665 return PTR_ERR(kbc->clk); 666 } 667 668 kbc->rst = devm_reset_control_get(&pdev->dev, "kbc"); 669 if (IS_ERR(kbc->rst)) { 670 dev_err(&pdev->dev, "failed to get keyboard reset\n"); 671 return PTR_ERR(kbc->rst); 672 } 673 674 /* 675 * The time delay between two consecutive reads of the FIFO is 676 * the sum of the repeat time and the time taken for scanning 677 * the rows. There is an additional delay before the row scanning 678 * starts. The repoll delay is computed in milliseconds. 679 */ 680 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 681 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; 682 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; 683 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); 684 685 kbc->idev->name = pdev->name; 686 kbc->idev->id.bustype = BUS_HOST; 687 kbc->idev->dev.parent = &pdev->dev; 688 kbc->idev->open = tegra_kbc_open; 689 kbc->idev->close = tegra_kbc_close; 690 691 if (kbc->keymap_data && kbc->use_fn_map) 692 keymap_rows *= 2; 693 694 err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, 695 keymap_rows, 696 kbc->hw_support->max_columns, 697 kbc->keycode, kbc->idev); 698 if (err) { 699 dev_err(&pdev->dev, "failed to setup keymap\n"); 700 return err; 701 } 702 703 __set_bit(EV_REP, kbc->idev->evbit); 704 input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); 705 706 input_set_drvdata(kbc->idev, kbc); 707 708 err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, 709 IRQF_TRIGGER_HIGH, pdev->name, kbc); 710 if (err) { 711 dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); 712 return err; 713 } 714 715 disable_irq(kbc->irq); 716 717 err = input_register_device(kbc->idev); 718 if (err) { 719 dev_err(&pdev->dev, "failed to register input device\n"); 720 return err; 721 } 722 723 platform_set_drvdata(pdev, kbc); 724 device_init_wakeup(&pdev->dev, kbc->wakeup); 725 726 return 0; 727} 728 729#ifdef CONFIG_PM_SLEEP 730static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) 731{ 732 u32 val; 733 734 val = readl(kbc->mmio + KBC_CONTROL_0); 735 if (enable) 736 val |= KBC_CONTROL_KEYPRESS_INT_EN; 737 else 738 val &= ~KBC_CONTROL_KEYPRESS_INT_EN; 739 writel(val, kbc->mmio + KBC_CONTROL_0); 740} 741 742static int tegra_kbc_suspend(struct device *dev) 743{ 744 struct platform_device *pdev = to_platform_device(dev); 745 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 746 747 mutex_lock(&kbc->idev->mutex); 748 if (device_may_wakeup(&pdev->dev)) { 749 disable_irq(kbc->irq); 750 del_timer_sync(&kbc->timer); 751 tegra_kbc_set_fifo_interrupt(kbc, false); 752 753 /* Forcefully clear the interrupt status */ 754 writel(0x7, kbc->mmio + KBC_INT_0); 755 /* 756 * Store the previous resident time of continuous polling mode. 757 * Force the keyboard into interrupt mode. 758 */ 759 kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); 760 writel(0, kbc->mmio + KBC_TO_CNT_0); 761 762 tegra_kbc_setup_wakekeys(kbc, true); 763 msleep(30); 764 765 kbc->keypress_caused_wake = false; 766 /* Enable keypress interrupt before going into suspend. */ 767 tegra_kbc_set_keypress_interrupt(kbc, true); 768 enable_irq(kbc->irq); 769 enable_irq_wake(kbc->irq); 770 } else { 771 if (kbc->idev->users) 772 tegra_kbc_stop(kbc); 773 } 774 mutex_unlock(&kbc->idev->mutex); 775 776 return 0; 777} 778 779static int tegra_kbc_resume(struct device *dev) 780{ 781 struct platform_device *pdev = to_platform_device(dev); 782 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 783 int err = 0; 784 785 mutex_lock(&kbc->idev->mutex); 786 if (device_may_wakeup(&pdev->dev)) { 787 disable_irq_wake(kbc->irq); 788 tegra_kbc_setup_wakekeys(kbc, false); 789 /* We will use fifo interrupts for key detection. */ 790 tegra_kbc_set_keypress_interrupt(kbc, false); 791 792 /* Restore the resident time of continuous polling mode. */ 793 writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); 794 795 tegra_kbc_set_fifo_interrupt(kbc, true); 796 797 if (kbc->keypress_caused_wake && kbc->wakeup_key) { 798 /* 799 * We can't report events directly from the ISR 800 * because timekeeping is stopped when processing 801 * wakeup request and we get a nasty warning when 802 * we try to call do_gettimeofday() in evdev 803 * handler. 804 */ 805 input_report_key(kbc->idev, kbc->wakeup_key, 1); 806 input_sync(kbc->idev); 807 input_report_key(kbc->idev, kbc->wakeup_key, 0); 808 input_sync(kbc->idev); 809 } 810 } else { 811 if (kbc->idev->users) 812 err = tegra_kbc_start(kbc); 813 } 814 mutex_unlock(&kbc->idev->mutex); 815 816 return err; 817} 818#endif 819 820static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); 821 822static struct platform_driver tegra_kbc_driver = { 823 .probe = tegra_kbc_probe, 824 .driver = { 825 .name = "tegra-kbc", 826 .pm = &tegra_kbc_pm_ops, 827 .of_match_table = tegra_kbc_of_match, 828 }, 829}; 830module_platform_driver(tegra_kbc_driver); 831 832MODULE_LICENSE("GPL"); 833MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); 834MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); 835MODULE_ALIAS("platform:tegra-kbc"); 836