1/* savage_bci.c -- BCI support for Savage 2 * 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25#include <drm/drmP.h> 26#include <drm/savage_drm.h> 27#include "savage_drv.h" 28 29/* Need a long timeout for shadow status updates can take a while 30 * and so can waiting for events when the queue is full. */ 31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 33#define SAVAGE_FREELIST_DEBUG 0 34 35static int savage_do_cleanup_bci(struct drm_device *dev); 36 37static int 38savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) 39{ 40 uint32_t mask = dev_priv->status_used_mask; 41 uint32_t threshold = dev_priv->bci_threshold_hi; 42 uint32_t status; 43 int i; 44 45#if SAVAGE_BCI_DEBUG 46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) 47 DRM_ERROR("Trying to emit %d words " 48 "(more than guaranteed space in COB)\n", n); 49#endif 50 51 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 52 mb(); 53 status = dev_priv->status_ptr[0]; 54 if ((status & mask) < threshold) 55 return 0; 56 DRM_UDELAY(1); 57 } 58 59#if SAVAGE_BCI_DEBUG 60 DRM_ERROR("failed!\n"); 61 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); 62#endif 63 return -EBUSY; 64} 65 66static int 67savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) 68{ 69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 70 uint32_t status; 71 int i; 72 73 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 74 status = SAVAGE_READ(SAVAGE_STATUS_WORD0); 75 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) 76 return 0; 77 DRM_UDELAY(1); 78 } 79 80#if SAVAGE_BCI_DEBUG 81 DRM_ERROR("failed!\n"); 82 DRM_INFO(" status=0x%08x\n", status); 83#endif 84 return -EBUSY; 85} 86 87static int 88savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) 89{ 90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 91 uint32_t status; 92 int i; 93 94 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 95 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); 96 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) 97 return 0; 98 DRM_UDELAY(1); 99 } 100 101#if SAVAGE_BCI_DEBUG 102 DRM_ERROR("failed!\n"); 103 DRM_INFO(" status=0x%08x\n", status); 104#endif 105 return -EBUSY; 106} 107 108/* 109 * Waiting for events. 110 * 111 * The BIOSresets the event tag to 0 on mode changes. Therefore we 112 * never emit 0 to the event tag. If we find a 0 event tag we know the 113 * BIOS stomped on it and return success assuming that the BIOS waited 114 * for engine idle. 115 * 116 * Note: if the Xserver uses the event tag it has to follow the same 117 * rule. Otherwise there may be glitches every 2^16 events. 118 */ 119static int 120savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) 121{ 122 uint32_t status; 123 int i; 124 125 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 126 mb(); 127 status = dev_priv->status_ptr[1]; 128 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 129 (status & 0xffff) == 0) 130 return 0; 131 DRM_UDELAY(1); 132 } 133 134#if SAVAGE_BCI_DEBUG 135 DRM_ERROR("failed!\n"); 136 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 137#endif 138 139 return -EBUSY; 140} 141 142static int 143savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e) 144{ 145 uint32_t status; 146 int i; 147 148 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 149 status = SAVAGE_READ(SAVAGE_STATUS_WORD1); 150 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 151 (status & 0xffff) == 0) 152 return 0; 153 DRM_UDELAY(1); 154 } 155 156#if SAVAGE_BCI_DEBUG 157 DRM_ERROR("failed!\n"); 158 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 159#endif 160 161 return -EBUSY; 162} 163 164uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 165 unsigned int flags) 166{ 167 uint16_t count; 168 BCI_LOCALS; 169 170 if (dev_priv->status_ptr) { 171 /* coordinate with Xserver */ 172 count = dev_priv->status_ptr[1023]; 173 if (count < dev_priv->event_counter) 174 dev_priv->event_wrap++; 175 } else { 176 count = dev_priv->event_counter; 177 } 178 count = (count + 1) & 0xffff; 179 if (count == 0) { 180 count++; /* See the comment above savage_wait_event_*. */ 181 dev_priv->event_wrap++; 182 } 183 dev_priv->event_counter = count; 184 if (dev_priv->status_ptr) 185 dev_priv->status_ptr[1023] = (uint32_t) count; 186 187 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 188 unsigned int wait_cmd = BCI_CMD_WAIT; 189 if ((flags & SAVAGE_WAIT_2D)) 190 wait_cmd |= BCI_CMD_WAIT_2D; 191 if ((flags & SAVAGE_WAIT_3D)) 192 wait_cmd |= BCI_CMD_WAIT_3D; 193 BEGIN_BCI(2); 194 BCI_WRITE(wait_cmd); 195 } else { 196 BEGIN_BCI(1); 197 } 198 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count); 199 200 return count; 201} 202 203/* 204 * Freelist management 205 */ 206static int savage_freelist_init(struct drm_device * dev) 207{ 208 drm_savage_private_t *dev_priv = dev->dev_private; 209 struct drm_device_dma *dma = dev->dma; 210 struct drm_buf *buf; 211 drm_savage_buf_priv_t *entry; 212 int i; 213 DRM_DEBUG("count=%d\n", dma->buf_count); 214 215 dev_priv->head.next = &dev_priv->tail; 216 dev_priv->head.prev = NULL; 217 dev_priv->head.buf = NULL; 218 219 dev_priv->tail.next = NULL; 220 dev_priv->tail.prev = &dev_priv->head; 221 dev_priv->tail.buf = NULL; 222 223 for (i = 0; i < dma->buf_count; i++) { 224 buf = dma->buflist[i]; 225 entry = buf->dev_private; 226 227 SET_AGE(&entry->age, 0, 0); 228 entry->buf = buf; 229 230 entry->next = dev_priv->head.next; 231 entry->prev = &dev_priv->head; 232 dev_priv->head.next->prev = entry; 233 dev_priv->head.next = entry; 234 } 235 236 return 0; 237} 238 239static struct drm_buf *savage_freelist_get(struct drm_device * dev) 240{ 241 drm_savage_private_t *dev_priv = dev->dev_private; 242 drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 243 uint16_t event; 244 unsigned int wrap; 245 DRM_DEBUG("\n"); 246 247 UPDATE_EVENT_COUNTER(); 248 if (dev_priv->status_ptr) 249 event = dev_priv->status_ptr[1] & 0xffff; 250 else 251 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 252 wrap = dev_priv->event_wrap; 253 if (event > dev_priv->event_counter) 254 wrap--; /* hardware hasn't passed the last wrap yet */ 255 256 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 257 DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 258 259 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { 260 drm_savage_buf_priv_t *next = tail->next; 261 drm_savage_buf_priv_t *prev = tail->prev; 262 prev->next = next; 263 next->prev = prev; 264 tail->next = tail->prev = NULL; 265 return tail->buf; 266 } 267 268 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); 269 return NULL; 270} 271 272void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf) 273{ 274 drm_savage_private_t *dev_priv = dev->dev_private; 275 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 276 277 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); 278 279 if (entry->next != NULL || entry->prev != NULL) { 280 DRM_ERROR("entry already on freelist.\n"); 281 return; 282 } 283 284 prev = &dev_priv->head; 285 next = prev->next; 286 prev->next = entry; 287 next->prev = entry; 288 entry->prev = prev; 289 entry->next = next; 290} 291 292/* 293 * Command DMA 294 */ 295static int savage_dma_init(drm_savage_private_t * dev_priv) 296{ 297 unsigned int i; 298 299 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 300 (SAVAGE_DMA_PAGE_SIZE * 4); 301 dev_priv->dma_pages = kmalloc(sizeof(drm_savage_dma_page_t) * 302 dev_priv->nr_dma_pages, GFP_KERNEL); 303 if (dev_priv->dma_pages == NULL) 304 return -ENOMEM; 305 306 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 307 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); 308 dev_priv->dma_pages[i].used = 0; 309 dev_priv->dma_pages[i].flushed = 0; 310 } 311 SET_AGE(&dev_priv->last_dma_age, 0, 0); 312 313 dev_priv->first_dma_page = 0; 314 dev_priv->current_dma_page = 0; 315 316 return 0; 317} 318 319void savage_dma_reset(drm_savage_private_t * dev_priv) 320{ 321 uint16_t event; 322 unsigned int wrap, i; 323 event = savage_bci_emit_event(dev_priv, 0); 324 wrap = dev_priv->event_wrap; 325 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 326 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 327 dev_priv->dma_pages[i].used = 0; 328 dev_priv->dma_pages[i].flushed = 0; 329 } 330 SET_AGE(&dev_priv->last_dma_age, event, wrap); 331 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 332} 333 334void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page) 335{ 336 uint16_t event; 337 unsigned int wrap; 338 339 /* Faked DMA buffer pages don't age. */ 340 if (dev_priv->cmd_dma == &dev_priv->fake_dma) 341 return; 342 343 UPDATE_EVENT_COUNTER(); 344 if (dev_priv->status_ptr) 345 event = dev_priv->status_ptr[1] & 0xffff; 346 else 347 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 348 wrap = dev_priv->event_wrap; 349 if (event > dev_priv->event_counter) 350 wrap--; /* hardware hasn't passed the last wrap yet */ 351 352 if (dev_priv->dma_pages[page].age.wrap > wrap || 353 (dev_priv->dma_pages[page].age.wrap == wrap && 354 dev_priv->dma_pages[page].age.event > event)) { 355 if (dev_priv->wait_evnt(dev_priv, 356 dev_priv->dma_pages[page].age.event) 357 < 0) 358 DRM_ERROR("wait_evnt failed!\n"); 359 } 360} 361 362uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) 363{ 364 unsigned int cur = dev_priv->current_dma_page; 365 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 366 dev_priv->dma_pages[cur].used; 367 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / 368 SAVAGE_DMA_PAGE_SIZE; 369 uint32_t *dma_ptr; 370 unsigned int i; 371 372 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", 373 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 374 375 if (cur + nr_pages < dev_priv->nr_dma_pages) { 376 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 377 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 378 if (n < rest) 379 rest = n; 380 dev_priv->dma_pages[cur].used += rest; 381 n -= rest; 382 cur++; 383 } else { 384 dev_priv->dma_flush(dev_priv); 385 nr_pages = 386 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; 387 for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 388 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 389 dev_priv->dma_pages[i].used = 0; 390 dev_priv->dma_pages[i].flushed = 0; 391 } 392 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; 393 dev_priv->first_dma_page = cur = 0; 394 } 395 for (i = cur; nr_pages > 0; ++i, --nr_pages) { 396#if SAVAGE_DMA_DEBUG 397 if (dev_priv->dma_pages[i].used) { 398 DRM_ERROR("unflushed page %u: used=%u\n", 399 i, dev_priv->dma_pages[i].used); 400 } 401#endif 402 if (n > SAVAGE_DMA_PAGE_SIZE) 403 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; 404 else 405 dev_priv->dma_pages[i].used = n; 406 n -= SAVAGE_DMA_PAGE_SIZE; 407 } 408 dev_priv->current_dma_page = --i; 409 410 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", 411 i, dev_priv->dma_pages[i].used, n); 412 413 savage_dma_wait(dev_priv, dev_priv->current_dma_page); 414 415 return dma_ptr; 416} 417 418static void savage_dma_flush(drm_savage_private_t * dev_priv) 419{ 420 unsigned int first = dev_priv->first_dma_page; 421 unsigned int cur = dev_priv->current_dma_page; 422 uint16_t event; 423 unsigned int wrap, pad, align, len, i; 424 unsigned long phys_addr; 425 BCI_LOCALS; 426 427 if (first == cur && 428 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) 429 return; 430 431 /* pad length to multiples of 2 entries 432 * align start of next DMA block to multiles of 8 entries */ 433 pad = -dev_priv->dma_pages[cur].used & 1; 434 align = -(dev_priv->dma_pages[cur].used + pad) & 7; 435 436 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " 437 "pad=%u, align=%u\n", 438 first, cur, dev_priv->dma_pages[first].flushed, 439 dev_priv->dma_pages[cur].used, pad, align); 440 441 /* pad with noops */ 442 if (pad) { 443 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 444 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 445 dev_priv->dma_pages[cur].used += pad; 446 while (pad != 0) { 447 *dma_ptr++ = BCI_CMD_WAIT; 448 pad--; 449 } 450 } 451 452 mb(); 453 454 /* do flush ... */ 455 phys_addr = dev_priv->cmd_dma->offset + 456 (first * SAVAGE_DMA_PAGE_SIZE + 457 dev_priv->dma_pages[first].flushed) * 4; 458 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 459 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; 460 461 DRM_DEBUG("phys_addr=%lx, len=%u\n", 462 phys_addr | dev_priv->dma_type, len); 463 464 BEGIN_BCI(3); 465 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); 466 BCI_WRITE(phys_addr | dev_priv->dma_type); 467 BCI_DMA(len); 468 469 /* fix alignment of the start of the next block */ 470 dev_priv->dma_pages[cur].used += align; 471 472 /* age DMA pages */ 473 event = savage_bci_emit_event(dev_priv, 0); 474 wrap = dev_priv->event_wrap; 475 for (i = first; i < cur; ++i) { 476 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 477 dev_priv->dma_pages[i].used = 0; 478 dev_priv->dma_pages[i].flushed = 0; 479 } 480 /* age the current page only when it's full */ 481 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { 482 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); 483 dev_priv->dma_pages[cur].used = 0; 484 dev_priv->dma_pages[cur].flushed = 0; 485 /* advance to next page */ 486 cur++; 487 if (cur == dev_priv->nr_dma_pages) 488 cur = 0; 489 dev_priv->first_dma_page = dev_priv->current_dma_page = cur; 490 } else { 491 dev_priv->first_dma_page = cur; 492 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; 493 } 494 SET_AGE(&dev_priv->last_dma_age, event, wrap); 495 496 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, 497 dev_priv->dma_pages[cur].used, 498 dev_priv->dma_pages[cur].flushed); 499} 500 501static void savage_fake_dma_flush(drm_savage_private_t * dev_priv) 502{ 503 unsigned int i, j; 504 BCI_LOCALS; 505 506 if (dev_priv->first_dma_page == dev_priv->current_dma_page && 507 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) 508 return; 509 510 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", 511 dev_priv->first_dma_page, dev_priv->current_dma_page, 512 dev_priv->dma_pages[dev_priv->current_dma_page].used); 513 514 for (i = dev_priv->first_dma_page; 515 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 516 ++i) { 517 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 518 i * SAVAGE_DMA_PAGE_SIZE; 519#if SAVAGE_DMA_DEBUG 520 /* Sanity check: all pages except the last one must be full. */ 521 if (i < dev_priv->current_dma_page && 522 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { 523 DRM_ERROR("partial DMA page %u: used=%u", 524 i, dev_priv->dma_pages[i].used); 525 } 526#endif 527 BEGIN_BCI(dev_priv->dma_pages[i].used); 528 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { 529 BCI_WRITE(dma_ptr[j]); 530 } 531 dev_priv->dma_pages[i].used = 0; 532 } 533 534 /* reset to first page */ 535 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 536} 537 538int savage_driver_load(struct drm_device *dev, unsigned long chipset) 539{ 540 drm_savage_private_t *dev_priv; 541 542 dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL); 543 if (dev_priv == NULL) 544 return -ENOMEM; 545 546 dev->dev_private = (void *)dev_priv; 547 548 dev_priv->chipset = (enum savage_family)chipset; 549 550 pci_set_master(dev->pdev); 551 552 return 0; 553} 554 555 556/* 557 * Initialize mappings. On Savage4 and SavageIX the alignment 558 * and size of the aperture is not suitable for automatic MTRR setup 559 * in drm_legacy_addmap. Therefore we add them manually before the maps are 560 * initialized, and tear them down on last close. 561 */ 562int savage_driver_firstopen(struct drm_device *dev) 563{ 564 drm_savage_private_t *dev_priv = dev->dev_private; 565 unsigned long mmio_base, fb_base, fb_size, aperture_base; 566 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist 567 * in case we decide we need information on the BAR for BSD in the 568 * future. 569 */ 570 unsigned int fb_rsrc, aper_rsrc; 571 int ret = 0; 572 573 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 574 fb_rsrc = 0; 575 fb_base = pci_resource_start(dev->pdev, 0); 576 fb_size = SAVAGE_FB_SIZE_S3; 577 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 578 aper_rsrc = 0; 579 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 580 /* this should always be true */ 581 if (pci_resource_len(dev->pdev, 0) == 0x08000000) { 582 /* Don't make MMIO write-cobining! We need 3 583 * MTRRs. */ 584 dev_priv->mtrr_handles[0] = 585 arch_phys_wc_add(fb_base, 0x01000000); 586 dev_priv->mtrr_handles[1] = 587 arch_phys_wc_add(fb_base + 0x02000000, 588 0x02000000); 589 dev_priv->mtrr_handles[2] = 590 arch_phys_wc_add(fb_base + 0x04000000, 591 0x04000000); 592 } else { 593 DRM_ERROR("strange pci_resource_len %08llx\n", 594 (unsigned long long) 595 pci_resource_len(dev->pdev, 0)); 596 } 597 } else if (dev_priv->chipset != S3_SUPERSAVAGE && 598 dev_priv->chipset != S3_SAVAGE2000) { 599 mmio_base = pci_resource_start(dev->pdev, 0); 600 fb_rsrc = 1; 601 fb_base = pci_resource_start(dev->pdev, 1); 602 fb_size = SAVAGE_FB_SIZE_S4; 603 aper_rsrc = 1; 604 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 605 /* this should always be true */ 606 if (pci_resource_len(dev->pdev, 1) == 0x08000000) { 607 /* Can use one MTRR to cover both fb and 608 * aperture. */ 609 dev_priv->mtrr_handles[0] = 610 arch_phys_wc_add(fb_base, 611 0x08000000); 612 } else { 613 DRM_ERROR("strange pci_resource_len %08llx\n", 614 (unsigned long long) 615 pci_resource_len(dev->pdev, 1)); 616 } 617 } else { 618 mmio_base = pci_resource_start(dev->pdev, 0); 619 fb_rsrc = 1; 620 fb_base = pci_resource_start(dev->pdev, 1); 621 fb_size = pci_resource_len(dev->pdev, 1); 622 aper_rsrc = 2; 623 aperture_base = pci_resource_start(dev->pdev, 2); 624 /* Automatic MTRR setup will do the right thing. */ 625 } 626 627 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, 628 _DRM_REGISTERS, _DRM_READ_ONLY, 629 &dev_priv->mmio); 630 if (ret) 631 return ret; 632 633 ret = drm_legacy_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER, 634 _DRM_WRITE_COMBINING, &dev_priv->fb); 635 if (ret) 636 return ret; 637 638 ret = drm_legacy_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 639 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, 640 &dev_priv->aperture); 641 return ret; 642} 643 644/* 645 * Delete MTRRs and free device-private data. 646 */ 647void savage_driver_lastclose(struct drm_device *dev) 648{ 649 drm_savage_private_t *dev_priv = dev->dev_private; 650 int i; 651 652 for (i = 0; i < 3; ++i) { 653 arch_phys_wc_del(dev_priv->mtrr_handles[i]); 654 dev_priv->mtrr_handles[i] = 0; 655 } 656} 657 658int savage_driver_unload(struct drm_device *dev) 659{ 660 drm_savage_private_t *dev_priv = dev->dev_private; 661 662 kfree(dev_priv); 663 664 return 0; 665} 666 667static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init) 668{ 669 drm_savage_private_t *dev_priv = dev->dev_private; 670 671 if (init->fb_bpp != 16 && init->fb_bpp != 32) { 672 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); 673 return -EINVAL; 674 } 675 if (init->depth_bpp != 16 && init->depth_bpp != 32) { 676 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); 677 return -EINVAL; 678 } 679 if (init->dma_type != SAVAGE_DMA_AGP && 680 init->dma_type != SAVAGE_DMA_PCI) { 681 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); 682 return -EINVAL; 683 } 684 685 dev_priv->cob_size = init->cob_size; 686 dev_priv->bci_threshold_lo = init->bci_threshold_lo; 687 dev_priv->bci_threshold_hi = init->bci_threshold_hi; 688 dev_priv->dma_type = init->dma_type; 689 690 dev_priv->fb_bpp = init->fb_bpp; 691 dev_priv->front_offset = init->front_offset; 692 dev_priv->front_pitch = init->front_pitch; 693 dev_priv->back_offset = init->back_offset; 694 dev_priv->back_pitch = init->back_pitch; 695 dev_priv->depth_bpp = init->depth_bpp; 696 dev_priv->depth_offset = init->depth_offset; 697 dev_priv->depth_pitch = init->depth_pitch; 698 699 dev_priv->texture_offset = init->texture_offset; 700 dev_priv->texture_size = init->texture_size; 701 702 dev_priv->sarea = drm_legacy_getsarea(dev); 703 if (!dev_priv->sarea) { 704 DRM_ERROR("could not find sarea!\n"); 705 savage_do_cleanup_bci(dev); 706 return -EINVAL; 707 } 708 if (init->status_offset != 0) { 709 dev_priv->status = drm_legacy_findmap(dev, init->status_offset); 710 if (!dev_priv->status) { 711 DRM_ERROR("could not find shadow status region!\n"); 712 savage_do_cleanup_bci(dev); 713 return -EINVAL; 714 } 715 } else { 716 dev_priv->status = NULL; 717 } 718 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { 719 dev->agp_buffer_token = init->buffers_offset; 720 dev->agp_buffer_map = drm_legacy_findmap(dev, 721 init->buffers_offset); 722 if (!dev->agp_buffer_map) { 723 DRM_ERROR("could not find DMA buffer region!\n"); 724 savage_do_cleanup_bci(dev); 725 return -EINVAL; 726 } 727 drm_legacy_ioremap(dev->agp_buffer_map, dev); 728 if (!dev->agp_buffer_map->handle) { 729 DRM_ERROR("failed to ioremap DMA buffer region!\n"); 730 savage_do_cleanup_bci(dev); 731 return -ENOMEM; 732 } 733 } 734 if (init->agp_textures_offset) { 735 dev_priv->agp_textures = 736 drm_legacy_findmap(dev, init->agp_textures_offset); 737 if (!dev_priv->agp_textures) { 738 DRM_ERROR("could not find agp texture region!\n"); 739 savage_do_cleanup_bci(dev); 740 return -EINVAL; 741 } 742 } else { 743 dev_priv->agp_textures = NULL; 744 } 745 746 if (init->cmd_dma_offset) { 747 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 748 DRM_ERROR("command DMA not supported on " 749 "Savage3D/MX/IX.\n"); 750 savage_do_cleanup_bci(dev); 751 return -EINVAL; 752 } 753 if (dev->dma && dev->dma->buflist) { 754 DRM_ERROR("command and vertex DMA not supported " 755 "at the same time.\n"); 756 savage_do_cleanup_bci(dev); 757 return -EINVAL; 758 } 759 dev_priv->cmd_dma = drm_legacy_findmap(dev, init->cmd_dma_offset); 760 if (!dev_priv->cmd_dma) { 761 DRM_ERROR("could not find command DMA region!\n"); 762 savage_do_cleanup_bci(dev); 763 return -EINVAL; 764 } 765 if (dev_priv->dma_type == SAVAGE_DMA_AGP) { 766 if (dev_priv->cmd_dma->type != _DRM_AGP) { 767 DRM_ERROR("AGP command DMA region is not a " 768 "_DRM_AGP map!\n"); 769 savage_do_cleanup_bci(dev); 770 return -EINVAL; 771 } 772 drm_legacy_ioremap(dev_priv->cmd_dma, dev); 773 if (!dev_priv->cmd_dma->handle) { 774 DRM_ERROR("failed to ioremap command " 775 "DMA region!\n"); 776 savage_do_cleanup_bci(dev); 777 return -ENOMEM; 778 } 779 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { 780 DRM_ERROR("PCI command DMA region is not a " 781 "_DRM_CONSISTENT map!\n"); 782 savage_do_cleanup_bci(dev); 783 return -EINVAL; 784 } 785 } else { 786 dev_priv->cmd_dma = NULL; 787 } 788 789 dev_priv->dma_flush = savage_dma_flush; 790 if (!dev_priv->cmd_dma) { 791 DRM_DEBUG("falling back to faked command DMA.\n"); 792 dev_priv->fake_dma.offset = 0; 793 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; 794 dev_priv->fake_dma.type = _DRM_SHM; 795 dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE, 796 GFP_KERNEL); 797 if (!dev_priv->fake_dma.handle) { 798 DRM_ERROR("could not allocate faked DMA buffer!\n"); 799 savage_do_cleanup_bci(dev); 800 return -ENOMEM; 801 } 802 dev_priv->cmd_dma = &dev_priv->fake_dma; 803 dev_priv->dma_flush = savage_fake_dma_flush; 804 } 805 806 dev_priv->sarea_priv = 807 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle + 808 init->sarea_priv_offset); 809 810 /* setup bitmap descriptors */ 811 { 812 unsigned int color_tile_format; 813 unsigned int depth_tile_format; 814 unsigned int front_stride, back_stride, depth_stride; 815 if (dev_priv->chipset <= S3_SAVAGE4) { 816 color_tile_format = dev_priv->fb_bpp == 16 ? 817 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 818 depth_tile_format = dev_priv->depth_bpp == 16 ? 819 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 820 } else { 821 color_tile_format = SAVAGE_BD_TILE_DEST; 822 depth_tile_format = SAVAGE_BD_TILE_DEST; 823 } 824 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); 825 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); 826 depth_stride = 827 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); 828 829 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 830 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 831 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 832 833 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 834 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 835 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 836 837 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 838 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 839 (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 840 } 841 842 /* setup status and bci ptr */ 843 dev_priv->event_counter = 0; 844 dev_priv->event_wrap = 0; 845 dev_priv->bci_ptr = (volatile uint32_t *) 846 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); 847 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 848 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 849 } else { 850 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; 851 } 852 if (dev_priv->status != NULL) { 853 dev_priv->status_ptr = 854 (volatile uint32_t *)dev_priv->status->handle; 855 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 856 dev_priv->wait_evnt = savage_bci_wait_event_shadow; 857 dev_priv->status_ptr[1023] = dev_priv->event_counter; 858 } else { 859 dev_priv->status_ptr = NULL; 860 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 861 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; 862 } else { 863 dev_priv->wait_fifo = savage_bci_wait_fifo_s4; 864 } 865 dev_priv->wait_evnt = savage_bci_wait_event_reg; 866 } 867 868 /* cliprect functions */ 869 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) 870 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; 871 else 872 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; 873 874 if (savage_freelist_init(dev) < 0) { 875 DRM_ERROR("could not initialize freelist\n"); 876 savage_do_cleanup_bci(dev); 877 return -ENOMEM; 878 } 879 880 if (savage_dma_init(dev_priv) < 0) { 881 DRM_ERROR("could not initialize command DMA\n"); 882 savage_do_cleanup_bci(dev); 883 return -ENOMEM; 884 } 885 886 return 0; 887} 888 889static int savage_do_cleanup_bci(struct drm_device * dev) 890{ 891 drm_savage_private_t *dev_priv = dev->dev_private; 892 893 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { 894 kfree(dev_priv->fake_dma.handle); 895 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && 896 dev_priv->cmd_dma->type == _DRM_AGP && 897 dev_priv->dma_type == SAVAGE_DMA_AGP) 898 drm_legacy_ioremapfree(dev_priv->cmd_dma, dev); 899 900 if (dev_priv->dma_type == SAVAGE_DMA_AGP && 901 dev->agp_buffer_map && dev->agp_buffer_map->handle) { 902 drm_legacy_ioremapfree(dev->agp_buffer_map, dev); 903 /* make sure the next instance (which may be running 904 * in PCI mode) doesn't try to use an old 905 * agp_buffer_map. */ 906 dev->agp_buffer_map = NULL; 907 } 908 909 kfree(dev_priv->dma_pages); 910 911 return 0; 912} 913 914static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 915{ 916 drm_savage_init_t *init = data; 917 918 LOCK_TEST_WITH_RETURN(dev, file_priv); 919 920 switch (init->func) { 921 case SAVAGE_INIT_BCI: 922 return savage_do_init_bci(dev, init); 923 case SAVAGE_CLEANUP_BCI: 924 return savage_do_cleanup_bci(dev); 925 } 926 927 return -EINVAL; 928} 929 930static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) 931{ 932 drm_savage_private_t *dev_priv = dev->dev_private; 933 drm_savage_event_emit_t *event = data; 934 935 DRM_DEBUG("\n"); 936 937 LOCK_TEST_WITH_RETURN(dev, file_priv); 938 939 event->count = savage_bci_emit_event(dev_priv, event->flags); 940 event->count |= dev_priv->event_wrap << 16; 941 942 return 0; 943} 944 945static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) 946{ 947 drm_savage_private_t *dev_priv = dev->dev_private; 948 drm_savage_event_wait_t *event = data; 949 unsigned int event_e, hw_e; 950 unsigned int event_w, hw_w; 951 952 DRM_DEBUG("\n"); 953 954 UPDATE_EVENT_COUNTER(); 955 if (dev_priv->status_ptr) 956 hw_e = dev_priv->status_ptr[1] & 0xffff; 957 else 958 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 959 hw_w = dev_priv->event_wrap; 960 if (hw_e > dev_priv->event_counter) 961 hw_w--; /* hardware hasn't passed the last wrap yet */ 962 963 event_e = event->count & 0xffff; 964 event_w = event->count >> 16; 965 966 /* Don't need to wait if 967 * - event counter wrapped since the event was emitted or 968 * - the hardware has advanced up to or over the event to wait for. 969 */ 970 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) 971 return 0; 972 else 973 return dev_priv->wait_evnt(dev_priv, event_e); 974} 975 976/* 977 * DMA buffer management 978 */ 979 980static int savage_bci_get_buffers(struct drm_device *dev, 981 struct drm_file *file_priv, 982 struct drm_dma *d) 983{ 984 struct drm_buf *buf; 985 int i; 986 987 for (i = d->granted_count; i < d->request_count; i++) { 988 buf = savage_freelist_get(dev); 989 if (!buf) 990 return -EAGAIN; 991 992 buf->file_priv = file_priv; 993 994 if (copy_to_user(&d->request_indices[i], 995 &buf->idx, sizeof(buf->idx))) 996 return -EFAULT; 997 if (copy_to_user(&d->request_sizes[i], 998 &buf->total, sizeof(buf->total))) 999 return -EFAULT; 1000 1001 d->granted_count++; 1002 } 1003 return 0; 1004} 1005 1006int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1007{ 1008 struct drm_device_dma *dma = dev->dma; 1009 struct drm_dma *d = data; 1010 int ret = 0; 1011 1012 LOCK_TEST_WITH_RETURN(dev, file_priv); 1013 1014 /* Please don't send us buffers. 1015 */ 1016 if (d->send_count != 0) { 1017 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1018 DRM_CURRENTPID, d->send_count); 1019 return -EINVAL; 1020 } 1021 1022 /* We'll send you buffers. 1023 */ 1024 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1025 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1026 DRM_CURRENTPID, d->request_count, dma->buf_count); 1027 return -EINVAL; 1028 } 1029 1030 d->granted_count = 0; 1031 1032 if (d->request_count) { 1033 ret = savage_bci_get_buffers(dev, file_priv, d); 1034 } 1035 1036 return ret; 1037} 1038 1039void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) 1040{ 1041 struct drm_device_dma *dma = dev->dma; 1042 drm_savage_private_t *dev_priv = dev->dev_private; 1043 int release_idlelock = 0; 1044 int i; 1045 1046 if (!dma) 1047 return; 1048 if (!dev_priv) 1049 return; 1050 if (!dma->buflist) 1051 return; 1052 1053 if (file_priv->master && file_priv->master->lock.hw_lock) { 1054 drm_legacy_idlelock_take(&file_priv->master->lock); 1055 release_idlelock = 1; 1056 } 1057 1058 for (i = 0; i < dma->buf_count; i++) { 1059 struct drm_buf *buf = dma->buflist[i]; 1060 drm_savage_buf_priv_t *buf_priv = buf->dev_private; 1061 1062 if (buf->file_priv == file_priv && buf_priv && 1063 buf_priv->next == NULL && buf_priv->prev == NULL) { 1064 uint16_t event; 1065 DRM_DEBUG("reclaimed from client\n"); 1066 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); 1067 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); 1068 savage_freelist_put(dev, buf); 1069 } 1070 } 1071 1072 if (release_idlelock) 1073 drm_legacy_idlelock_release(&file_priv->master->lock); 1074} 1075 1076const struct drm_ioctl_desc savage_ioctls[] = { 1077 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1078 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1079 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), 1080 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), 1081}; 1082 1083int savage_max_ioctl = ARRAY_SIZE(savage_ioctls); 1084