1/*
2 * rcar_du_group.c  --  R-Car Display Unit Channels Pair
3 *
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14/*
15 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
16 * unit, timings generator, ...) and device-global resources (start/stop
17 * control, planes, ...) shared between the two CRTCs.
18 *
19 * The R8A7790 introduced a third CRTC with its own set of global resources.
20 * This would be modeled as two separate DU device instances if it wasn't for
21 * a handful or resources that are shared between the three CRTCs (mostly
22 * related to input and output routing). For this reason the R8A7790 DU must be
23 * modeled as a single device with three CRTCs, two sets of "semi-global"
24 * resources, and a few device-global resources.
25 *
26 * The rcar_du_group object is a driver specific object, without any real
27 * counterpart in the DU documentation, that models those semi-global resources.
28 */
29
30#include <linux/clk.h>
31#include <linux/io.h>
32
33#include "rcar_du_drv.h"
34#include "rcar_du_group.h"
35#include "rcar_du_regs.h"
36
37u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
38{
39	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
40}
41
42void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
43{
44	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
45}
46
47static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
48{
49	u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
50
51	/* The DEFR8 register for the first group also controls RGB output
52	 * routing to DPAD0 for DU instances that support it.
53	 */
54	if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1 &&
55	    rgrp->index == 0)
56		defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
57
58	rcar_du_group_write(rgrp, DEFR8, defr8);
59}
60
61static void rcar_du_group_setup(struct rcar_du_group *rgrp)
62{
63	/* Enable extended features */
64	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
65	rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
66	rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
67	rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
68	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
69
70	if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
71		rcar_du_group_setup_defr8(rgrp);
72
73		/* Configure input dot clock routing. We currently hardcode the
74		 * configuration to routing DOTCLKINn to DUn.
75		 */
76		rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
77				    DIDSR_LCDS_DCLKIN(2) |
78				    DIDSR_LCDS_DCLKIN(1) |
79				    DIDSR_LCDS_DCLKIN(0) |
80				    DIDSR_PDCS_CLK(2, 0) |
81				    DIDSR_PDCS_CLK(1, 0) |
82				    DIDSR_PDCS_CLK(0, 0));
83	}
84
85	/* Use DS1PR and DS2PR to configure planes priorities and connects the
86	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
87	 */
88	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
89
90	/* Apply planes to CRTCs association. */
91	mutex_lock(&rgrp->lock);
92	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
93			    rgrp->dptsr_planes);
94	mutex_unlock(&rgrp->lock);
95}
96
97/*
98 * rcar_du_group_get - Acquire a reference to the DU channels group
99 *
100 * Acquiring the first reference setups core registers. A reference must be held
101 * before accessing any hardware registers.
102 *
103 * This function must be called with the DRM mode_config lock held.
104 *
105 * Return 0 in case of success or a negative error code otherwise.
106 */
107int rcar_du_group_get(struct rcar_du_group *rgrp)
108{
109	if (rgrp->use_count)
110		goto done;
111
112	rcar_du_group_setup(rgrp);
113
114done:
115	rgrp->use_count++;
116	return 0;
117}
118
119/*
120 * rcar_du_group_put - Release a reference to the DU
121 *
122 * This function must be called with the DRM mode_config lock held.
123 */
124void rcar_du_group_put(struct rcar_du_group *rgrp)
125{
126	--rgrp->use_count;
127}
128
129static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
130{
131	rcar_du_group_write(rgrp, DSYSR,
132		(rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
133		(start ? DSYSR_DEN : DSYSR_DRES));
134}
135
136void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
137{
138	/* Many of the configuration bits are only updated when the display
139	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
140	 * of those bits could be pre-configured, but others (especially the
141	 * bits related to plane assignment to display timing controllers) need
142	 * to be modified at runtime.
143	 *
144	 * Restart the display controller if a start is requested. Sorry for the
145	 * flicker. It should be possible to move most of the "DRES-update" bits
146	 * setup to driver initialization time and minimize the number of cases
147	 * when the display controller will have to be restarted.
148	 */
149	if (start) {
150		if (rgrp->used_crtcs++ != 0)
151			__rcar_du_group_start_stop(rgrp, false);
152		__rcar_du_group_start_stop(rgrp, true);
153	} else {
154		if (--rgrp->used_crtcs == 0)
155			__rcar_du_group_start_stop(rgrp, false);
156	}
157}
158
159void rcar_du_group_restart(struct rcar_du_group *rgrp)
160{
161	__rcar_du_group_start_stop(rgrp, false);
162	__rcar_du_group_start_stop(rgrp, true);
163}
164
165static int rcar_du_set_dpad0_routing(struct rcar_du_device *rcdu)
166{
167	int ret;
168
169	if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
170		return 0;
171
172	/* RGB output routing to DPAD0 is configured in the DEFR8 register of
173	 * the first group. As this function can be called with the DU0 and DU1
174	 * CRTCs disabled, we need to enable the first group clock before
175	 * accessing the register.
176	 */
177	ret = clk_prepare_enable(rcdu->crtcs[0].clock);
178	if (ret < 0)
179		return ret;
180
181	rcar_du_group_setup_defr8(&rcdu->groups[0]);
182
183	clk_disable_unprepare(rcdu->crtcs[0].clock);
184
185	return 0;
186}
187
188int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
189{
190	struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
191	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
192
193	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
194
195	/* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
196	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
197	 * by default.
198	 */
199	if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
200		dorcr |= DORCR_PG2D_DS1;
201	else
202		dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
203
204	rcar_du_group_write(rgrp, DORCR, dorcr);
205
206	return rcar_du_set_dpad0_routing(rgrp->dev);
207}
208