1/* 2 * drivers/gpu/drm/omapdrm/omap_drv.c 3 * 4 * Copyright (C) 2011 Texas Instruments 5 * Author: Rob Clark <rob@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#include <linux/wait.h> 21 22#include <drm/drm_atomic.h> 23#include <drm/drm_atomic_helper.h> 24#include <drm/drm_crtc_helper.h> 25#include <drm/drm_fb_helper.h> 26 27#include "omap_dmm_tiler.h" 28#include "omap_drv.h" 29 30#define DRIVER_NAME MODULE_NAME 31#define DRIVER_DESC "OMAP DRM" 32#define DRIVER_DATE "20110917" 33#define DRIVER_MAJOR 1 34#define DRIVER_MINOR 0 35#define DRIVER_PATCHLEVEL 0 36 37static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; 38 39MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); 40module_param(num_crtc, int, 0600); 41 42/* 43 * mode config funcs 44 */ 45 46/* Notes about mapping DSS and DRM entities: 47 * CRTC: overlay 48 * encoder: manager.. with some extension to allow one primary CRTC 49 * and zero or more video CRTC's to be mapped to one encoder? 50 * connector: dssdev.. manager can be attached/detached from different 51 * devices 52 */ 53 54static void omap_fb_output_poll_changed(struct drm_device *dev) 55{ 56 struct omap_drm_private *priv = dev->dev_private; 57 DBG("dev=%p", dev); 58 if (priv->fbdev) 59 drm_fb_helper_hotplug_event(priv->fbdev); 60} 61 62struct omap_atomic_state_commit { 63 struct work_struct work; 64 struct drm_device *dev; 65 struct drm_atomic_state *state; 66 u32 crtcs; 67}; 68 69static void omap_atomic_wait_for_completion(struct drm_device *dev, 70 struct drm_atomic_state *old_state) 71{ 72 struct drm_crtc_state *old_crtc_state; 73 struct drm_crtc *crtc; 74 unsigned int i; 75 int ret; 76 77 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { 78 if (!crtc->state->enable) 79 continue; 80 81 ret = omap_crtc_wait_pending(crtc); 82 83 if (!ret) 84 dev_warn(dev->dev, 85 "atomic complete timeout (pipe %u)!\n", i); 86 } 87} 88 89static void omap_atomic_complete(struct omap_atomic_state_commit *commit) 90{ 91 struct drm_device *dev = commit->dev; 92 struct omap_drm_private *priv = dev->dev_private; 93 struct drm_atomic_state *old_state = commit->state; 94 95 /* Apply the atomic update. */ 96 dispc_runtime_get(); 97 98 drm_atomic_helper_commit_modeset_disables(dev, old_state); 99 drm_atomic_helper_commit_planes(dev, old_state, false); 100 drm_atomic_helper_commit_modeset_enables(dev, old_state); 101 102 omap_atomic_wait_for_completion(dev, old_state); 103 104 drm_atomic_helper_cleanup_planes(dev, old_state); 105 106 dispc_runtime_put(); 107 108 drm_atomic_state_free(old_state); 109 110 /* Complete the commit, wake up any waiter. */ 111 spin_lock(&priv->commit.lock); 112 priv->commit.pending &= ~commit->crtcs; 113 spin_unlock(&priv->commit.lock); 114 115 wake_up_all(&priv->commit.wait); 116 117 kfree(commit); 118} 119 120static void omap_atomic_work(struct work_struct *work) 121{ 122 struct omap_atomic_state_commit *commit = 123 container_of(work, struct omap_atomic_state_commit, work); 124 125 omap_atomic_complete(commit); 126} 127 128static bool omap_atomic_is_pending(struct omap_drm_private *priv, 129 struct omap_atomic_state_commit *commit) 130{ 131 bool pending; 132 133 spin_lock(&priv->commit.lock); 134 pending = priv->commit.pending & commit->crtcs; 135 spin_unlock(&priv->commit.lock); 136 137 return pending; 138} 139 140static int omap_atomic_commit(struct drm_device *dev, 141 struct drm_atomic_state *state, bool async) 142{ 143 struct omap_drm_private *priv = dev->dev_private; 144 struct omap_atomic_state_commit *commit; 145 unsigned long flags; 146 unsigned int i; 147 int ret; 148 149 ret = drm_atomic_helper_prepare_planes(dev, state); 150 if (ret) 151 return ret; 152 153 /* Allocate the commit object. */ 154 commit = kzalloc(sizeof(*commit), GFP_KERNEL); 155 if (commit == NULL) { 156 ret = -ENOMEM; 157 goto error; 158 } 159 160 INIT_WORK(&commit->work, omap_atomic_work); 161 commit->dev = dev; 162 commit->state = state; 163 164 /* Wait until all affected CRTCs have completed previous commits and 165 * mark them as pending. 166 */ 167 for (i = 0; i < dev->mode_config.num_crtc; ++i) { 168 if (state->crtcs[i]) 169 commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]); 170 } 171 172 wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit)); 173 174 spin_lock(&priv->commit.lock); 175 priv->commit.pending |= commit->crtcs; 176 spin_unlock(&priv->commit.lock); 177 178 /* Keep track of all CRTC events to unlink them in preclose(). */ 179 spin_lock_irqsave(&dev->event_lock, flags); 180 for (i = 0; i < dev->mode_config.num_crtc; ++i) { 181 struct drm_crtc_state *cstate = state->crtc_states[i]; 182 183 if (cstate && cstate->event) 184 list_add_tail(&cstate->event->base.link, 185 &priv->commit.events); 186 } 187 spin_unlock_irqrestore(&dev->event_lock, flags); 188 189 /* Swap the state, this is the point of no return. */ 190 drm_atomic_helper_swap_state(dev, state); 191 192 if (async) 193 schedule_work(&commit->work); 194 else 195 omap_atomic_complete(commit); 196 197 return 0; 198 199error: 200 drm_atomic_helper_cleanup_planes(dev, state); 201 return ret; 202} 203 204static const struct drm_mode_config_funcs omap_mode_config_funcs = { 205 .fb_create = omap_framebuffer_create, 206 .output_poll_changed = omap_fb_output_poll_changed, 207 .atomic_check = drm_atomic_helper_check, 208 .atomic_commit = omap_atomic_commit, 209}; 210 211static int get_connector_type(struct omap_dss_device *dssdev) 212{ 213 switch (dssdev->type) { 214 case OMAP_DISPLAY_TYPE_HDMI: 215 return DRM_MODE_CONNECTOR_HDMIA; 216 case OMAP_DISPLAY_TYPE_DVI: 217 return DRM_MODE_CONNECTOR_DVID; 218 default: 219 return DRM_MODE_CONNECTOR_Unknown; 220 } 221} 222 223static bool channel_used(struct drm_device *dev, enum omap_channel channel) 224{ 225 struct omap_drm_private *priv = dev->dev_private; 226 int i; 227 228 for (i = 0; i < priv->num_crtcs; i++) { 229 struct drm_crtc *crtc = priv->crtcs[i]; 230 231 if (omap_crtc_channel(crtc) == channel) 232 return true; 233 } 234 235 return false; 236} 237static void omap_disconnect_dssdevs(void) 238{ 239 struct omap_dss_device *dssdev = NULL; 240 241 for_each_dss_dev(dssdev) 242 dssdev->driver->disconnect(dssdev); 243} 244 245static int omap_connect_dssdevs(void) 246{ 247 int r; 248 struct omap_dss_device *dssdev = NULL; 249 bool no_displays = true; 250 251 for_each_dss_dev(dssdev) { 252 r = dssdev->driver->connect(dssdev); 253 if (r == -EPROBE_DEFER) { 254 omap_dss_put_device(dssdev); 255 goto cleanup; 256 } else if (r) { 257 dev_warn(dssdev->dev, "could not connect display: %s\n", 258 dssdev->name); 259 } else { 260 no_displays = false; 261 } 262 } 263 264 if (no_displays) 265 return -EPROBE_DEFER; 266 267 return 0; 268 269cleanup: 270 /* 271 * if we are deferring probe, we disconnect the devices we previously 272 * connected 273 */ 274 omap_disconnect_dssdevs(); 275 276 return r; 277} 278 279static int omap_modeset_create_crtc(struct drm_device *dev, int id, 280 enum omap_channel channel) 281{ 282 struct omap_drm_private *priv = dev->dev_private; 283 struct drm_plane *plane; 284 struct drm_crtc *crtc; 285 286 plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY); 287 if (IS_ERR(plane)) 288 return PTR_ERR(plane); 289 290 crtc = omap_crtc_init(dev, plane, channel, id); 291 292 BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); 293 priv->crtcs[id] = crtc; 294 priv->num_crtcs++; 295 296 priv->planes[id] = plane; 297 priv->num_planes++; 298 299 return 0; 300} 301 302static int omap_modeset_init_properties(struct drm_device *dev) 303{ 304 struct omap_drm_private *priv = dev->dev_private; 305 306 if (priv->has_dmm) { 307 dev->mode_config.rotation_property = 308 drm_mode_create_rotation_property(dev, 309 BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | 310 BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) | 311 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)); 312 if (!dev->mode_config.rotation_property) 313 return -ENOMEM; 314 } 315 316 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3); 317 if (!priv->zorder_prop) 318 return -ENOMEM; 319 320 return 0; 321} 322 323static int omap_modeset_init(struct drm_device *dev) 324{ 325 struct omap_drm_private *priv = dev->dev_private; 326 struct omap_dss_device *dssdev = NULL; 327 int num_ovls = dss_feat_get_num_ovls(); 328 int num_mgrs = dss_feat_get_num_mgrs(); 329 int num_crtcs; 330 int i, id = 0; 331 int ret; 332 333 drm_mode_config_init(dev); 334 335 omap_drm_irq_install(dev); 336 337 ret = omap_modeset_init_properties(dev); 338 if (ret < 0) 339 return ret; 340 341 /* 342 * We usually don't want to create a CRTC for each manager, at least 343 * not until we have a way to expose private planes to userspace. 344 * Otherwise there would not be enough video pipes left for drm planes. 345 * We use the num_crtc argument to limit the number of crtcs we create. 346 */ 347 num_crtcs = min3(num_crtc, num_mgrs, num_ovls); 348 349 dssdev = NULL; 350 351 for_each_dss_dev(dssdev) { 352 struct drm_connector *connector; 353 struct drm_encoder *encoder; 354 enum omap_channel channel; 355 struct omap_overlay_manager *mgr; 356 357 if (!omapdss_device_is_connected(dssdev)) 358 continue; 359 360 encoder = omap_encoder_init(dev, dssdev); 361 362 if (!encoder) { 363 dev_err(dev->dev, "could not create encoder: %s\n", 364 dssdev->name); 365 return -ENOMEM; 366 } 367 368 connector = omap_connector_init(dev, 369 get_connector_type(dssdev), dssdev, encoder); 370 371 if (!connector) { 372 dev_err(dev->dev, "could not create connector: %s\n", 373 dssdev->name); 374 return -ENOMEM; 375 } 376 377 BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); 378 BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); 379 380 priv->encoders[priv->num_encoders++] = encoder; 381 priv->connectors[priv->num_connectors++] = connector; 382 383 drm_mode_connector_attach_encoder(connector, encoder); 384 385 /* 386 * if we have reached the limit of the crtcs we are allowed to 387 * create, let's not try to look for a crtc for this 388 * panel/encoder and onwards, we will, of course, populate the 389 * the possible_crtcs field for all the encoders with the final 390 * set of crtcs we create 391 */ 392 if (id == num_crtcs) 393 continue; 394 395 /* 396 * get the recommended DISPC channel for this encoder. For now, 397 * we only try to get create a crtc out of the recommended, the 398 * other possible channels to which the encoder can connect are 399 * not considered. 400 */ 401 402 mgr = omapdss_find_mgr_from_display(dssdev); 403 channel = mgr->id; 404 /* 405 * if this channel hasn't already been taken by a previously 406 * allocated crtc, we create a new crtc for it 407 */ 408 if (!channel_used(dev, channel)) { 409 ret = omap_modeset_create_crtc(dev, id, channel); 410 if (ret < 0) { 411 dev_err(dev->dev, 412 "could not create CRTC (channel %u)\n", 413 channel); 414 return ret; 415 } 416 417 id++; 418 } 419 } 420 421 /* 422 * we have allocated crtcs according to the need of the panels/encoders, 423 * adding more crtcs here if needed 424 */ 425 for (; id < num_crtcs; id++) { 426 427 /* find a free manager for this crtc */ 428 for (i = 0; i < num_mgrs; i++) { 429 if (!channel_used(dev, i)) 430 break; 431 } 432 433 if (i == num_mgrs) { 434 /* this shouldn't really happen */ 435 dev_err(dev->dev, "no managers left for crtc\n"); 436 return -ENOMEM; 437 } 438 439 ret = omap_modeset_create_crtc(dev, id, i); 440 if (ret < 0) { 441 dev_err(dev->dev, 442 "could not create CRTC (channel %u)\n", i); 443 return ret; 444 } 445 } 446 447 /* 448 * Create normal planes for the remaining overlays: 449 */ 450 for (; id < num_ovls; id++) { 451 struct drm_plane *plane; 452 453 plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY); 454 if (IS_ERR(plane)) 455 return PTR_ERR(plane); 456 457 BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); 458 priv->planes[priv->num_planes++] = plane; 459 } 460 461 for (i = 0; i < priv->num_encoders; i++) { 462 struct drm_encoder *encoder = priv->encoders[i]; 463 struct omap_dss_device *dssdev = 464 omap_encoder_get_dssdev(encoder); 465 struct omap_dss_device *output; 466 467 output = omapdss_find_output_from_display(dssdev); 468 469 /* figure out which crtc's we can connect the encoder to: */ 470 encoder->possible_crtcs = 0; 471 for (id = 0; id < priv->num_crtcs; id++) { 472 struct drm_crtc *crtc = priv->crtcs[id]; 473 enum omap_channel crtc_channel; 474 475 crtc_channel = omap_crtc_channel(crtc); 476 477 if (output->dispc_channel == crtc_channel) { 478 encoder->possible_crtcs |= (1 << id); 479 break; 480 } 481 } 482 483 omap_dss_put_device(output); 484 } 485 486 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", 487 priv->num_planes, priv->num_crtcs, priv->num_encoders, 488 priv->num_connectors); 489 490 dev->mode_config.min_width = 32; 491 dev->mode_config.min_height = 32; 492 493 /* note: eventually will need some cpu_is_omapXYZ() type stuff here 494 * to fill in these limits properly on different OMAP generations.. 495 */ 496 dev->mode_config.max_width = 2048; 497 dev->mode_config.max_height = 2048; 498 499 dev->mode_config.funcs = &omap_mode_config_funcs; 500 501 drm_mode_config_reset(dev); 502 503 return 0; 504} 505 506static void omap_modeset_free(struct drm_device *dev) 507{ 508 drm_mode_config_cleanup(dev); 509} 510 511/* 512 * drm ioctl funcs 513 */ 514 515 516static int ioctl_get_param(struct drm_device *dev, void *data, 517 struct drm_file *file_priv) 518{ 519 struct omap_drm_private *priv = dev->dev_private; 520 struct drm_omap_param *args = data; 521 522 DBG("%p: param=%llu", dev, args->param); 523 524 switch (args->param) { 525 case OMAP_PARAM_CHIPSET_ID: 526 args->value = priv->omaprev; 527 break; 528 default: 529 DBG("unknown parameter %lld", args->param); 530 return -EINVAL; 531 } 532 533 return 0; 534} 535 536static int ioctl_set_param(struct drm_device *dev, void *data, 537 struct drm_file *file_priv) 538{ 539 struct drm_omap_param *args = data; 540 541 switch (args->param) { 542 default: 543 DBG("unknown parameter %lld", args->param); 544 return -EINVAL; 545 } 546 547 return 0; 548} 549 550static int ioctl_gem_new(struct drm_device *dev, void *data, 551 struct drm_file *file_priv) 552{ 553 struct drm_omap_gem_new *args = data; 554 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, 555 args->size.bytes, args->flags); 556 return omap_gem_new_handle(dev, file_priv, args->size, 557 args->flags, &args->handle); 558} 559 560static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 561 struct drm_file *file_priv) 562{ 563 struct drm_omap_gem_cpu_prep *args = data; 564 struct drm_gem_object *obj; 565 int ret; 566 567 VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); 568 569 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 570 if (!obj) 571 return -ENOENT; 572 573 ret = omap_gem_op_sync(obj, args->op); 574 575 if (!ret) 576 ret = omap_gem_op_start(obj, args->op); 577 578 drm_gem_object_unreference_unlocked(obj); 579 580 return ret; 581} 582 583static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 584 struct drm_file *file_priv) 585{ 586 struct drm_omap_gem_cpu_fini *args = data; 587 struct drm_gem_object *obj; 588 int ret; 589 590 VERB("%p:%p: handle=%d", dev, file_priv, args->handle); 591 592 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 593 if (!obj) 594 return -ENOENT; 595 596 /* XXX flushy, flushy */ 597 ret = 0; 598 599 if (!ret) 600 ret = omap_gem_op_finish(obj, args->op); 601 602 drm_gem_object_unreference_unlocked(obj); 603 604 return ret; 605} 606 607static int ioctl_gem_info(struct drm_device *dev, void *data, 608 struct drm_file *file_priv) 609{ 610 struct drm_omap_gem_info *args = data; 611 struct drm_gem_object *obj; 612 int ret = 0; 613 614 VERB("%p:%p: handle=%d", dev, file_priv, args->handle); 615 616 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 617 if (!obj) 618 return -ENOENT; 619 620 args->size = omap_gem_mmap_size(obj); 621 args->offset = omap_gem_mmap_offset(obj); 622 623 drm_gem_object_unreference_unlocked(obj); 624 625 return ret; 626} 627 628static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { 629 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH), 630 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 631 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH), 632 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH), 633 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH), 634 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH), 635}; 636 637/* 638 * drm driver funcs 639 */ 640 641/** 642 * load - setup chip and create an initial config 643 * @dev: DRM device 644 * @flags: startup flags 645 * 646 * The driver load routine has to do several things: 647 * - initialize the memory manager 648 * - allocate initial config memory 649 * - setup the DRM framebuffer with the allocated memory 650 */ 651static int dev_load(struct drm_device *dev, unsigned long flags) 652{ 653 struct omap_drm_platform_data *pdata = dev->dev->platform_data; 654 struct omap_drm_private *priv; 655 unsigned int i; 656 int ret; 657 658 DBG("load: dev=%p", dev); 659 660 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 661 if (!priv) 662 return -ENOMEM; 663 664 priv->omaprev = pdata->omaprev; 665 666 dev->dev_private = priv; 667 668 priv->wq = alloc_ordered_workqueue("omapdrm", 0); 669 init_waitqueue_head(&priv->commit.wait); 670 spin_lock_init(&priv->commit.lock); 671 INIT_LIST_HEAD(&priv->commit.events); 672 673 spin_lock_init(&priv->list_lock); 674 INIT_LIST_HEAD(&priv->obj_list); 675 676 omap_gem_init(dev); 677 678 ret = omap_modeset_init(dev); 679 if (ret) { 680 dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret); 681 dev->dev_private = NULL; 682 kfree(priv); 683 return ret; 684 } 685 686 /* Initialize vblank handling, start with all CRTCs disabled. */ 687 ret = drm_vblank_init(dev, priv->num_crtcs); 688 if (ret) 689 dev_warn(dev->dev, "could not init vblank\n"); 690 691 for (i = 0; i < priv->num_crtcs; i++) 692 drm_crtc_vblank_off(priv->crtcs[i]); 693 694 priv->fbdev = omap_fbdev_init(dev); 695 if (!priv->fbdev) { 696 dev_warn(dev->dev, "omap_fbdev_init failed\n"); 697 /* well, limp along without an fbdev.. maybe X11 will work? */ 698 } 699 700 /* store off drm_device for use in pm ops */ 701 dev_set_drvdata(dev->dev, dev); 702 703 drm_kms_helper_poll_init(dev); 704 705 return 0; 706} 707 708static int dev_unload(struct drm_device *dev) 709{ 710 struct omap_drm_private *priv = dev->dev_private; 711 712 DBG("unload: dev=%p", dev); 713 714 drm_kms_helper_poll_fini(dev); 715 716 if (priv->fbdev) 717 omap_fbdev_free(dev); 718 719 omap_modeset_free(dev); 720 omap_gem_deinit(dev); 721 722 destroy_workqueue(priv->wq); 723 724 drm_vblank_cleanup(dev); 725 omap_drm_irq_uninstall(dev); 726 727 kfree(dev->dev_private); 728 dev->dev_private = NULL; 729 730 dev_set_drvdata(dev->dev, NULL); 731 732 return 0; 733} 734 735static int dev_open(struct drm_device *dev, struct drm_file *file) 736{ 737 file->driver_priv = NULL; 738 739 DBG("open: dev=%p, file=%p", dev, file); 740 741 return 0; 742} 743 744/** 745 * lastclose - clean up after all DRM clients have exited 746 * @dev: DRM device 747 * 748 * Take care of cleaning up after all DRM clients have exited. In the 749 * mode setting case, we want to restore the kernel's initial mode (just 750 * in case the last client left us in a bad state). 751 */ 752static void dev_lastclose(struct drm_device *dev) 753{ 754 int i; 755 756 /* we don't support vga_switcheroo.. so just make sure the fbdev 757 * mode is active 758 */ 759 struct omap_drm_private *priv = dev->dev_private; 760 int ret; 761 762 DBG("lastclose: dev=%p", dev); 763 764 if (dev->mode_config.rotation_property) { 765 /* need to restore default rotation state.. not sure 766 * if there is a cleaner way to restore properties to 767 * default state? Maybe a flag that properties should 768 * automatically be restored to default state on 769 * lastclose? 770 */ 771 for (i = 0; i < priv->num_crtcs; i++) { 772 drm_object_property_set_value(&priv->crtcs[i]->base, 773 dev->mode_config.rotation_property, 0); 774 } 775 776 for (i = 0; i < priv->num_planes; i++) { 777 drm_object_property_set_value(&priv->planes[i]->base, 778 dev->mode_config.rotation_property, 0); 779 } 780 } 781 782 if (priv->fbdev) { 783 ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); 784 if (ret) 785 DBG("failed to restore crtc mode"); 786 } 787} 788 789static void dev_preclose(struct drm_device *dev, struct drm_file *file) 790{ 791 struct omap_drm_private *priv = dev->dev_private; 792 struct drm_pending_event *event; 793 unsigned long flags; 794 795 DBG("preclose: dev=%p", dev); 796 797 /* 798 * Unlink all pending CRTC events to make sure they won't be queued up 799 * by a pending asynchronous commit. 800 */ 801 spin_lock_irqsave(&dev->event_lock, flags); 802 list_for_each_entry(event, &priv->commit.events, link) { 803 if (event->file_priv == file) { 804 file->event_space += event->event->length; 805 event->file_priv = NULL; 806 } 807 } 808 spin_unlock_irqrestore(&dev->event_lock, flags); 809} 810 811static void dev_postclose(struct drm_device *dev, struct drm_file *file) 812{ 813 DBG("postclose: dev=%p, file=%p", dev, file); 814} 815 816static const struct vm_operations_struct omap_gem_vm_ops = { 817 .fault = omap_gem_fault, 818 .open = drm_gem_vm_open, 819 .close = drm_gem_vm_close, 820}; 821 822static const struct file_operations omapdriver_fops = { 823 .owner = THIS_MODULE, 824 .open = drm_open, 825 .unlocked_ioctl = drm_ioctl, 826 .release = drm_release, 827 .mmap = omap_gem_mmap, 828 .poll = drm_poll, 829 .read = drm_read, 830 .llseek = noop_llseek, 831}; 832 833static struct drm_driver omap_drm_driver = { 834 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, 835 .load = dev_load, 836 .unload = dev_unload, 837 .open = dev_open, 838 .lastclose = dev_lastclose, 839 .preclose = dev_preclose, 840 .postclose = dev_postclose, 841 .set_busid = drm_platform_set_busid, 842 .get_vblank_counter = drm_vblank_no_hw_counter, 843 .enable_vblank = omap_irq_enable_vblank, 844 .disable_vblank = omap_irq_disable_vblank, 845#ifdef CONFIG_DEBUG_FS 846 .debugfs_init = omap_debugfs_init, 847 .debugfs_cleanup = omap_debugfs_cleanup, 848#endif 849 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 850 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 851 .gem_prime_export = omap_gem_prime_export, 852 .gem_prime_import = omap_gem_prime_import, 853 .gem_free_object = omap_gem_free_object, 854 .gem_vm_ops = &omap_gem_vm_ops, 855 .dumb_create = omap_gem_dumb_create, 856 .dumb_map_offset = omap_gem_dumb_map_offset, 857 .dumb_destroy = drm_gem_dumb_destroy, 858 .ioctls = ioctls, 859 .num_ioctls = DRM_OMAP_NUM_IOCTLS, 860 .fops = &omapdriver_fops, 861 .name = DRIVER_NAME, 862 .desc = DRIVER_DESC, 863 .date = DRIVER_DATE, 864 .major = DRIVER_MAJOR, 865 .minor = DRIVER_MINOR, 866 .patchlevel = DRIVER_PATCHLEVEL, 867}; 868 869static int pdev_probe(struct platform_device *device) 870{ 871 int r; 872 873 if (omapdss_is_initialized() == false) 874 return -EPROBE_DEFER; 875 876 omap_crtc_pre_init(); 877 878 r = omap_connect_dssdevs(); 879 if (r) { 880 omap_crtc_pre_uninit(); 881 return r; 882 } 883 884 DBG("%s", device->name); 885 return drm_platform_init(&omap_drm_driver, device); 886} 887 888static int pdev_remove(struct platform_device *device) 889{ 890 DBG(""); 891 892 drm_put_dev(platform_get_drvdata(device)); 893 894 omap_disconnect_dssdevs(); 895 omap_crtc_pre_uninit(); 896 897 return 0; 898} 899 900#ifdef CONFIG_PM_SLEEP 901static int omap_drm_suspend(struct device *dev) 902{ 903 struct drm_device *drm_dev = dev_get_drvdata(dev); 904 905 drm_kms_helper_poll_disable(drm_dev); 906 907 return 0; 908} 909 910static int omap_drm_resume(struct device *dev) 911{ 912 struct drm_device *drm_dev = dev_get_drvdata(dev); 913 914 drm_kms_helper_poll_enable(drm_dev); 915 916 return omap_gem_resume(dev); 917} 918#endif 919 920static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); 921 922static struct platform_driver pdev = { 923 .driver = { 924 .name = DRIVER_NAME, 925 .pm = &omapdrm_pm_ops, 926 }, 927 .probe = pdev_probe, 928 .remove = pdev_remove, 929}; 930 931static int __init omap_drm_init(void) 932{ 933 int r; 934 935 DBG("init"); 936 937 r = platform_driver_register(&omap_dmm_driver); 938 if (r) { 939 pr_err("DMM driver registration failed\n"); 940 return r; 941 } 942 943 r = platform_driver_register(&pdev); 944 if (r) { 945 pr_err("omapdrm driver registration failed\n"); 946 platform_driver_unregister(&omap_dmm_driver); 947 return r; 948 } 949 950 return 0; 951} 952 953static void __exit omap_drm_fini(void) 954{ 955 DBG("fini"); 956 957 platform_driver_unregister(&pdev); 958 959 platform_driver_unregister(&omap_dmm_driver); 960} 961 962/* need late_initcall() so we load after dss_driver's are loaded */ 963late_initcall(omap_drm_init); 964module_exit(omap_drm_fini); 965 966MODULE_AUTHOR("Rob Clark <rob@ti.com>"); 967MODULE_DESCRIPTION("OMAP DRM Display Driver"); 968MODULE_ALIAS("platform:" DRIVER_NAME); 969MODULE_LICENSE("GPL v2"); 970