1/* 2 * SuperH Timer Support - MTU2 3 * 4 * Copyright (C) 2009 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/clk.h> 17#include <linux/clockchips.h> 18#include <linux/delay.h> 19#include <linux/err.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/io.h> 23#include <linux/ioport.h> 24#include <linux/irq.h> 25#include <linux/module.h> 26#include <linux/of.h> 27#include <linux/platform_device.h> 28#include <linux/pm_domain.h> 29#include <linux/pm_runtime.h> 30#include <linux/sh_timer.h> 31#include <linux/slab.h> 32#include <linux/spinlock.h> 33 34struct sh_mtu2_device; 35 36struct sh_mtu2_channel { 37 struct sh_mtu2_device *mtu; 38 unsigned int index; 39 40 void __iomem *base; 41 42 struct clock_event_device ced; 43}; 44 45struct sh_mtu2_device { 46 struct platform_device *pdev; 47 48 void __iomem *mapbase; 49 struct clk *clk; 50 51 raw_spinlock_t lock; /* Protect the shared registers */ 52 53 struct sh_mtu2_channel *channels; 54 unsigned int num_channels; 55 56 bool has_clockevent; 57}; 58 59#define TSTR -1 /* shared register */ 60#define TCR 0 /* channel register */ 61#define TMDR 1 /* channel register */ 62#define TIOR 2 /* channel register */ 63#define TIER 3 /* channel register */ 64#define TSR 4 /* channel register */ 65#define TCNT 5 /* channel register */ 66#define TGR 6 /* channel register */ 67 68#define TCR_CCLR_NONE (0 << 5) 69#define TCR_CCLR_TGRA (1 << 5) 70#define TCR_CCLR_TGRB (2 << 5) 71#define TCR_CCLR_SYNC (3 << 5) 72#define TCR_CCLR_TGRC (5 << 5) 73#define TCR_CCLR_TGRD (6 << 5) 74#define TCR_CCLR_MASK (7 << 5) 75#define TCR_CKEG_RISING (0 << 3) 76#define TCR_CKEG_FALLING (1 << 3) 77#define TCR_CKEG_BOTH (2 << 3) 78#define TCR_CKEG_MASK (3 << 3) 79/* Values 4 to 7 are channel-dependent */ 80#define TCR_TPSC_P1 (0 << 0) 81#define TCR_TPSC_P4 (1 << 0) 82#define TCR_TPSC_P16 (2 << 0) 83#define TCR_TPSC_P64 (3 << 0) 84#define TCR_TPSC_CH0_TCLKA (4 << 0) 85#define TCR_TPSC_CH0_TCLKB (5 << 0) 86#define TCR_TPSC_CH0_TCLKC (6 << 0) 87#define TCR_TPSC_CH0_TCLKD (7 << 0) 88#define TCR_TPSC_CH1_TCLKA (4 << 0) 89#define TCR_TPSC_CH1_TCLKB (5 << 0) 90#define TCR_TPSC_CH1_P256 (6 << 0) 91#define TCR_TPSC_CH1_TCNT2 (7 << 0) 92#define TCR_TPSC_CH2_TCLKA (4 << 0) 93#define TCR_TPSC_CH2_TCLKB (5 << 0) 94#define TCR_TPSC_CH2_TCLKC (6 << 0) 95#define TCR_TPSC_CH2_P1024 (7 << 0) 96#define TCR_TPSC_CH34_P256 (4 << 0) 97#define TCR_TPSC_CH34_P1024 (5 << 0) 98#define TCR_TPSC_CH34_TCLKA (6 << 0) 99#define TCR_TPSC_CH34_TCLKB (7 << 0) 100#define TCR_TPSC_MASK (7 << 0) 101 102#define TMDR_BFE (1 << 6) 103#define TMDR_BFB (1 << 5) 104#define TMDR_BFA (1 << 4) 105#define TMDR_MD_NORMAL (0 << 0) 106#define TMDR_MD_PWM_1 (2 << 0) 107#define TMDR_MD_PWM_2 (3 << 0) 108#define TMDR_MD_PHASE_1 (4 << 0) 109#define TMDR_MD_PHASE_2 (5 << 0) 110#define TMDR_MD_PHASE_3 (6 << 0) 111#define TMDR_MD_PHASE_4 (7 << 0) 112#define TMDR_MD_PWM_SYNC (8 << 0) 113#define TMDR_MD_PWM_COMP_CREST (13 << 0) 114#define TMDR_MD_PWM_COMP_TROUGH (14 << 0) 115#define TMDR_MD_PWM_COMP_BOTH (15 << 0) 116#define TMDR_MD_MASK (15 << 0) 117 118#define TIOC_IOCH(n) ((n) << 4) 119#define TIOC_IOCL(n) ((n) << 0) 120#define TIOR_OC_RETAIN (0 << 0) 121#define TIOR_OC_0_CLEAR (1 << 0) 122#define TIOR_OC_0_SET (2 << 0) 123#define TIOR_OC_0_TOGGLE (3 << 0) 124#define TIOR_OC_1_CLEAR (5 << 0) 125#define TIOR_OC_1_SET (6 << 0) 126#define TIOR_OC_1_TOGGLE (7 << 0) 127#define TIOR_IC_RISING (8 << 0) 128#define TIOR_IC_FALLING (9 << 0) 129#define TIOR_IC_BOTH (10 << 0) 130#define TIOR_IC_TCNT (12 << 0) 131#define TIOR_MASK (15 << 0) 132 133#define TIER_TTGE (1 << 7) 134#define TIER_TTGE2 (1 << 6) 135#define TIER_TCIEU (1 << 5) 136#define TIER_TCIEV (1 << 4) 137#define TIER_TGIED (1 << 3) 138#define TIER_TGIEC (1 << 2) 139#define TIER_TGIEB (1 << 1) 140#define TIER_TGIEA (1 << 0) 141 142#define TSR_TCFD (1 << 7) 143#define TSR_TCFU (1 << 5) 144#define TSR_TCFV (1 << 4) 145#define TSR_TGFD (1 << 3) 146#define TSR_TGFC (1 << 2) 147#define TSR_TGFB (1 << 1) 148#define TSR_TGFA (1 << 0) 149 150static unsigned long mtu2_reg_offs[] = { 151 [TCR] = 0, 152 [TMDR] = 1, 153 [TIOR] = 2, 154 [TIER] = 4, 155 [TSR] = 5, 156 [TCNT] = 6, 157 [TGR] = 8, 158}; 159 160static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) 161{ 162 unsigned long offs; 163 164 if (reg_nr == TSTR) 165 return ioread8(ch->mtu->mapbase + 0x280); 166 167 offs = mtu2_reg_offs[reg_nr]; 168 169 if ((reg_nr == TCNT) || (reg_nr == TGR)) 170 return ioread16(ch->base + offs); 171 else 172 return ioread8(ch->base + offs); 173} 174 175static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, 176 unsigned long value) 177{ 178 unsigned long offs; 179 180 if (reg_nr == TSTR) 181 return iowrite8(value, ch->mtu->mapbase + 0x280); 182 183 offs = mtu2_reg_offs[reg_nr]; 184 185 if ((reg_nr == TCNT) || (reg_nr == TGR)) 186 iowrite16(value, ch->base + offs); 187 else 188 iowrite8(value, ch->base + offs); 189} 190 191static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) 192{ 193 unsigned long flags, value; 194 195 /* start stop register shared by multiple timer channels */ 196 raw_spin_lock_irqsave(&ch->mtu->lock, flags); 197 value = sh_mtu2_read(ch, TSTR); 198 199 if (start) 200 value |= 1 << ch->index; 201 else 202 value &= ~(1 << ch->index); 203 204 sh_mtu2_write(ch, TSTR, value); 205 raw_spin_unlock_irqrestore(&ch->mtu->lock, flags); 206} 207 208static int sh_mtu2_enable(struct sh_mtu2_channel *ch) 209{ 210 unsigned long periodic; 211 unsigned long rate; 212 int ret; 213 214 pm_runtime_get_sync(&ch->mtu->pdev->dev); 215 dev_pm_syscore_device(&ch->mtu->pdev->dev, true); 216 217 /* enable clock */ 218 ret = clk_enable(ch->mtu->clk); 219 if (ret) { 220 dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n", 221 ch->index); 222 return ret; 223 } 224 225 /* make sure channel is disabled */ 226 sh_mtu2_start_stop_ch(ch, 0); 227 228 rate = clk_get_rate(ch->mtu->clk) / 64; 229 periodic = (rate + HZ/2) / HZ; 230 231 /* 232 * "Periodic Counter Operation" 233 * Clear on TGRA compare match, divide clock by 64. 234 */ 235 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64); 236 sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) | 237 TIOC_IOCL(TIOR_OC_0_CLEAR)); 238 sh_mtu2_write(ch, TGR, periodic); 239 sh_mtu2_write(ch, TCNT, 0); 240 sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL); 241 sh_mtu2_write(ch, TIER, TIER_TGIEA); 242 243 /* enable channel */ 244 sh_mtu2_start_stop_ch(ch, 1); 245 246 return 0; 247} 248 249static void sh_mtu2_disable(struct sh_mtu2_channel *ch) 250{ 251 /* disable channel */ 252 sh_mtu2_start_stop_ch(ch, 0); 253 254 /* stop clock */ 255 clk_disable(ch->mtu->clk); 256 257 dev_pm_syscore_device(&ch->mtu->pdev->dev, false); 258 pm_runtime_put(&ch->mtu->pdev->dev); 259} 260 261static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) 262{ 263 struct sh_mtu2_channel *ch = dev_id; 264 265 /* acknowledge interrupt */ 266 sh_mtu2_read(ch, TSR); 267 sh_mtu2_write(ch, TSR, ~TSR_TGFA); 268 269 /* notify clockevent layer */ 270 ch->ced.event_handler(&ch->ced); 271 return IRQ_HANDLED; 272} 273 274static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) 275{ 276 return container_of(ced, struct sh_mtu2_channel, ced); 277} 278 279static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced) 280{ 281 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); 282 283 if (clockevent_state_periodic(ced)) 284 sh_mtu2_disable(ch); 285 286 return 0; 287} 288 289static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced) 290{ 291 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); 292 293 if (clockevent_state_periodic(ced)) 294 sh_mtu2_disable(ch); 295 296 dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n", 297 ch->index); 298 sh_mtu2_enable(ch); 299 return 0; 300} 301 302static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) 303{ 304 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); 305} 306 307static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) 308{ 309 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); 310} 311 312static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, 313 const char *name) 314{ 315 struct clock_event_device *ced = &ch->ced; 316 317 ced->name = name; 318 ced->features = CLOCK_EVT_FEAT_PERIODIC; 319 ced->rating = 200; 320 ced->cpumask = cpu_possible_mask; 321 ced->set_state_shutdown = sh_mtu2_clock_event_shutdown; 322 ced->set_state_periodic = sh_mtu2_clock_event_set_periodic; 323 ced->suspend = sh_mtu2_clock_event_suspend; 324 ced->resume = sh_mtu2_clock_event_resume; 325 326 dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n", 327 ch->index); 328 clockevents_register_device(ced); 329} 330 331static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name) 332{ 333 ch->mtu->has_clockevent = true; 334 sh_mtu2_register_clockevent(ch, name); 335 336 return 0; 337} 338 339static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index, 340 struct sh_mtu2_device *mtu) 341{ 342 static const unsigned int channel_offsets[] = { 343 0x300, 0x380, 0x000, 344 }; 345 char name[6]; 346 int irq; 347 int ret; 348 349 ch->mtu = mtu; 350 351 sprintf(name, "tgi%ua", index); 352 irq = platform_get_irq_byname(mtu->pdev, name); 353 if (irq < 0) { 354 /* Skip channels with no declared interrupt. */ 355 return 0; 356 } 357 358 ret = request_irq(irq, sh_mtu2_interrupt, 359 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, 360 dev_name(&ch->mtu->pdev->dev), ch); 361 if (ret) { 362 dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n", 363 index, irq); 364 return ret; 365 } 366 367 ch->base = mtu->mapbase + channel_offsets[index]; 368 ch->index = index; 369 370 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev)); 371} 372 373static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu) 374{ 375 struct resource *res; 376 377 res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0); 378 if (!res) { 379 dev_err(&mtu->pdev->dev, "failed to get I/O memory\n"); 380 return -ENXIO; 381 } 382 383 mtu->mapbase = ioremap_nocache(res->start, resource_size(res)); 384 if (mtu->mapbase == NULL) 385 return -ENXIO; 386 387 return 0; 388} 389 390static int sh_mtu2_setup(struct sh_mtu2_device *mtu, 391 struct platform_device *pdev) 392{ 393 unsigned int i; 394 int ret; 395 396 mtu->pdev = pdev; 397 398 raw_spin_lock_init(&mtu->lock); 399 400 /* Get hold of clock. */ 401 mtu->clk = clk_get(&mtu->pdev->dev, "fck"); 402 if (IS_ERR(mtu->clk)) { 403 dev_err(&mtu->pdev->dev, "cannot get clock\n"); 404 return PTR_ERR(mtu->clk); 405 } 406 407 ret = clk_prepare(mtu->clk); 408 if (ret < 0) 409 goto err_clk_put; 410 411 /* Map the memory resource. */ 412 ret = sh_mtu2_map_memory(mtu); 413 if (ret < 0) { 414 dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); 415 goto err_clk_unprepare; 416 } 417 418 /* Allocate and setup the channels. */ 419 mtu->num_channels = 3; 420 421 mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels, 422 GFP_KERNEL); 423 if (mtu->channels == NULL) { 424 ret = -ENOMEM; 425 goto err_unmap; 426 } 427 428 for (i = 0; i < mtu->num_channels; ++i) { 429 ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu); 430 if (ret < 0) 431 goto err_unmap; 432 } 433 434 platform_set_drvdata(pdev, mtu); 435 436 return 0; 437 438err_unmap: 439 kfree(mtu->channels); 440 iounmap(mtu->mapbase); 441err_clk_unprepare: 442 clk_unprepare(mtu->clk); 443err_clk_put: 444 clk_put(mtu->clk); 445 return ret; 446} 447 448static int sh_mtu2_probe(struct platform_device *pdev) 449{ 450 struct sh_mtu2_device *mtu = platform_get_drvdata(pdev); 451 int ret; 452 453 if (!is_early_platform_device(pdev)) { 454 pm_runtime_set_active(&pdev->dev); 455 pm_runtime_enable(&pdev->dev); 456 } 457 458 if (mtu) { 459 dev_info(&pdev->dev, "kept as earlytimer\n"); 460 goto out; 461 } 462 463 mtu = kzalloc(sizeof(*mtu), GFP_KERNEL); 464 if (mtu == NULL) 465 return -ENOMEM; 466 467 ret = sh_mtu2_setup(mtu, pdev); 468 if (ret) { 469 kfree(mtu); 470 pm_runtime_idle(&pdev->dev); 471 return ret; 472 } 473 if (is_early_platform_device(pdev)) 474 return 0; 475 476 out: 477 if (mtu->has_clockevent) 478 pm_runtime_irq_safe(&pdev->dev); 479 else 480 pm_runtime_idle(&pdev->dev); 481 482 return 0; 483} 484 485static int sh_mtu2_remove(struct platform_device *pdev) 486{ 487 return -EBUSY; /* cannot unregister clockevent */ 488} 489 490static const struct platform_device_id sh_mtu2_id_table[] = { 491 { "sh-mtu2", 0 }, 492 { }, 493}; 494MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table); 495 496static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = { 497 { .compatible = "renesas,mtu2" }, 498 { } 499}; 500MODULE_DEVICE_TABLE(of, sh_mtu2_of_table); 501 502static struct platform_driver sh_mtu2_device_driver = { 503 .probe = sh_mtu2_probe, 504 .remove = sh_mtu2_remove, 505 .driver = { 506 .name = "sh_mtu2", 507 .of_match_table = of_match_ptr(sh_mtu2_of_table), 508 }, 509 .id_table = sh_mtu2_id_table, 510}; 511 512static int __init sh_mtu2_init(void) 513{ 514 return platform_driver_register(&sh_mtu2_device_driver); 515} 516 517static void __exit sh_mtu2_exit(void) 518{ 519 platform_driver_unregister(&sh_mtu2_device_driver); 520} 521 522early_platform_init("earlytimer", &sh_mtu2_device_driver); 523subsys_initcall(sh_mtu2_init); 524module_exit(sh_mtu2_exit); 525 526MODULE_AUTHOR("Magnus Damm"); 527MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); 528MODULE_LICENSE("GPL v2"); 529