1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/sched_clock.h>
28
29#include <asm/delay.h>
30
31#define TIMER_MATCH_VAL			0x0000
32#define TIMER_COUNT_VAL			0x0004
33#define TIMER_ENABLE			0x0008
34#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
35#define TIMER_ENABLE_EN			BIT(0)
36#define TIMER_CLEAR			0x000C
37#define DGT_CLK_CTL			0x10
38#define DGT_CLK_CTL_DIV_4		0x3
39#define TIMER_STS_GPT0_CLR_PEND		BIT(10)
40
41#define GPT_HZ 32768
42
43static void __iomem *event_base;
44static void __iomem *sts_base;
45
46static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
47{
48	struct clock_event_device *evt = dev_id;
49	/* Stop the timer tick */
50	if (clockevent_state_oneshot(evt)) {
51		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
52		ctrl &= ~TIMER_ENABLE_EN;
53		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
54	}
55	evt->event_handler(evt);
56	return IRQ_HANDLED;
57}
58
59static int msm_timer_set_next_event(unsigned long cycles,
60				    struct clock_event_device *evt)
61{
62	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
63
64	ctrl &= ~TIMER_ENABLE_EN;
65	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
66
67	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
68	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
69
70	if (sts_base)
71		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
72			cpu_relax();
73
74	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
75	return 0;
76}
77
78static int msm_timer_shutdown(struct clock_event_device *evt)
79{
80	u32 ctrl;
81
82	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
83	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
84	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
85	return 0;
86}
87
88static struct clock_event_device __percpu *msm_evt;
89
90static void __iomem *source_base;
91
92static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
93{
94	return readl_relaxed(source_base + TIMER_COUNT_VAL);
95}
96
97static struct clocksource msm_clocksource = {
98	.name	= "dg_timer",
99	.rating	= 300,
100	.read	= msm_read_timer_count,
101	.mask	= CLOCKSOURCE_MASK(32),
102	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
103};
104
105static int msm_timer_irq;
106static int msm_timer_has_ppi;
107
108static int msm_local_timer_setup(struct clock_event_device *evt)
109{
110	int cpu = smp_processor_id();
111	int err;
112
113	evt->irq = msm_timer_irq;
114	evt->name = "msm_timer";
115	evt->features = CLOCK_EVT_FEAT_ONESHOT;
116	evt->rating = 200;
117	evt->set_state_shutdown = msm_timer_shutdown;
118	evt->set_state_oneshot = msm_timer_shutdown;
119	evt->tick_resume = msm_timer_shutdown;
120	evt->set_next_event = msm_timer_set_next_event;
121	evt->cpumask = cpumask_of(cpu);
122
123	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
124
125	if (msm_timer_has_ppi) {
126		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
127	} else {
128		err = request_irq(evt->irq, msm_timer_interrupt,
129				IRQF_TIMER | IRQF_NOBALANCING |
130				IRQF_TRIGGER_RISING, "gp_timer", evt);
131		if (err)
132			pr_err("request_irq failed\n");
133	}
134
135	return 0;
136}
137
138static void msm_local_timer_stop(struct clock_event_device *evt)
139{
140	evt->set_state_shutdown(evt);
141	disable_percpu_irq(evt->irq);
142}
143
144static int msm_timer_cpu_notify(struct notifier_block *self,
145					   unsigned long action, void *hcpu)
146{
147	/*
148	 * Grab cpu pointer in each case to avoid spurious
149	 * preemptible warnings
150	 */
151	switch (action & ~CPU_TASKS_FROZEN) {
152	case CPU_STARTING:
153		msm_local_timer_setup(this_cpu_ptr(msm_evt));
154		break;
155	case CPU_DYING:
156		msm_local_timer_stop(this_cpu_ptr(msm_evt));
157		break;
158	}
159
160	return NOTIFY_OK;
161}
162
163static struct notifier_block msm_timer_cpu_nb = {
164	.notifier_call = msm_timer_cpu_notify,
165};
166
167static u64 notrace msm_sched_clock_read(void)
168{
169	return msm_clocksource.read(&msm_clocksource);
170}
171
172static unsigned long msm_read_current_timer(void)
173{
174	return msm_clocksource.read(&msm_clocksource);
175}
176
177static struct delay_timer msm_delay_timer = {
178	.read_current_timer = msm_read_current_timer,
179};
180
181static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
182				  bool percpu)
183{
184	struct clocksource *cs = &msm_clocksource;
185	int res = 0;
186
187	msm_timer_irq = irq;
188	msm_timer_has_ppi = percpu;
189
190	msm_evt = alloc_percpu(struct clock_event_device);
191	if (!msm_evt) {
192		pr_err("memory allocation failed for clockevents\n");
193		goto err;
194	}
195
196	if (percpu)
197		res = request_percpu_irq(irq, msm_timer_interrupt,
198					 "gp_timer", msm_evt);
199
200	if (res) {
201		pr_err("request_percpu_irq failed\n");
202	} else {
203		res = register_cpu_notifier(&msm_timer_cpu_nb);
204		if (res) {
205			free_percpu_irq(irq, msm_evt);
206			goto err;
207		}
208
209		/* Immediately configure the timer on the boot CPU */
210		msm_local_timer_setup(raw_cpu_ptr(msm_evt));
211	}
212
213err:
214	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
215	res = clocksource_register_hz(cs, dgt_hz);
216	if (res)
217		pr_err("clocksource_register failed\n");
218	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
219	msm_delay_timer.freq = dgt_hz;
220	register_current_timer_delay(&msm_delay_timer);
221}
222
223static void __init msm_dt_timer_init(struct device_node *np)
224{
225	u32 freq;
226	int irq;
227	struct resource res;
228	u32 percpu_offset;
229	void __iomem *base;
230	void __iomem *cpu0_base;
231
232	base = of_iomap(np, 0);
233	if (!base) {
234		pr_err("Failed to map event base\n");
235		return;
236	}
237
238	/* We use GPT0 for the clockevent */
239	irq = irq_of_parse_and_map(np, 1);
240	if (irq <= 0) {
241		pr_err("Can't get irq\n");
242		return;
243	}
244
245	/* We use CPU0's DGT for the clocksource */
246	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
247		percpu_offset = 0;
248
249	if (of_address_to_resource(np, 0, &res)) {
250		pr_err("Failed to parse DGT resource\n");
251		return;
252	}
253
254	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
255	if (!cpu0_base) {
256		pr_err("Failed to map source base\n");
257		return;
258	}
259
260	if (of_property_read_u32(np, "clock-frequency", &freq)) {
261		pr_err("Unknown frequency\n");
262		return;
263	}
264
265	event_base = base + 0x4;
266	sts_base = base + 0x88;
267	source_base = cpu0_base + 0x24;
268	freq /= 4;
269	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
270
271	msm_timer_init(freq, 32, irq, !!percpu_offset);
272}
273CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
274CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
275