1/* 2 * clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator 3 * 4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Rabeeh Khoury <rabeeh@solid-run.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13#ifndef _CLK_SI5351_H_ 14#define _CLK_SI5351_H_ 15 16#define SI5351_BUS_BASE_ADDR 0x60 17 18#define SI5351_PLL_VCO_MIN 600000000 19#define SI5351_PLL_VCO_MAX 900000000 20#define SI5351_MULTISYNTH_MIN_FREQ 1000000 21#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000 22#define SI5351_MULTISYNTH_MAX_FREQ 160000000 23#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ 24#define SI5351_CLKOUT_MIN_FREQ 8000 25#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ 26#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ 27 28#define SI5351_PLL_A_MIN 15 29#define SI5351_PLL_A_MAX 90 30#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1) 31#define SI5351_PLL_C_MAX 1048575 32#define SI5351_MULTISYNTH_A_MIN 6 33#define SI5351_MULTISYNTH_A_MAX 1800 34#define SI5351_MULTISYNTH67_A_MAX 254 35#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1) 36#define SI5351_MULTISYNTH_C_MAX 1048575 37#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1) 38#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1) 39#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1) 40 41#define SI5351_DEVICE_STATUS 0 42#define SI5351_INTERRUPT_STATUS 1 43#define SI5351_INTERRUPT_MASK 2 44#define SI5351_STATUS_SYS_INIT (1<<7) 45#define SI5351_STATUS_LOL_B (1<<6) 46#define SI5351_STATUS_LOL_A (1<<5) 47#define SI5351_STATUS_LOS (1<<4) 48#define SI5351_OUTPUT_ENABLE_CTRL 3 49#define SI5351_OEB_PIN_ENABLE_CTRL 9 50#define SI5351_PLL_INPUT_SOURCE 15 51#define SI5351_CLKIN_DIV_MASK (3<<6) 52#define SI5351_CLKIN_DIV_1 (0<<6) 53#define SI5351_CLKIN_DIV_2 (1<<6) 54#define SI5351_CLKIN_DIV_4 (2<<6) 55#define SI5351_CLKIN_DIV_8 (3<<6) 56#define SI5351_PLLB_SOURCE (1<<3) 57#define SI5351_PLLA_SOURCE (1<<2) 58 59#define SI5351_CLK0_CTRL 16 60#define SI5351_CLK1_CTRL 17 61#define SI5351_CLK2_CTRL 18 62#define SI5351_CLK3_CTRL 19 63#define SI5351_CLK4_CTRL 20 64#define SI5351_CLK5_CTRL 21 65#define SI5351_CLK6_CTRL 22 66#define SI5351_CLK7_CTRL 23 67#define SI5351_CLK_POWERDOWN (1<<7) 68#define SI5351_CLK_INTEGER_MODE (1<<6) 69#define SI5351_CLK_PLL_SELECT (1<<5) 70#define SI5351_CLK_INVERT (1<<4) 71#define SI5351_CLK_INPUT_MASK (3<<2) 72#define SI5351_CLK_INPUT_XTAL (0<<2) 73#define SI5351_CLK_INPUT_CLKIN (1<<2) 74#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2) 75#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2) 76#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0) 77#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0) 78#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0) 79#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0) 80#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0) 81 82#define SI5351_CLK3_0_DISABLE_STATE 24 83#define SI5351_CLK7_4_DISABLE_STATE 25 84#define SI5351_CLK_DISABLE_STATE_MASK 3 85#define SI5351_CLK_DISABLE_STATE_LOW 0 86#define SI5351_CLK_DISABLE_STATE_HIGH 1 87#define SI5351_CLK_DISABLE_STATE_FLOAT 2 88#define SI5351_CLK_DISABLE_STATE_NEVER 3 89 90#define SI5351_PARAMETERS_LENGTH 8 91#define SI5351_PLLA_PARAMETERS 26 92#define SI5351_PLLB_PARAMETERS 34 93#define SI5351_CLK0_PARAMETERS 42 94#define SI5351_CLK1_PARAMETERS 50 95#define SI5351_CLK2_PARAMETERS 58 96#define SI5351_CLK3_PARAMETERS 66 97#define SI5351_CLK4_PARAMETERS 74 98#define SI5351_CLK5_PARAMETERS 82 99#define SI5351_CLK6_PARAMETERS 90 100#define SI5351_CLK7_PARAMETERS 91 101#define SI5351_CLK6_7_OUTPUT_DIVIDER 92 102#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4) 103#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0) 104#define SI5351_OUTPUT_CLK_DIV_SHIFT 4 105#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0 106#define SI5351_OUTPUT_CLK_DIV_1 0 107#define SI5351_OUTPUT_CLK_DIV_2 1 108#define SI5351_OUTPUT_CLK_DIV_4 2 109#define SI5351_OUTPUT_CLK_DIV_8 3 110#define SI5351_OUTPUT_CLK_DIV_16 4 111#define SI5351_OUTPUT_CLK_DIV_32 5 112#define SI5351_OUTPUT_CLK_DIV_64 6 113#define SI5351_OUTPUT_CLK_DIV_128 7 114#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2) 115 116#define SI5351_SSC_PARAM0 149 117#define SI5351_SSC_PARAM1 150 118#define SI5351_SSC_PARAM2 151 119#define SI5351_SSC_PARAM3 152 120#define SI5351_SSC_PARAM4 153 121#define SI5351_SSC_PARAM5 154 122#define SI5351_SSC_PARAM6 155 123#define SI5351_SSC_PARAM7 156 124#define SI5351_SSC_PARAM8 157 125#define SI5351_SSC_PARAM9 158 126#define SI5351_SSC_PARAM10 159 127#define SI5351_SSC_PARAM11 160 128#define SI5351_SSC_PARAM12 161 129 130#define SI5351_VXCO_PARAMETERS_LOW 162 131#define SI5351_VXCO_PARAMETERS_MID 163 132#define SI5351_VXCO_PARAMETERS_HIGH 164 133 134#define SI5351_CLK0_PHASE_OFFSET 165 135#define SI5351_CLK1_PHASE_OFFSET 166 136#define SI5351_CLK2_PHASE_OFFSET 167 137#define SI5351_CLK3_PHASE_OFFSET 168 138#define SI5351_CLK4_PHASE_OFFSET 169 139#define SI5351_CLK5_PHASE_OFFSET 170 140 141#define SI5351_PLL_RESET 177 142#define SI5351_PLL_RESET_B (1<<7) 143#define SI5351_PLL_RESET_A (1<<5) 144 145#define SI5351_CRYSTAL_LOAD 183 146#define SI5351_CRYSTAL_LOAD_MASK (3<<6) 147#define SI5351_CRYSTAL_LOAD_6PF (1<<6) 148#define SI5351_CRYSTAL_LOAD_8PF (2<<6) 149#define SI5351_CRYSTAL_LOAD_10PF (3<<6) 150 151#define SI5351_FANOUT_ENABLE 187 152#define SI5351_CLKIN_ENABLE (1<<7) 153#define SI5351_XTAL_ENABLE (1<<6) 154#define SI5351_MULTISYNTH_ENABLE (1<<4) 155 156/** 157 * enum si5351_variant - SiLabs Si5351 chip variant 158 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) 159 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) 160 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) 161 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) 162 */ 163enum si5351_variant { 164 SI5351_VARIANT_A = 1, 165 SI5351_VARIANT_A3 = 2, 166 SI5351_VARIANT_B = 3, 167 SI5351_VARIANT_C = 4, 168}; 169 170#endif 171