1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 *		http://www.samsung.com
4 *
5 * PATA driver for Samsung SoCs.
6 * Supports CF Interface in True IDE mode. Currently only PIO mode has been
7 * implemented; UDMA support has to be added.
8 *
9 * Based on:
10 *	PATA driver for AT91SAM9260 Static Memory Controller
11 *	PATA driver for Toshiba SCC controller
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16*/
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/libata.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25
26#include <linux/platform_data/ata-samsung_cf.h>
27
28#define DRV_NAME "pata_samsung_cf"
29#define DRV_VERSION "0.1"
30
31#define S3C_CFATA_REG(x)	(x)
32#define S3C_CFATA_MUX		S3C_CFATA_REG(0x0)
33#define S3C_ATA_CTRL		S3C_CFATA_REG(0x0)
34#define S3C_ATA_CMD		S3C_CFATA_REG(0x8)
35#define S3C_ATA_IRQ		S3C_CFATA_REG(0x10)
36#define S3C_ATA_IRQ_MSK		S3C_CFATA_REG(0x14)
37#define S3C_ATA_CFG		S3C_CFATA_REG(0x18)
38
39#define S3C_ATA_PIO_TIME	S3C_CFATA_REG(0x2c)
40#define S3C_ATA_PIO_DTR		S3C_CFATA_REG(0x54)
41#define S3C_ATA_PIO_FED		S3C_CFATA_REG(0x58)
42#define S3C_ATA_PIO_SCR		S3C_CFATA_REG(0x5c)
43#define S3C_ATA_PIO_LLR		S3C_CFATA_REG(0x60)
44#define S3C_ATA_PIO_LMR		S3C_CFATA_REG(0x64)
45#define S3C_ATA_PIO_LHR		S3C_CFATA_REG(0x68)
46#define S3C_ATA_PIO_DVR		S3C_CFATA_REG(0x6c)
47#define S3C_ATA_PIO_CSD		S3C_CFATA_REG(0x70)
48#define S3C_ATA_PIO_DAD		S3C_CFATA_REG(0x74)
49#define S3C_ATA_PIO_RDATA	S3C_CFATA_REG(0x7c)
50
51#define S3C_CFATA_MUX_TRUEIDE	0x01
52#define S3C_ATA_CFG_SWAP	0x40
53#define S3C_ATA_CFG_IORDYEN	0x02
54
55enum s3c_cpu_type {
56	TYPE_S3C64XX,
57	TYPE_S5PV210,
58};
59
60/*
61 * struct s3c_ide_info - S3C PATA instance.
62 * @clk: The clock resource for this controller.
63 * @ide_addr: The area mapped for the hardware registers.
64 * @sfr_addr: The area mapped for the special function registers.
65 * @irq: The IRQ number we are using.
66 * @cpu_type: The exact type of this controller.
67 * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
68 */
69struct s3c_ide_info {
70	struct clk *clk;
71	void __iomem *ide_addr;
72	void __iomem *sfr_addr;
73	int irq;
74	enum s3c_cpu_type cpu_type;
75	unsigned int fifo_status_reg;
76};
77
78static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
79{
80	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
81	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
82	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
83}
84
85static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
86{
87	/* Select true-ide as the internal operating mode */
88	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
89		s3c_ide_sfrbase + S3C_CFATA_MUX);
90}
91
92static unsigned long
93pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
94{
95	int t1 = ata->setup;
96	int t2 = ata->act8b;
97	int t2i = ata->rec8b;
98	ulong piotime;
99
100	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
101
102	return piotime;
103}
104
105static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
106{
107	struct s3c_ide_info *info = ap->host->private_data;
108	struct ata_timing timing;
109	int cycle_time;
110	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
111	ulong piotime;
112
113	/* Enables IORDY if mode requires it */
114	if (ata_pio_need_iordy(adev))
115		ata_cfg |= S3C_ATA_CFG_IORDYEN;
116	else
117		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
118
119	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
120
121	ata_timing_compute(adev, adev->pio_mode, &timing,
122					cycle_time * 1000, 0);
123
124	piotime = pata_s3c_setup_timing(info, &timing);
125
126	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
127	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
128}
129
130/*
131 * Waits until the IDE controller is able to perform next read/write
132 * operation to the disk. Needed for 64XX series boards only.
133 */
134static int wait_for_host_ready(struct s3c_ide_info *info)
135{
136	ulong timeout;
137	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
138
139	/* wait for maximum of 20 msec */
140	timeout = jiffies + msecs_to_jiffies(20);
141	while (time_before(jiffies, timeout)) {
142		if ((readl(fifo_reg) >> 28) == 0)
143			return 0;
144	}
145	return -EBUSY;
146}
147
148/*
149 * Writes to one of the task file registers.
150 */
151static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
152{
153	struct s3c_ide_info *info = host->private_data;
154
155	wait_for_host_ready(info);
156	writeb(addr, reg);
157}
158
159/*
160 * Reads from one of the task file registers.
161 */
162static u8 ata_inb(struct ata_host *host, void __iomem *reg)
163{
164	struct s3c_ide_info *info = host->private_data;
165	u8 temp;
166
167	wait_for_host_ready(info);
168	(void) readb(reg);
169	wait_for_host_ready(info);
170	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
171	return temp;
172}
173
174/*
175 * pata_s3c_tf_load - send taskfile registers to host controller
176 */
177static void pata_s3c_tf_load(struct ata_port *ap,
178				const struct ata_taskfile *tf)
179{
180	struct ata_ioports *ioaddr = &ap->ioaddr;
181	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
182
183	if (tf->ctl != ap->last_ctl) {
184		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
185		ap->last_ctl = tf->ctl;
186		ata_wait_idle(ap);
187	}
188
189	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
190		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
191		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
192		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
193		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
194		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
195	}
196
197	if (is_addr) {
198		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
199		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
200		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
201		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
202		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
203	}
204
205	if (tf->flags & ATA_TFLAG_DEVICE)
206		ata_outb(ap->host, tf->device, ioaddr->device_addr);
207
208	ata_wait_idle(ap);
209}
210
211/*
212 * pata_s3c_tf_read - input device's ATA taskfile shadow registers
213 */
214static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
215{
216	struct ata_ioports *ioaddr = &ap->ioaddr;
217
218	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
219	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
220	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
221	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
222	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
223	tf->device = ata_inb(ap->host, ioaddr->device_addr);
224
225	if (tf->flags & ATA_TFLAG_LBA48) {
226		ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
227		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
228		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
229		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
230		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
231		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
232		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
233		ap->last_ctl = tf->ctl;
234	}
235}
236
237/*
238 * pata_s3c_exec_command - issue ATA command to host controller
239 */
240static void pata_s3c_exec_command(struct ata_port *ap,
241				const struct ata_taskfile *tf)
242{
243	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
244	ata_sff_pause(ap);
245}
246
247/*
248 * pata_s3c_check_status - Read device status register
249 */
250static u8 pata_s3c_check_status(struct ata_port *ap)
251{
252	return ata_inb(ap->host, ap->ioaddr.status_addr);
253}
254
255/*
256 * pata_s3c_check_altstatus - Read alternate device status register
257 */
258static u8 pata_s3c_check_altstatus(struct ata_port *ap)
259{
260	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
261}
262
263/*
264 * pata_s3c_data_xfer - Transfer data by PIO
265 */
266static unsigned int pata_s3c_data_xfer(struct ata_device *dev,
267				unsigned char *buf, unsigned int buflen, int rw)
268{
269	struct ata_port *ap = dev->link->ap;
270	struct s3c_ide_info *info = ap->host->private_data;
271	void __iomem *data_addr = ap->ioaddr.data_addr;
272	unsigned int words = buflen >> 1, i;
273	u16 *data_ptr = (u16 *)buf;
274
275	/* Requires wait same as in ata_inb/ata_outb */
276	if (rw == READ)
277		for (i = 0; i < words; i++, data_ptr++) {
278			wait_for_host_ready(info);
279			(void) readw(data_addr);
280			wait_for_host_ready(info);
281			*data_ptr = readw(info->ide_addr
282					+ S3C_ATA_PIO_RDATA);
283		}
284	else
285		for (i = 0; i < words; i++, data_ptr++) {
286			wait_for_host_ready(info);
287			writew(*data_ptr, data_addr);
288		}
289
290	if (buflen & 0x01)
291		dev_err(ap->dev, "unexpected trailing data\n");
292
293	return words << 1;
294}
295
296/*
297 * pata_s3c_dev_select - Select device on ATA bus
298 */
299static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
300{
301	u8 tmp = ATA_DEVICE_OBS;
302
303	if (device != 0)
304		tmp |= ATA_DEV1;
305
306	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
307	ata_sff_pause(ap);
308}
309
310/*
311 * pata_s3c_devchk - PATA device presence detection
312 */
313static unsigned int pata_s3c_devchk(struct ata_port *ap,
314				unsigned int device)
315{
316	struct ata_ioports *ioaddr = &ap->ioaddr;
317	u8 nsect, lbal;
318
319	pata_s3c_dev_select(ap, device);
320
321	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
322	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
323
324	ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
325	ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
326
327	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
328	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
329
330	nsect = ata_inb(ap->host, ioaddr->nsect_addr);
331	lbal = ata_inb(ap->host, ioaddr->lbal_addr);
332
333	if ((nsect == 0x55) && (lbal == 0xaa))
334		return 1;	/* we found a device */
335
336	return 0;		/* nothing found */
337}
338
339/*
340 * pata_s3c_wait_after_reset - wait for devices to become ready after reset
341 */
342static int pata_s3c_wait_after_reset(struct ata_link *link,
343		unsigned long deadline)
344{
345	int rc;
346
347	ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
348
349	/* always check readiness of the master device */
350	rc = ata_sff_wait_ready(link, deadline);
351	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
352	 * and TF status is 0xff, bail out on it too.
353	 */
354	if (rc)
355		return rc;
356
357	return 0;
358}
359
360/*
361 * pata_s3c_bus_softreset - PATA device software reset
362 */
363static int pata_s3c_bus_softreset(struct ata_port *ap,
364		unsigned long deadline)
365{
366	struct ata_ioports *ioaddr = &ap->ioaddr;
367
368	/* software reset.  causes dev0 to be selected */
369	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
370	udelay(20);
371	ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
372	udelay(20);
373	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
374	ap->last_ctl = ap->ctl;
375
376	return pata_s3c_wait_after_reset(&ap->link, deadline);
377}
378
379/*
380 * pata_s3c_softreset - reset host port via ATA SRST
381 */
382static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
383			 unsigned long deadline)
384{
385	struct ata_port *ap = link->ap;
386	unsigned int devmask = 0;
387	int rc;
388	u8 err;
389
390	/* determine if device 0 is present */
391	if (pata_s3c_devchk(ap, 0))
392		devmask |= (1 << 0);
393
394	/* select device 0 again */
395	pata_s3c_dev_select(ap, 0);
396
397	/* issue bus reset */
398	rc = pata_s3c_bus_softreset(ap, deadline);
399	/* if link is occupied, -ENODEV too is an error */
400	if (rc && rc != -ENODEV) {
401		ata_link_err(link, "SRST failed (errno=%d)\n", rc);
402		return rc;
403	}
404
405	/* determine by signature whether we have ATA or ATAPI devices */
406	classes[0] = ata_sff_dev_classify(&ap->link.device[0],
407					  devmask & (1 << 0), &err);
408
409	return 0;
410}
411
412/*
413 * pata_s3c_set_devctl - Write device control register
414 */
415static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
416{
417	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
418}
419
420static struct scsi_host_template pata_s3c_sht = {
421	ATA_PIO_SHT(DRV_NAME),
422};
423
424static struct ata_port_operations pata_s3c_port_ops = {
425	.inherits		= &ata_sff_port_ops,
426	.sff_check_status	= pata_s3c_check_status,
427	.sff_check_altstatus    = pata_s3c_check_altstatus,
428	.sff_tf_load		= pata_s3c_tf_load,
429	.sff_tf_read		= pata_s3c_tf_read,
430	.sff_data_xfer		= pata_s3c_data_xfer,
431	.sff_exec_command	= pata_s3c_exec_command,
432	.sff_dev_select         = pata_s3c_dev_select,
433	.sff_set_devctl         = pata_s3c_set_devctl,
434	.softreset		= pata_s3c_softreset,
435	.set_piomode		= pata_s3c_set_piomode,
436};
437
438static struct ata_port_operations pata_s5p_port_ops = {
439	.inherits		= &ata_sff_port_ops,
440	.set_piomode		= pata_s3c_set_piomode,
441};
442
443static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
444{
445	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
446	temp = state ? (temp | 1) : (temp & ~1);
447	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
448}
449
450static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
451{
452	struct ata_host *host = dev_instance;
453	struct s3c_ide_info *info = host->private_data;
454	u32 reg;
455
456	reg = readl(info->ide_addr + S3C_ATA_IRQ);
457	writel(reg, info->ide_addr + S3C_ATA_IRQ);
458
459	return ata_sff_interrupt(irq, dev_instance);
460}
461
462static void pata_s3c_hwinit(struct s3c_ide_info *info,
463				struct s3c_ide_platdata *pdata)
464{
465	switch (info->cpu_type) {
466	case TYPE_S3C64XX:
467		/* Configure as big endian */
468		pata_s3c_cfg_mode(info->sfr_addr);
469		pata_s3c_set_endian(info->ide_addr, 1);
470		pata_s3c_enable(info->ide_addr, true);
471		msleep(100);
472
473		/* Remove IRQ Status */
474		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
475		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
476		break;
477
478	case TYPE_S5PV210:
479		/* Configure as little endian */
480		pata_s3c_set_endian(info->ide_addr, 0);
481		pata_s3c_enable(info->ide_addr, true);
482		msleep(100);
483
484		/* Remove IRQ Status */
485		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
486		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
487		break;
488
489	default:
490		BUG();
491	}
492}
493
494static int __init pata_s3c_probe(struct platform_device *pdev)
495{
496	struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
497	struct device *dev = &pdev->dev;
498	struct s3c_ide_info *info;
499	struct resource *res;
500	struct ata_port *ap;
501	struct ata_host *host;
502	enum s3c_cpu_type cpu_type;
503	int ret;
504
505	cpu_type = platform_get_device_id(pdev)->driver_data;
506
507	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
508	if (!info) {
509		dev_err(dev, "failed to allocate memory for device data\n");
510		return -ENOMEM;
511	}
512
513	info->irq = platform_get_irq(pdev, 0);
514
515	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
516
517	info->ide_addr = devm_ioremap_resource(dev, res);
518	if (IS_ERR(info->ide_addr))
519		return PTR_ERR(info->ide_addr);
520
521	info->clk = devm_clk_get(&pdev->dev, "cfcon");
522	if (IS_ERR(info->clk)) {
523		dev_err(dev, "failed to get access to cf controller clock\n");
524		ret = PTR_ERR(info->clk);
525		info->clk = NULL;
526		return ret;
527	}
528
529	clk_enable(info->clk);
530
531	/* init ata host */
532	host = ata_host_alloc(dev, 1);
533	if (!host) {
534		dev_err(dev, "failed to allocate ide host\n");
535		ret = -ENOMEM;
536		goto stop_clk;
537	}
538
539	ap = host->ports[0];
540	ap->pio_mask = ATA_PIO4;
541
542	if (cpu_type == TYPE_S3C64XX) {
543		ap->ops = &pata_s3c_port_ops;
544		info->sfr_addr = info->ide_addr + 0x1800;
545		info->ide_addr += 0x1900;
546		info->fifo_status_reg = 0x94;
547	} else {
548		ap->ops = &pata_s5p_port_ops;
549		info->fifo_status_reg = 0x84;
550	}
551
552	info->cpu_type = cpu_type;
553
554	if (info->irq <= 0) {
555		ap->flags |= ATA_FLAG_PIO_POLLING;
556		info->irq = 0;
557		ata_port_desc(ap, "no IRQ, using PIO polling\n");
558	}
559
560	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
561	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
562	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
563	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
564	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
565	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
566	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
567	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
568	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
569	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
570	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
571	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
572	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
573
574	ata_port_desc(ap, "mmio cmd 0x%llx ",
575			(unsigned long long)res->start);
576
577	host->private_data = info;
578
579	if (pdata && pdata->setup_gpio)
580		pdata->setup_gpio();
581
582	/* Set endianness and enable the interface */
583	pata_s3c_hwinit(info, pdata);
584
585	platform_set_drvdata(pdev, host);
586
587	ret = ata_host_activate(host, info->irq,
588				info->irq ? pata_s3c_irq : NULL,
589				0, &pata_s3c_sht);
590	if (ret)
591		goto stop_clk;
592
593	return 0;
594
595stop_clk:
596	clk_disable(info->clk);
597	return ret;
598}
599
600static int __exit pata_s3c_remove(struct platform_device *pdev)
601{
602	struct ata_host *host = platform_get_drvdata(pdev);
603	struct s3c_ide_info *info = host->private_data;
604
605	ata_host_detach(host);
606
607	clk_disable(info->clk);
608
609	return 0;
610}
611
612#ifdef CONFIG_PM_SLEEP
613static int pata_s3c_suspend(struct device *dev)
614{
615	struct platform_device *pdev = to_platform_device(dev);
616	struct ata_host *host = platform_get_drvdata(pdev);
617
618	return ata_host_suspend(host, PMSG_SUSPEND);
619}
620
621static int pata_s3c_resume(struct device *dev)
622{
623	struct platform_device *pdev = to_platform_device(dev);
624	struct ata_host *host = platform_get_drvdata(pdev);
625	struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
626	struct s3c_ide_info *info = host->private_data;
627
628	pata_s3c_hwinit(info, pdata);
629	ata_host_resume(host);
630
631	return 0;
632}
633
634static const struct dev_pm_ops pata_s3c_pm_ops = {
635	.suspend	= pata_s3c_suspend,
636	.resume		= pata_s3c_resume,
637};
638#endif
639
640/* driver device registration */
641static const struct platform_device_id pata_s3c_driver_ids[] = {
642	{
643		.name		= "s3c64xx-pata",
644		.driver_data	= TYPE_S3C64XX,
645	}, {
646		.name		= "s5pv210-pata",
647		.driver_data	= TYPE_S5PV210,
648	},
649	{ }
650};
651
652MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
653
654static struct platform_driver pata_s3c_driver = {
655	.remove		= __exit_p(pata_s3c_remove),
656	.id_table	= pata_s3c_driver_ids,
657	.driver		= {
658		.name	= DRV_NAME,
659#ifdef CONFIG_PM_SLEEP
660		.pm	= &pata_s3c_pm_ops,
661#endif
662	},
663};
664
665module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
666
667MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
668MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
669MODULE_LICENSE("GPL");
670MODULE_VERSION(DRV_VERSION);
671