1/* 2 * pata_artop.c - ARTOP ATA controller driver 3 * 4 * (C) 2006 Red Hat 5 * (C) 2007,2011 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on drivers/ide/pci/aec62xx.c 8 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 9 * 865/865R fixes for Macintosh card version from a patch to the old 10 * driver by Thibaut VARENE <varenet@parisc-linux.org> 11 * When setting the PCI latency we must set 0x80 or higher for burst 12 * performance Alessandro Zummo <alessandro.zummo@towertech.it> 13 * 14 * TODO 15 * Investigate no_dsc on 850R 16 * Clock detect 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/device.h> 25#include <scsi/scsi_host.h> 26#include <linux/libata.h> 27#include <linux/ata.h> 28 29#define DRV_NAME "pata_artop" 30#define DRV_VERSION "0.4.6" 31 32/* 33 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we 34 * get PCI bus speed functionality we leave this as 0. Its a variable 35 * for when we get the functionality and also for folks wanting to 36 * test stuff. 37 */ 38 39static int clock = 0; 40 41/** 42 * artop62x0_pre_reset - probe begin 43 * @link: link 44 * @deadline: deadline jiffies for the operation 45 * 46 * Nothing complicated needed here. 47 */ 48 49static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline) 50{ 51 static const struct pci_bits artop_enable_bits[] = { 52 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 53 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 54 }; 55 56 struct ata_port *ap = link->ap; 57 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 58 59 /* Odd numbered device ids are the units with enable bits. */ 60 if ((pdev->device & 1) && 61 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) 62 return -ENOENT; 63 64 return ata_sff_prereset(link, deadline); 65} 66 67/** 68 * artop6260_cable_detect - identify cable type 69 * @ap: Port 70 * 71 * Identify the cable type for the ARTOP interface in question 72 */ 73 74static int artop6260_cable_detect(struct ata_port *ap) 75{ 76 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 77 u8 tmp; 78 pci_read_config_byte(pdev, 0x49, &tmp); 79 if (tmp & (1 << ap->port_no)) 80 return ATA_CBL_PATA40; 81 return ATA_CBL_PATA80; 82} 83 84/** 85 * artop6210_load_piomode - Load a set of PATA PIO timings 86 * @ap: Port whose timings we are configuring 87 * @adev: Device 88 * @pio: PIO mode 89 * 90 * Set PIO mode for device, in host controller PCI config space. This 91 * is used both to set PIO timings in PIO mode and also to set the 92 * matching PIO clocking for UDMA, as well as the MWDMA timings. 93 * 94 * LOCKING: 95 * None (inherited from caller). 96 */ 97 98static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) 99{ 100 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 101 int dn = adev->devno + 2 * ap->port_no; 102 const u16 timing[2][5] = { 103 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 }, 104 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 } 105 106 }; 107 /* Load the PIO timing active/recovery bits */ 108 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); 109} 110 111/** 112 * artop6210_set_piomode - Initialize host controller PATA PIO timings 113 * @ap: Port whose timings we are configuring 114 * @adev: Device we are configuring 115 * 116 * Set PIO mode for device, in host controller PCI config space. For 117 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 118 * the event UDMA is used the later call to set_dmamode will set the 119 * bits as required. 120 * 121 * LOCKING: 122 * None (inherited from caller). 123 */ 124 125static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev) 126{ 127 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 128 int dn = adev->devno + 2 * ap->port_no; 129 u8 ultra; 130 131 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 132 133 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 134 pci_read_config_byte(pdev, 0x54, &ultra); 135 ultra &= ~(3 << (2 * dn)); 136 pci_write_config_byte(pdev, 0x54, ultra); 137} 138 139/** 140 * artop6260_load_piomode - Initialize host controller PATA PIO timings 141 * @ap: Port whose timings we are configuring 142 * @adev: Device we are configuring 143 * @pio: PIO mode 144 * 145 * Set PIO mode for device, in host controller PCI config space. The 146 * ARTOP6260 and relatives store the timing data differently. 147 * 148 * LOCKING: 149 * None (inherited from caller). 150 */ 151 152static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio) 153{ 154 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 155 int dn = adev->devno + 2 * ap->port_no; 156 const u8 timing[2][5] = { 157 { 0x00, 0x0A, 0x08, 0x33, 0x31 }, 158 { 0x70, 0x7A, 0x78, 0x43, 0x41 } 159 160 }; 161 /* Load the PIO timing active/recovery bits */ 162 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); 163} 164 165/** 166 * artop6260_set_piomode - Initialize host controller PATA PIO timings 167 * @ap: Port whose timings we are configuring 168 * @adev: Device we are configuring 169 * 170 * Set PIO mode for device, in host controller PCI config space. For 171 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 172 * the event UDMA is used the later call to set_dmamode will set the 173 * bits as required. 174 * 175 * LOCKING: 176 * None (inherited from caller). 177 */ 178 179static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev) 180{ 181 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 182 u8 ultra; 183 184 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 185 186 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 187 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 188 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 189 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 190} 191 192/** 193 * artop6210_set_dmamode - Initialize host controller PATA PIO timings 194 * @ap: Port whose timings we are configuring 195 * @adev: Device whose timings we are configuring 196 * 197 * Set DMA mode for device, in host controller PCI config space. 198 * 199 * LOCKING: 200 * None (inherited from caller). 201 */ 202 203static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev) 204{ 205 unsigned int pio; 206 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 207 int dn = adev->devno + 2 * ap->port_no; 208 u8 ultra; 209 210 if (adev->dma_mode == XFER_MW_DMA_0) 211 pio = 1; 212 else 213 pio = 4; 214 215 /* Load the PIO timing active/recovery bits */ 216 artop6210_load_piomode(ap, adev, pio); 217 218 pci_read_config_byte(pdev, 0x54, &ultra); 219 ultra &= ~(3 << (2 * dn)); 220 221 /* Add ultra DMA bits if in UDMA mode */ 222 if (adev->dma_mode >= XFER_UDMA_0) { 223 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock; 224 if (mode == 0) 225 mode = 1; 226 ultra |= (mode << (2 * dn)); 227 } 228 pci_write_config_byte(pdev, 0x54, ultra); 229} 230 231/** 232 * artop6260_set_dmamode - Initialize host controller PATA PIO timings 233 * @ap: Port whose timings we are configuring 234 * @adev: Device we are configuring 235 * 236 * Set DMA mode for device, in host controller PCI config space. The 237 * ARTOP6260 and relatives store the timing data differently. 238 * 239 * LOCKING: 240 * None (inherited from caller). 241 */ 242 243static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev) 244{ 245 unsigned int pio = adev->pio_mode - XFER_PIO_0; 246 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 247 u8 ultra; 248 249 if (adev->dma_mode == XFER_MW_DMA_0) 250 pio = 1; 251 else 252 pio = 4; 253 254 /* Load the PIO timing active/recovery bits */ 255 artop6260_load_piomode(ap, adev, pio); 256 257 /* Add ultra DMA bits if in UDMA mode */ 258 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 259 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 260 if (adev->dma_mode >= XFER_UDMA_0) { 261 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock; 262 if (mode == 0) 263 mode = 1; 264 ultra |= (mode << (4 * adev->devno)); 265 } 266 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 267} 268 269/** 270 * artop_6210_qc_defer - implement serialization 271 * @qc: command 272 * 273 * Issue commands per host on this chip. 274 */ 275 276static int artop6210_qc_defer(struct ata_queued_cmd *qc) 277{ 278 struct ata_host *host = qc->ap->host; 279 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 280 int rc; 281 282 /* First apply the usual rules */ 283 rc = ata_std_qc_defer(qc); 284 if (rc != 0) 285 return rc; 286 287 /* Now apply serialization rules. Only allow a command if the 288 other channel state machine is idle */ 289 if (alt && alt->qc_active) 290 return ATA_DEFER_PORT; 291 return 0; 292} 293 294static struct scsi_host_template artop_sht = { 295 ATA_BMDMA_SHT(DRV_NAME), 296}; 297 298static struct ata_port_operations artop6210_ops = { 299 .inherits = &ata_bmdma_port_ops, 300 .cable_detect = ata_cable_40wire, 301 .set_piomode = artop6210_set_piomode, 302 .set_dmamode = artop6210_set_dmamode, 303 .prereset = artop62x0_pre_reset, 304 .qc_defer = artop6210_qc_defer, 305}; 306 307static struct ata_port_operations artop6260_ops = { 308 .inherits = &ata_bmdma_port_ops, 309 .cable_detect = artop6260_cable_detect, 310 .set_piomode = artop6260_set_piomode, 311 .set_dmamode = artop6260_set_dmamode, 312 .prereset = artop62x0_pre_reset, 313}; 314 315static void atp8xx_fixup(struct pci_dev *pdev) 316{ 317 if (pdev->device == 0x0005) 318 /* BIOS may have left us in UDMA, clear it before libata probe */ 319 pci_write_config_byte(pdev, 0x54, 0); 320 else if (pdev->device == 0x0008 || pdev->device == 0x0009) { 321 u8 reg; 322 323 /* Mac systems come up with some registers not set as we 324 will need them */ 325 326 /* Clear reset & test bits */ 327 pci_read_config_byte(pdev, 0x49, ®); 328 pci_write_config_byte(pdev, 0x49, reg & ~0x30); 329 330 /* PCI latency must be > 0x80 for burst mode, tweak it 331 * if required. 332 */ 333 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); 334 if (reg <= 0x80) 335 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90); 336 337 /* Enable IRQ output and burst mode */ 338 pci_read_config_byte(pdev, 0x4a, ®); 339 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); 340 } 341} 342 343/** 344 * artop_init_one - Register ARTOP ATA PCI device with kernel services 345 * @pdev: PCI device to register 346 * @ent: Entry in artop_pci_tbl matching with @pdev 347 * 348 * Called from kernel PCI layer. 349 * 350 * LOCKING: 351 * Inherited from PCI layer (may sleep). 352 * 353 * RETURNS: 354 * Zero on success, or -ERRNO value. 355 */ 356 357static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) 358{ 359 static const struct ata_port_info info_6210 = { 360 .flags = ATA_FLAG_SLAVE_POSS, 361 .pio_mask = ATA_PIO4, 362 .mwdma_mask = ATA_MWDMA2, 363 .udma_mask = ATA_UDMA2, 364 .port_ops = &artop6210_ops, 365 }; 366 static const struct ata_port_info info_626x = { 367 .flags = ATA_FLAG_SLAVE_POSS, 368 .pio_mask = ATA_PIO4, 369 .mwdma_mask = ATA_MWDMA2, 370 .udma_mask = ATA_UDMA4, 371 .port_ops = &artop6260_ops, 372 }; 373 static const struct ata_port_info info_628x = { 374 .flags = ATA_FLAG_SLAVE_POSS, 375 .pio_mask = ATA_PIO4, 376 .mwdma_mask = ATA_MWDMA2, 377 .udma_mask = ATA_UDMA5, 378 .port_ops = &artop6260_ops, 379 }; 380 static const struct ata_port_info info_628x_fast = { 381 .flags = ATA_FLAG_SLAVE_POSS, 382 .pio_mask = ATA_PIO4, 383 .mwdma_mask = ATA_MWDMA2, 384 .udma_mask = ATA_UDMA6, 385 .port_ops = &artop6260_ops, 386 }; 387 const struct ata_port_info *ppi[] = { NULL, NULL }; 388 int rc; 389 390 ata_print_version_once(&pdev->dev, DRV_VERSION); 391 392 rc = pcim_enable_device(pdev); 393 if (rc) 394 return rc; 395 396 if (id->driver_data == 0) /* 6210 variant */ 397 ppi[0] = &info_6210; 398 else if (id->driver_data == 1) /* 6260 */ 399 ppi[0] = &info_626x; 400 else if (id->driver_data == 2) { /* 6280 or 6280 + fast */ 401 unsigned long io = pci_resource_start(pdev, 4); 402 403 ppi[0] = &info_628x; 404 if (inb(io) & 0x10) 405 ppi[0] = &info_628x_fast; 406 } 407 408 BUG_ON(ppi[0] == NULL); 409 410 atp8xx_fixup(pdev); 411 412 return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0); 413} 414 415static const struct pci_device_id artop_pci_tbl[] = { 416 { PCI_VDEVICE(ARTOP, 0x0005), 0 }, 417 { PCI_VDEVICE(ARTOP, 0x0006), 1 }, 418 { PCI_VDEVICE(ARTOP, 0x0007), 1 }, 419 { PCI_VDEVICE(ARTOP, 0x0008), 2 }, 420 { PCI_VDEVICE(ARTOP, 0x0009), 2 }, 421 422 { } /* terminate list */ 423}; 424 425#ifdef CONFIG_PM_SLEEP 426static int atp8xx_reinit_one(struct pci_dev *pdev) 427{ 428 struct ata_host *host = pci_get_drvdata(pdev); 429 int rc; 430 431 rc = ata_pci_device_do_resume(pdev); 432 if (rc) 433 return rc; 434 435 atp8xx_fixup(pdev); 436 437 ata_host_resume(host); 438 return 0; 439} 440#endif 441 442static struct pci_driver artop_pci_driver = { 443 .name = DRV_NAME, 444 .id_table = artop_pci_tbl, 445 .probe = artop_init_one, 446 .remove = ata_pci_remove_one, 447#ifdef CONFIG_PM_SLEEP 448 .suspend = ata_pci_device_suspend, 449 .resume = atp8xx_reinit_one, 450#endif 451}; 452 453module_pci_driver(artop_pci_driver); 454 455MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz"); 456MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA"); 457MODULE_LICENSE("GPL"); 458MODULE_DEVICE_TABLE(pci, artop_pci_tbl); 459MODULE_VERSION(DRV_VERSION); 460