1#include <linux/perf_event.h>
2
3enum perf_msr_id {
4	PERF_MSR_TSC			= 0,
5	PERF_MSR_APERF			= 1,
6	PERF_MSR_MPERF			= 2,
7	PERF_MSR_PPERF			= 3,
8	PERF_MSR_SMI			= 4,
9
10	PERF_MSR_EVENT_MAX,
11};
12
13static bool test_aperfmperf(int idx)
14{
15	return boot_cpu_has(X86_FEATURE_APERFMPERF);
16}
17
18static bool test_intel(int idx)
19{
20	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
21	    boot_cpu_data.x86 != 6)
22		return false;
23
24	switch (boot_cpu_data.x86_model) {
25	case 30: /* 45nm Nehalem    */
26	case 26: /* 45nm Nehalem-EP */
27	case 46: /* 45nm Nehalem-EX */
28
29	case 37: /* 32nm Westmere    */
30	case 44: /* 32nm Westmere-EP */
31	case 47: /* 32nm Westmere-EX */
32
33	case 42: /* 32nm SandyBridge         */
34	case 45: /* 32nm SandyBridge-E/EN/EP */
35
36	case 58: /* 22nm IvyBridge       */
37	case 62: /* 22nm IvyBridge-EP/EX */
38
39	case 60: /* 22nm Haswell Core */
40	case 63: /* 22nm Haswell Server */
41	case 69: /* 22nm Haswell ULT */
42	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
43
44	case 61: /* 14nm Broadwell Core-M */
45	case 86: /* 14nm Broadwell Xeon D */
46	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
47	case 79: /* 14nm Broadwell Server */
48
49	case 55: /* 22nm Atom "Silvermont"                */
50	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
51	case 76: /* 14nm Atom "Airmont"                   */
52		if (idx == PERF_MSR_SMI)
53			return true;
54		break;
55
56	case 78: /* 14nm Skylake Mobile */
57	case 94: /* 14nm Skylake Desktop */
58		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
59			return true;
60		break;
61	}
62
63	return false;
64}
65
66struct perf_msr {
67	u64	msr;
68	struct	perf_pmu_events_attr *attr;
69	bool	(*test)(int idx);
70};
71
72PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
73PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
74PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
75PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
76PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
77
78static struct perf_msr msr[] = {
79	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
80	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
81	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
82	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
83	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
84};
85
86static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
87	NULL,
88};
89
90static struct attribute_group events_attr_group = {
91	.name = "events",
92	.attrs = events_attrs,
93};
94
95PMU_FORMAT_ATTR(event, "config:0-63");
96static struct attribute *format_attrs[] = {
97	&format_attr_event.attr,
98	NULL,
99};
100static struct attribute_group format_attr_group = {
101	.name = "format",
102	.attrs = format_attrs,
103};
104
105static const struct attribute_group *attr_groups[] = {
106	&events_attr_group,
107	&format_attr_group,
108	NULL,
109};
110
111static int msr_event_init(struct perf_event *event)
112{
113	u64 cfg = event->attr.config;
114
115	if (event->attr.type != event->pmu->type)
116		return -ENOENT;
117
118	if (cfg >= PERF_MSR_EVENT_MAX)
119		return -EINVAL;
120
121	/* unsupported modes and filters */
122	if (event->attr.exclude_user   ||
123	    event->attr.exclude_kernel ||
124	    event->attr.exclude_hv     ||
125	    event->attr.exclude_idle   ||
126	    event->attr.exclude_host   ||
127	    event->attr.exclude_guest  ||
128	    event->attr.sample_period) /* no sampling */
129		return -EINVAL;
130
131	if (!msr[cfg].attr)
132		return -EINVAL;
133
134	event->hw.idx = -1;
135	event->hw.event_base = msr[cfg].msr;
136	event->hw.config = cfg;
137
138	return 0;
139}
140
141static inline u64 msr_read_counter(struct perf_event *event)
142{
143	u64 now;
144
145	if (event->hw.event_base)
146		rdmsrl(event->hw.event_base, now);
147	else
148		rdtscll(now);
149
150	return now;
151}
152static void msr_event_update(struct perf_event *event)
153{
154	u64 prev, now;
155	s64 delta;
156
157	/* Careful, an NMI might modify the previous event value. */
158again:
159	prev = local64_read(&event->hw.prev_count);
160	now = msr_read_counter(event);
161
162	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
163		goto again;
164
165	delta = now - prev;
166	if (unlikely(event->hw.event_base == MSR_SMI_COUNT))
167		delta = sign_extend64(delta, 31);
168
169	local64_add(now - prev, &event->count);
170}
171
172static void msr_event_start(struct perf_event *event, int flags)
173{
174	u64 now;
175
176	now = msr_read_counter(event);
177	local64_set(&event->hw.prev_count, now);
178}
179
180static void msr_event_stop(struct perf_event *event, int flags)
181{
182	msr_event_update(event);
183}
184
185static void msr_event_del(struct perf_event *event, int flags)
186{
187	msr_event_stop(event, PERF_EF_UPDATE);
188}
189
190static int msr_event_add(struct perf_event *event, int flags)
191{
192	if (flags & PERF_EF_START)
193		msr_event_start(event, flags);
194
195	return 0;
196}
197
198static struct pmu pmu_msr = {
199	.task_ctx_nr	= perf_sw_context,
200	.attr_groups	= attr_groups,
201	.event_init	= msr_event_init,
202	.add		= msr_event_add,
203	.del		= msr_event_del,
204	.start		= msr_event_start,
205	.stop		= msr_event_stop,
206	.read		= msr_event_update,
207	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
208};
209
210static int __init msr_init(void)
211{
212	int i, j = 0;
213
214	if (!boot_cpu_has(X86_FEATURE_TSC)) {
215		pr_cont("no MSR PMU driver.\n");
216		return 0;
217	}
218
219	/* Probe the MSRs. */
220	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
221		u64 val;
222
223		/*
224		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
225		 */
226		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
227			msr[i].attr = NULL;
228	}
229
230	/* List remaining MSRs in the sysfs attrs. */
231	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
232		if (msr[i].attr)
233			events_attrs[j++] = &msr[i].attr->attr.attr;
234	}
235	events_attrs[j] = NULL;
236
237	perf_pmu_register(&pmu_msr, "msr", -1);
238
239	return 0;
240}
241device_initcall(msr_init);
242