1/* 2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Enable support of hierarchical irqdomains 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13#include <linux/interrupt.h> 14#include <linux/init.h> 15#include <linux/compiler.h> 16#include <linux/slab.h> 17#include <asm/irqdomain.h> 18#include <asm/hw_irq.h> 19#include <asm/apic.h> 20#include <asm/i8259.h> 21#include <asm/desc.h> 22#include <asm/irq_remapping.h> 23 24struct apic_chip_data { 25 struct irq_cfg cfg; 26 cpumask_var_t domain; 27 cpumask_var_t old_domain; 28 u8 move_in_progress : 1; 29}; 30 31struct irq_domain *x86_vector_domain; 32static DEFINE_RAW_SPINLOCK(vector_lock); 33static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; 34static struct irq_chip lapic_controller; 35#ifdef CONFIG_X86_IO_APIC 36static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; 37#endif 38 39void lock_vector_lock(void) 40{ 41 /* Used to the online set of cpus does not change 42 * during assign_irq_vector. 43 */ 44 raw_spin_lock(&vector_lock); 45} 46 47void unlock_vector_lock(void) 48{ 49 raw_spin_unlock(&vector_lock); 50} 51 52static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) 53{ 54 if (!irq_data) 55 return NULL; 56 57 while (irq_data->parent_data) 58 irq_data = irq_data->parent_data; 59 60 return irq_data->chip_data; 61} 62 63struct irq_cfg *irqd_cfg(struct irq_data *irq_data) 64{ 65 struct apic_chip_data *data = apic_chip_data(irq_data); 66 67 return data ? &data->cfg : NULL; 68} 69 70struct irq_cfg *irq_cfg(unsigned int irq) 71{ 72 return irqd_cfg(irq_get_irq_data(irq)); 73} 74 75static struct apic_chip_data *alloc_apic_chip_data(int node) 76{ 77 struct apic_chip_data *data; 78 79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); 80 if (!data) 81 return NULL; 82 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) 83 goto out_data; 84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) 85 goto out_domain; 86 return data; 87out_domain: 88 free_cpumask_var(data->domain); 89out_data: 90 kfree(data); 91 return NULL; 92} 93 94static void free_apic_chip_data(struct apic_chip_data *data) 95{ 96 if (data) { 97 free_cpumask_var(data->domain); 98 free_cpumask_var(data->old_domain); 99 kfree(data); 100 } 101} 102 103static int __assign_irq_vector(int irq, struct apic_chip_data *d, 104 const struct cpumask *mask) 105{ 106 /* 107 * NOTE! The local APIC isn't very good at handling 108 * multiple interrupts at the same interrupt level. 109 * As the interrupt level is determined by taking the 110 * vector number and shifting that right by 4, we 111 * want to spread these out a bit so that they don't 112 * all fall in the same interrupt level. 113 * 114 * Also, we've got to be careful not to trash gate 115 * 0x80, because int 0x80 is hm, kind of importantish. ;) 116 */ 117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 118 static int current_offset = VECTOR_OFFSET_START % 16; 119 int cpu, vector; 120 121 /* 122 * If there is still a move in progress or the previous move has not 123 * been cleaned up completely, tell the caller to come back later. 124 */ 125 if (d->move_in_progress || 126 cpumask_intersects(d->old_domain, cpu_online_mask)) 127 return -EBUSY; 128 129 /* Only try and allocate irqs on cpus that are present */ 130 cpumask_clear(d->old_domain); 131 cpumask_clear(searched_cpumask); 132 cpu = cpumask_first_and(mask, cpu_online_mask); 133 while (cpu < nr_cpu_ids) { 134 int new_cpu, offset; 135 136 /* Get the possible target cpus for @mask/@cpu from the apic */ 137 apic->vector_allocation_domain(cpu, vector_cpumask, mask); 138 139 /* 140 * Clear the offline cpus from @vector_cpumask for searching 141 * and verify whether the result overlaps with @mask. If true, 142 * then the call to apic->cpu_mask_to_apicid_and() will 143 * succeed as well. If not, no point in trying to find a 144 * vector in this mask. 145 */ 146 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); 147 if (!cpumask_intersects(vector_searchmask, mask)) 148 goto next_cpu; 149 150 if (cpumask_subset(vector_cpumask, d->domain)) { 151 if (cpumask_equal(vector_cpumask, d->domain)) 152 goto success; 153 /* 154 * Mark the cpus which are not longer in the mask for 155 * cleanup. 156 */ 157 cpumask_andnot(d->old_domain, d->domain, vector_cpumask); 158 vector = d->cfg.vector; 159 goto update; 160 } 161 162 vector = current_vector; 163 offset = current_offset; 164next: 165 vector += 16; 166 if (vector >= first_system_vector) { 167 offset = (offset + 1) % 16; 168 vector = FIRST_EXTERNAL_VECTOR + offset; 169 } 170 171 /* If the search wrapped around, try the next cpu */ 172 if (unlikely(current_vector == vector)) 173 goto next_cpu; 174 175 if (test_bit(vector, used_vectors)) 176 goto next; 177 178 for_each_cpu(new_cpu, vector_searchmask) { 179 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) 180 goto next; 181 } 182 /* Found one! */ 183 current_vector = vector; 184 current_offset = offset; 185 /* Schedule the old vector for cleanup on all cpus */ 186 if (d->cfg.vector) 187 cpumask_copy(d->old_domain, d->domain); 188 for_each_cpu(new_cpu, vector_searchmask) 189 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); 190 goto update; 191 192next_cpu: 193 /* 194 * We exclude the current @vector_cpumask from the requested 195 * @mask and try again with the next online cpu in the 196 * result. We cannot modify @mask, so we use @vector_cpumask 197 * as a temporary buffer here as it will be reassigned when 198 * calling apic->vector_allocation_domain() above. 199 */ 200 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); 201 cpumask_andnot(vector_cpumask, mask, searched_cpumask); 202 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); 203 continue; 204 } 205 return -ENOSPC; 206 207update: 208 /* 209 * Exclude offline cpus from the cleanup mask and set the 210 * move_in_progress flag when the result is not empty. 211 */ 212 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); 213 d->move_in_progress = !cpumask_empty(d->old_domain); 214 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; 215 d->cfg.vector = vector; 216 cpumask_copy(d->domain, vector_cpumask); 217success: 218 /* 219 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail 220 * as we already established, that mask & d->domain & cpu_online_mask 221 * is not empty. 222 */ 223 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain, 224 &d->cfg.dest_apicid)); 225 return 0; 226} 227 228static int assign_irq_vector(int irq, struct apic_chip_data *data, 229 const struct cpumask *mask) 230{ 231 int err; 232 unsigned long flags; 233 234 raw_spin_lock_irqsave(&vector_lock, flags); 235 err = __assign_irq_vector(irq, data, mask); 236 raw_spin_unlock_irqrestore(&vector_lock, flags); 237 return err; 238} 239 240static int assign_irq_vector_policy(int irq, int node, 241 struct apic_chip_data *data, 242 struct irq_alloc_info *info) 243{ 244 if (info && info->mask) 245 return assign_irq_vector(irq, data, info->mask); 246 if (node != NUMA_NO_NODE && 247 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) 248 return 0; 249 return assign_irq_vector(irq, data, apic->target_cpus()); 250} 251 252static void clear_irq_vector(int irq, struct apic_chip_data *data) 253{ 254 struct irq_desc *desc; 255 int cpu, vector; 256 257 if (!data->cfg.vector) 258 return; 259 260 vector = data->cfg.vector; 261 for_each_cpu_and(cpu, data->domain, cpu_online_mask) 262 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 263 264 data->cfg.vector = 0; 265 cpumask_clear(data->domain); 266 267 /* 268 * If move is in progress or the old_domain mask is not empty, 269 * i.e. the cleanup IPI has not been processed yet, we need to remove 270 * the old references to desc from all cpus vector tables. 271 */ 272 if (!data->move_in_progress && cpumask_empty(data->old_domain)) 273 return; 274 275 desc = irq_to_desc(irq); 276 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { 277 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 278 vector++) { 279 if (per_cpu(vector_irq, cpu)[vector] != desc) 280 continue; 281 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 282 break; 283 } 284 } 285 data->move_in_progress = 0; 286} 287 288void init_irq_alloc_info(struct irq_alloc_info *info, 289 const struct cpumask *mask) 290{ 291 memset(info, 0, sizeof(*info)); 292 info->mask = mask; 293} 294 295void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 296{ 297 if (src) 298 *dst = *src; 299 else 300 memset(dst, 0, sizeof(*dst)); 301} 302 303static void x86_vector_free_irqs(struct irq_domain *domain, 304 unsigned int virq, unsigned int nr_irqs) 305{ 306 struct apic_chip_data *apic_data; 307 struct irq_data *irq_data; 308 unsigned long flags; 309 int i; 310 311 for (i = 0; i < nr_irqs; i++) { 312 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); 313 if (irq_data && irq_data->chip_data) { 314 raw_spin_lock_irqsave(&vector_lock, flags); 315 clear_irq_vector(virq + i, irq_data->chip_data); 316 apic_data = irq_data->chip_data; 317 irq_domain_reset_irq_data(irq_data); 318 raw_spin_unlock_irqrestore(&vector_lock, flags); 319 free_apic_chip_data(apic_data); 320#ifdef CONFIG_X86_IO_APIC 321 if (virq + i < nr_legacy_irqs()) 322 legacy_irq_data[virq + i] = NULL; 323#endif 324 } 325 } 326} 327 328static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 329 unsigned int nr_irqs, void *arg) 330{ 331 struct irq_alloc_info *info = arg; 332 struct apic_chip_data *data; 333 struct irq_data *irq_data; 334 int i, err, node; 335 336 if (disable_apic) 337 return -ENXIO; 338 339 /* Currently vector allocator can't guarantee contiguous allocations */ 340 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 341 return -ENOSYS; 342 343 for (i = 0; i < nr_irqs; i++) { 344 irq_data = irq_domain_get_irq_data(domain, virq + i); 345 BUG_ON(!irq_data); 346 node = irq_data_get_node(irq_data); 347#ifdef CONFIG_X86_IO_APIC 348 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) 349 data = legacy_irq_data[virq + i]; 350 else 351#endif 352 data = alloc_apic_chip_data(node); 353 if (!data) { 354 err = -ENOMEM; 355 goto error; 356 } 357 358 irq_data->chip = &lapic_controller; 359 irq_data->chip_data = data; 360 irq_data->hwirq = virq + i; 361 err = assign_irq_vector_policy(virq + i, node, data, info); 362 if (err) 363 goto error; 364 } 365 366 return 0; 367 368error: 369 x86_vector_free_irqs(domain, virq, i + 1); 370 return err; 371} 372 373static const struct irq_domain_ops x86_vector_domain_ops = { 374 .alloc = x86_vector_alloc_irqs, 375 .free = x86_vector_free_irqs, 376}; 377 378int __init arch_probe_nr_irqs(void) 379{ 380 int nr; 381 382 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 383 nr_irqs = NR_VECTORS * nr_cpu_ids; 384 385 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 386#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 387 /* 388 * for MSI and HT dyn irq 389 */ 390 if (gsi_top <= NR_IRQS_LEGACY) 391 nr += 8 * nr_cpu_ids; 392 else 393 nr += gsi_top * 16; 394#endif 395 if (nr < nr_irqs) 396 nr_irqs = nr; 397 398 /* 399 * We don't know if PIC is present at this point so we need to do 400 * probe() to get the right number of legacy IRQs. 401 */ 402 return legacy_pic->probe(); 403} 404 405#ifdef CONFIG_X86_IO_APIC 406static void init_legacy_irqs(void) 407{ 408 int i, node = cpu_to_node(0); 409 struct apic_chip_data *data; 410 411 /* 412 * For legacy IRQ's, start with assigning irq0 to irq15 to 413 * ISA_IRQ_VECTOR(i) for all cpu's. 414 */ 415 for (i = 0; i < nr_legacy_irqs(); i++) { 416 data = legacy_irq_data[i] = alloc_apic_chip_data(node); 417 BUG_ON(!data); 418 419 data->cfg.vector = ISA_IRQ_VECTOR(i); 420 cpumask_setall(data->domain); 421 irq_set_chip_data(i, data); 422 } 423} 424#else 425static void init_legacy_irqs(void) { } 426#endif 427 428int __init arch_early_irq_init(void) 429{ 430 init_legacy_irqs(); 431 432 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, 433 NULL); 434 BUG_ON(x86_vector_domain == NULL); 435 irq_set_default_host(x86_vector_domain); 436 437 arch_init_msi_domain(x86_vector_domain); 438 arch_init_htirq_domain(x86_vector_domain); 439 440 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); 441 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); 442 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); 443 444 return arch_early_ioapic_init(); 445} 446 447/* Initialize vector_irq on a new cpu */ 448static void __setup_vector_irq(int cpu) 449{ 450 struct apic_chip_data *data; 451 struct irq_desc *desc; 452 int irq, vector; 453 454 /* Mark the inuse vectors */ 455 for_each_irq_desc(irq, desc) { 456 struct irq_data *idata = irq_desc_get_irq_data(desc); 457 458 data = apic_chip_data(idata); 459 if (!data || !cpumask_test_cpu(cpu, data->domain)) 460 continue; 461 vector = data->cfg.vector; 462 per_cpu(vector_irq, cpu)[vector] = desc; 463 } 464 /* Mark the free vectors */ 465 for (vector = 0; vector < NR_VECTORS; ++vector) { 466 desc = per_cpu(vector_irq, cpu)[vector]; 467 if (IS_ERR_OR_NULL(desc)) 468 continue; 469 470 data = apic_chip_data(irq_desc_get_irq_data(desc)); 471 if (!cpumask_test_cpu(cpu, data->domain)) 472 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 473 } 474} 475 476/* 477 * Setup the vector to irq mappings. Must be called with vector_lock held. 478 */ 479void setup_vector_irq(int cpu) 480{ 481 int irq; 482 483 lockdep_assert_held(&vector_lock); 484 /* 485 * On most of the platforms, legacy PIC delivers the interrupts on the 486 * boot cpu. But there are certain platforms where PIC interrupts are 487 * delivered to multiple cpu's. If the legacy IRQ is handled by the 488 * legacy PIC, for the new cpu that is coming online, setup the static 489 * legacy vector to irq mapping: 490 */ 491 for (irq = 0; irq < nr_legacy_irqs(); irq++) 492 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); 493 494 __setup_vector_irq(cpu); 495} 496 497static int apic_retrigger_irq(struct irq_data *irq_data) 498{ 499 struct apic_chip_data *data = apic_chip_data(irq_data); 500 unsigned long flags; 501 int cpu; 502 503 raw_spin_lock_irqsave(&vector_lock, flags); 504 cpu = cpumask_first_and(data->domain, cpu_online_mask); 505 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); 506 raw_spin_unlock_irqrestore(&vector_lock, flags); 507 508 return 1; 509} 510 511void apic_ack_edge(struct irq_data *data) 512{ 513 irq_complete_move(irqd_cfg(data)); 514 irq_move_irq(data); 515 ack_APIC_irq(); 516} 517 518static int apic_set_affinity(struct irq_data *irq_data, 519 const struct cpumask *dest, bool force) 520{ 521 struct apic_chip_data *data = irq_data->chip_data; 522 int err, irq = irq_data->irq; 523 524 if (!config_enabled(CONFIG_SMP)) 525 return -EPERM; 526 527 if (!cpumask_intersects(dest, cpu_online_mask)) 528 return -EINVAL; 529 530 err = assign_irq_vector(irq, data, dest); 531 return err ? err : IRQ_SET_MASK_OK; 532} 533 534static struct irq_chip lapic_controller = { 535 .irq_ack = apic_ack_edge, 536 .irq_set_affinity = apic_set_affinity, 537 .irq_retrigger = apic_retrigger_irq, 538}; 539 540#ifdef CONFIG_SMP 541static void __send_cleanup_vector(struct apic_chip_data *data) 542{ 543 raw_spin_lock(&vector_lock); 544 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); 545 data->move_in_progress = 0; 546 if (!cpumask_empty(data->old_domain)) 547 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR); 548 raw_spin_unlock(&vector_lock); 549} 550 551void send_cleanup_vector(struct irq_cfg *cfg) 552{ 553 struct apic_chip_data *data; 554 555 data = container_of(cfg, struct apic_chip_data, cfg); 556 if (data->move_in_progress) 557 __send_cleanup_vector(data); 558} 559 560asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) 561{ 562 unsigned vector, me; 563 564 entering_ack_irq(); 565 566 /* Prevent vectors vanishing under us */ 567 raw_spin_lock(&vector_lock); 568 569 me = smp_processor_id(); 570 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 571 struct apic_chip_data *data; 572 struct irq_desc *desc; 573 unsigned int irr; 574 575 retry: 576 desc = __this_cpu_read(vector_irq[vector]); 577 if (IS_ERR_OR_NULL(desc)) 578 continue; 579 580 if (!raw_spin_trylock(&desc->lock)) { 581 raw_spin_unlock(&vector_lock); 582 cpu_relax(); 583 raw_spin_lock(&vector_lock); 584 goto retry; 585 } 586 587 data = apic_chip_data(irq_desc_get_irq_data(desc)); 588 if (!data) 589 goto unlock; 590 591 /* 592 * Nothing to cleanup if irq migration is in progress 593 * or this cpu is not set in the cleanup mask. 594 */ 595 if (data->move_in_progress || 596 !cpumask_test_cpu(me, data->old_domain)) 597 goto unlock; 598 599 /* 600 * We have two cases to handle here: 601 * 1) vector is unchanged but the target mask got reduced 602 * 2) vector and the target mask has changed 603 * 604 * #1 is obvious, but in #2 we have two vectors with the same 605 * irq descriptor: the old and the new vector. So we need to 606 * make sure that we only cleanup the old vector. The new 607 * vector has the current @vector number in the config and 608 * this cpu is part of the target mask. We better leave that 609 * one alone. 610 */ 611 if (vector == data->cfg.vector && 612 cpumask_test_cpu(me, data->domain)) 613 goto unlock; 614 615 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 616 /* 617 * Check if the vector that needs to be cleanedup is 618 * registered at the cpu's IRR. If so, then this is not 619 * the best time to clean it up. Lets clean it up in the 620 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 621 * to myself. 622 */ 623 if (irr & (1 << (vector % 32))) { 624 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 625 goto unlock; 626 } 627 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); 628 cpumask_clear_cpu(me, data->old_domain); 629unlock: 630 raw_spin_unlock(&desc->lock); 631 } 632 633 raw_spin_unlock(&vector_lock); 634 635 exiting_irq(); 636} 637 638static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 639{ 640 unsigned me; 641 struct apic_chip_data *data; 642 643 data = container_of(cfg, struct apic_chip_data, cfg); 644 if (likely(!data->move_in_progress)) 645 return; 646 647 me = smp_processor_id(); 648 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) 649 __send_cleanup_vector(data); 650} 651 652void irq_complete_move(struct irq_cfg *cfg) 653{ 654 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 655} 656 657/* 658 * Called from fixup_irqs() with @desc->lock held and interrupts disabled. 659 */ 660void irq_force_complete_move(struct irq_desc *desc) 661{ 662 struct irq_data *irqdata = irq_desc_get_irq_data(desc); 663 struct apic_chip_data *data = apic_chip_data(irqdata); 664 struct irq_cfg *cfg = data ? &data->cfg : NULL; 665 unsigned int cpu; 666 667 if (!cfg) 668 return; 669 670 /* 671 * This is tricky. If the cleanup of @data->old_domain has not been 672 * done yet, then the following setaffinity call will fail with 673 * -EBUSY. This can leave the interrupt in a stale state. 674 * 675 * All CPUs are stuck in stop machine with interrupts disabled so 676 * calling __irq_complete_move() would be completely pointless. 677 */ 678 raw_spin_lock(&vector_lock); 679 /* 680 * Clean out all offline cpus (including the outgoing one) from the 681 * old_domain mask. 682 */ 683 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); 684 685 /* 686 * If move_in_progress is cleared and the old_domain mask is empty, 687 * then there is nothing to cleanup. fixup_irqs() will take care of 688 * the stale vectors on the outgoing cpu. 689 */ 690 if (!data->move_in_progress && cpumask_empty(data->old_domain)) { 691 raw_spin_unlock(&vector_lock); 692 return; 693 } 694 695 /* 696 * 1) The interrupt is in move_in_progress state. That means that we 697 * have not seen an interrupt since the io_apic was reprogrammed to 698 * the new vector. 699 * 700 * 2) The interrupt has fired on the new vector, but the cleanup IPIs 701 * have not been processed yet. 702 */ 703 if (data->move_in_progress) { 704 /* 705 * In theory there is a race: 706 * 707 * set_ioapic(new_vector) <-- Interrupt is raised before update 708 * is effective, i.e. it's raised on 709 * the old vector. 710 * 711 * So if the target cpu cannot handle that interrupt before 712 * the old vector is cleaned up, we get a spurious interrupt 713 * and in the worst case the ioapic irq line becomes stale. 714 * 715 * But in case of cpu hotplug this should be a non issue 716 * because if the affinity update happens right before all 717 * cpus rendevouz in stop machine, there is no way that the 718 * interrupt can be blocked on the target cpu because all cpus 719 * loops first with interrupts enabled in stop machine, so the 720 * old vector is not yet cleaned up when the interrupt fires. 721 * 722 * So the only way to run into this issue is if the delivery 723 * of the interrupt on the apic/system bus would be delayed 724 * beyond the point where the target cpu disables interrupts 725 * in stop machine. I doubt that it can happen, but at least 726 * there is a theroretical chance. Virtualization might be 727 * able to expose this, but AFAICT the IOAPIC emulation is not 728 * as stupid as the real hardware. 729 * 730 * Anyway, there is nothing we can do about that at this point 731 * w/o refactoring the whole fixup_irq() business completely. 732 * We print at least the irq number and the old vector number, 733 * so we have the necessary information when a problem in that 734 * area arises. 735 */ 736 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", 737 irqdata->irq, cfg->old_vector); 738 } 739 /* 740 * If old_domain is not empty, then other cpus still have the irq 741 * descriptor set in their vector array. Clean it up. 742 */ 743 for_each_cpu(cpu, data->old_domain) 744 per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED; 745 746 /* Cleanup the left overs of the (half finished) move */ 747 cpumask_clear(data->old_domain); 748 data->move_in_progress = 0; 749 raw_spin_unlock(&vector_lock); 750} 751#endif 752 753static void __init print_APIC_field(int base) 754{ 755 int i; 756 757 printk(KERN_DEBUG); 758 759 for (i = 0; i < 8; i++) 760 pr_cont("%08x", apic_read(base + i*0x10)); 761 762 pr_cont("\n"); 763} 764 765static void __init print_local_APIC(void *dummy) 766{ 767 unsigned int i, v, ver, maxlvt; 768 u64 icr; 769 770 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 771 smp_processor_id(), hard_smp_processor_id()); 772 v = apic_read(APIC_ID); 773 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 774 v = apic_read(APIC_LVR); 775 pr_info("... APIC VERSION: %08x\n", v); 776 ver = GET_APIC_VERSION(v); 777 maxlvt = lapic_get_maxlvt(); 778 779 v = apic_read(APIC_TASKPRI); 780 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 781 782 /* !82489DX */ 783 if (APIC_INTEGRATED(ver)) { 784 if (!APIC_XAPIC(ver)) { 785 v = apic_read(APIC_ARBPRI); 786 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 787 v, v & APIC_ARBPRI_MASK); 788 } 789 v = apic_read(APIC_PROCPRI); 790 pr_debug("... APIC PROCPRI: %08x\n", v); 791 } 792 793 /* 794 * Remote read supported only in the 82489DX and local APIC for 795 * Pentium processors. 796 */ 797 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 798 v = apic_read(APIC_RRR); 799 pr_debug("... APIC RRR: %08x\n", v); 800 } 801 802 v = apic_read(APIC_LDR); 803 pr_debug("... APIC LDR: %08x\n", v); 804 if (!x2apic_enabled()) { 805 v = apic_read(APIC_DFR); 806 pr_debug("... APIC DFR: %08x\n", v); 807 } 808 v = apic_read(APIC_SPIV); 809 pr_debug("... APIC SPIV: %08x\n", v); 810 811 pr_debug("... APIC ISR field:\n"); 812 print_APIC_field(APIC_ISR); 813 pr_debug("... APIC TMR field:\n"); 814 print_APIC_field(APIC_TMR); 815 pr_debug("... APIC IRR field:\n"); 816 print_APIC_field(APIC_IRR); 817 818 /* !82489DX */ 819 if (APIC_INTEGRATED(ver)) { 820 /* Due to the Pentium erratum 3AP. */ 821 if (maxlvt > 3) 822 apic_write(APIC_ESR, 0); 823 824 v = apic_read(APIC_ESR); 825 pr_debug("... APIC ESR: %08x\n", v); 826 } 827 828 icr = apic_icr_read(); 829 pr_debug("... APIC ICR: %08x\n", (u32)icr); 830 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 831 832 v = apic_read(APIC_LVTT); 833 pr_debug("... APIC LVTT: %08x\n", v); 834 835 if (maxlvt > 3) { 836 /* PC is LVT#4. */ 837 v = apic_read(APIC_LVTPC); 838 pr_debug("... APIC LVTPC: %08x\n", v); 839 } 840 v = apic_read(APIC_LVT0); 841 pr_debug("... APIC LVT0: %08x\n", v); 842 v = apic_read(APIC_LVT1); 843 pr_debug("... APIC LVT1: %08x\n", v); 844 845 if (maxlvt > 2) { 846 /* ERR is LVT#3. */ 847 v = apic_read(APIC_LVTERR); 848 pr_debug("... APIC LVTERR: %08x\n", v); 849 } 850 851 v = apic_read(APIC_TMICT); 852 pr_debug("... APIC TMICT: %08x\n", v); 853 v = apic_read(APIC_TMCCT); 854 pr_debug("... APIC TMCCT: %08x\n", v); 855 v = apic_read(APIC_TDCR); 856 pr_debug("... APIC TDCR: %08x\n", v); 857 858 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 859 v = apic_read(APIC_EFEAT); 860 maxlvt = (v >> 16) & 0xff; 861 pr_debug("... APIC EFEAT: %08x\n", v); 862 v = apic_read(APIC_ECTRL); 863 pr_debug("... APIC ECTRL: %08x\n", v); 864 for (i = 0; i < maxlvt; i++) { 865 v = apic_read(APIC_EILVTn(i)); 866 pr_debug("... APIC EILVT%d: %08x\n", i, v); 867 } 868 } 869 pr_cont("\n"); 870} 871 872static void __init print_local_APICs(int maxcpu) 873{ 874 int cpu; 875 876 if (!maxcpu) 877 return; 878 879 preempt_disable(); 880 for_each_online_cpu(cpu) { 881 if (cpu >= maxcpu) 882 break; 883 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 884 } 885 preempt_enable(); 886} 887 888static void __init print_PIC(void) 889{ 890 unsigned int v; 891 unsigned long flags; 892 893 if (!nr_legacy_irqs()) 894 return; 895 896 pr_debug("\nprinting PIC contents\n"); 897 898 raw_spin_lock_irqsave(&i8259A_lock, flags); 899 900 v = inb(0xa1) << 8 | inb(0x21); 901 pr_debug("... PIC IMR: %04x\n", v); 902 903 v = inb(0xa0) << 8 | inb(0x20); 904 pr_debug("... PIC IRR: %04x\n", v); 905 906 outb(0x0b, 0xa0); 907 outb(0x0b, 0x20); 908 v = inb(0xa0) << 8 | inb(0x20); 909 outb(0x0a, 0xa0); 910 outb(0x0a, 0x20); 911 912 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 913 914 pr_debug("... PIC ISR: %04x\n", v); 915 916 v = inb(0x4d1) << 8 | inb(0x4d0); 917 pr_debug("... PIC ELCR: %04x\n", v); 918} 919 920static int show_lapic __initdata = 1; 921static __init int setup_show_lapic(char *arg) 922{ 923 int num = -1; 924 925 if (strcmp(arg, "all") == 0) { 926 show_lapic = CONFIG_NR_CPUS; 927 } else { 928 get_option(&arg, &num); 929 if (num >= 0) 930 show_lapic = num; 931 } 932 933 return 1; 934} 935__setup("show_lapic=", setup_show_lapic); 936 937static int __init print_ICs(void) 938{ 939 if (apic_verbosity == APIC_QUIET) 940 return 0; 941 942 print_PIC(); 943 944 /* don't print out if apic is not there */ 945 if (!cpu_has_apic && !apic_from_smp_config()) 946 return 0; 947 948 print_local_APICs(show_lapic); 949 print_IO_APICs(); 950 951 return 0; 952} 953 954late_initcall(print_ICs); 955