1/*
2 * apb_timer.c: Driver for Langwell APB timers
3 *
4 * (C) Copyright 2009 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * Note:
13 * Langwell is the south complex of Intel Moorestown MID platform. There are
14 * eight external timers in total that can be used by the operating system.
15 * The timer information, such as frequency and addresses, is provided to the
16 * OS via SFI tables.
17 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
18 * individual redirection table entries (RTE).
19 * Unlike HPET, there is no master counter, therefore one of the timers are
20 * used as clocksource. The overall allocation looks like:
21 *  - timer 0 - NR_CPUs for per cpu timer
22 *  - one timer for clocksource
23 *  - one timer for watchdog driver.
24 * It is also worth notice that APB timer does not support true one-shot mode,
25 * free-running mode will be used here to emulate one-shot mode.
26 * APB timer can also be used as broadcast timer along with per cpu local APIC
27 * timer, but by default APB timer has higher rating than local APIC timers.
28 */
29
30#include <linux/delay.h>
31#include <linux/dw_apb_timer.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/slab.h>
35#include <linux/pm.h>
36#include <linux/sfi.h>
37#include <linux/interrupt.h>
38#include <linux/cpu.h>
39#include <linux/irq.h>
40
41#include <asm/fixmap.h>
42#include <asm/apb_timer.h>
43#include <asm/intel-mid.h>
44#include <asm/time.h>
45
46#define APBT_CLOCKEVENT_RATING		110
47#define APBT_CLOCKSOURCE_RATING		250
48
49#define APBT_CLOCKEVENT0_NUM   (0)
50#define APBT_CLOCKSOURCE_NUM   (2)
51
52static phys_addr_t apbt_address;
53static int apb_timer_block_enabled;
54static void __iomem *apbt_virt_address;
55
56/*
57 * Common DW APB timer info
58 */
59static unsigned long apbt_freq;
60
61struct apbt_dev {
62	struct dw_apb_clock_event_device	*timer;
63	unsigned int				num;
64	int					cpu;
65	unsigned int				irq;
66	char					name[10];
67};
68
69static struct dw_apb_clocksource *clocksource_apbt;
70
71static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
72{
73	return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
74}
75
76static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
77
78#ifdef CONFIG_SMP
79static unsigned int apbt_num_timers_used;
80#endif
81
82static inline void apbt_set_mapping(void)
83{
84	struct sfi_timer_table_entry *mtmr;
85	int phy_cs_timer_id = 0;
86
87	if (apbt_virt_address) {
88		pr_debug("APBT base already mapped\n");
89		return;
90	}
91	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
92	if (mtmr == NULL) {
93		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
94		       APBT_CLOCKEVENT0_NUM);
95		return;
96	}
97	apbt_address = (phys_addr_t)mtmr->phys_addr;
98	if (!apbt_address) {
99		printk(KERN_WARNING "No timer base from SFI, use default\n");
100		apbt_address = APBT_DEFAULT_BASE;
101	}
102	apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
103	if (!apbt_virt_address) {
104		pr_debug("Failed mapping APBT phy address at %lu\n",\
105			 (unsigned long)apbt_address);
106		goto panic_noapbt;
107	}
108	apbt_freq = mtmr->freq_hz;
109	sfi_free_mtmr(mtmr);
110
111	/* Now figure out the physical timer id for clocksource device */
112	mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
113	if (mtmr == NULL)
114		goto panic_noapbt;
115
116	/* Now figure out the physical timer id */
117	pr_debug("Use timer %d for clocksource\n",
118		 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
119	phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
120		APBTMRS_REG_SIZE;
121
122	clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
123		"apbt0", apbt_virt_address + phy_cs_timer_id *
124		APBTMRS_REG_SIZE, apbt_freq);
125	return;
126
127panic_noapbt:
128	panic("Failed to setup APB system timer\n");
129
130}
131
132static inline void apbt_clear_mapping(void)
133{
134	iounmap(apbt_virt_address);
135	apbt_virt_address = NULL;
136}
137
138static int __init apbt_clockevent_register(void)
139{
140	struct sfi_timer_table_entry *mtmr;
141	struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
142
143	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
144	if (mtmr == NULL) {
145		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
146		       APBT_CLOCKEVENT0_NUM);
147		return -ENODEV;
148	}
149
150	adev->num = smp_processor_id();
151	adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
152		intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
153		APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
154		adev_virt_addr(adev), 0, apbt_freq);
155	/* Firmware does EOI handling for us. */
156	adev->timer->eoi = NULL;
157
158	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
159		global_clock_event = &adev->timer->ced;
160		printk(KERN_DEBUG "%s clockevent registered as global\n",
161		       global_clock_event->name);
162	}
163
164	dw_apb_clockevent_register(adev->timer);
165
166	sfi_free_mtmr(mtmr);
167	return 0;
168}
169
170#ifdef CONFIG_SMP
171
172static void apbt_setup_irq(struct apbt_dev *adev)
173{
174	irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
175	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
176}
177
178/* Should be called with per cpu */
179void apbt_setup_secondary_clock(void)
180{
181	struct apbt_dev *adev;
182	int cpu;
183
184	/* Don't register boot CPU clockevent */
185	cpu = smp_processor_id();
186	if (!cpu)
187		return;
188
189	adev = this_cpu_ptr(&cpu_apbt_dev);
190	if (!adev->timer) {
191		adev->timer = dw_apb_clockevent_init(cpu, adev->name,
192			APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
193			adev->irq, apbt_freq);
194		adev->timer->eoi = NULL;
195	} else {
196		dw_apb_clockevent_resume(adev->timer);
197	}
198
199	printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
200	       cpu, adev->name, adev->cpu);
201
202	apbt_setup_irq(adev);
203	dw_apb_clockevent_register(adev->timer);
204
205	return;
206}
207
208/*
209 * this notify handler process CPU hotplug events. in case of S0i3, nonboot
210 * cpus are disabled/enabled frequently, for performance reasons, we keep the
211 * per cpu timer irq registered so that we do need to do free_irq/request_irq.
212 *
213 * TODO: it might be more reliable to directly disable percpu clockevent device
214 * without the notifier chain. currently, cpu 0 may get interrupts from other
215 * cpu timers during the offline process due to the ordering of notification.
216 * the extra interrupt is harmless.
217 */
218static int apbt_cpuhp_notify(struct notifier_block *n,
219			     unsigned long action, void *hcpu)
220{
221	unsigned long cpu = (unsigned long)hcpu;
222	struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
223
224	switch (action & 0xf) {
225	case CPU_DEAD:
226		dw_apb_clockevent_pause(adev->timer);
227		if (system_state == SYSTEM_RUNNING) {
228			pr_debug("skipping APBT CPU %lu offline\n", cpu);
229		} else {
230			pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
231			dw_apb_clockevent_stop(adev->timer);
232		}
233		break;
234	default:
235		pr_debug("APBT notified %lu, no action\n", action);
236	}
237	return NOTIFY_OK;
238}
239
240static __init int apbt_late_init(void)
241{
242	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
243		!apb_timer_block_enabled)
244		return 0;
245	/* This notifier should be called after workqueue is ready */
246	hotcpu_notifier(apbt_cpuhp_notify, -20);
247	return 0;
248}
249fs_initcall(apbt_late_init);
250#else
251
252void apbt_setup_secondary_clock(void) {}
253
254#endif /* CONFIG_SMP */
255
256static int apbt_clocksource_register(void)
257{
258	u64 start, now;
259	cycle_t t1;
260
261	/* Start the counter, use timer 2 as source, timer 0/1 for event */
262	dw_apb_clocksource_start(clocksource_apbt);
263
264	/* Verify whether apbt counter works */
265	t1 = dw_apb_clocksource_read(clocksource_apbt);
266	start = rdtsc();
267
268	/*
269	 * We don't know the TSC frequency yet, but waiting for
270	 * 200000 TSC cycles is safe:
271	 * 4 GHz == 50us
272	 * 1 GHz == 200us
273	 */
274	do {
275		rep_nop();
276		now = rdtsc();
277	} while ((now - start) < 200000UL);
278
279	/* APBT is the only always on clocksource, it has to work! */
280	if (t1 == dw_apb_clocksource_read(clocksource_apbt))
281		panic("APBT counter not counting. APBT disabled\n");
282
283	dw_apb_clocksource_register(clocksource_apbt);
284
285	return 0;
286}
287
288/*
289 * Early setup the APBT timer, only use timer 0 for booting then switch to
290 * per CPU timer if possible.
291 * returns 1 if per cpu apbt is setup
292 * returns 0 if no per cpu apbt is chosen
293 * panic if set up failed, this is the only platform timer on Moorestown.
294 */
295void __init apbt_time_init(void)
296{
297#ifdef CONFIG_SMP
298	int i;
299	struct sfi_timer_table_entry *p_mtmr;
300	struct apbt_dev *adev;
301#endif
302
303	if (apb_timer_block_enabled)
304		return;
305	apbt_set_mapping();
306	if (!apbt_virt_address)
307		goto out_noapbt;
308	/*
309	 * Read the frequency and check for a sane value, for ESL model
310	 * we extend the possible clock range to allow time scaling.
311	 */
312
313	if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
314		pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
315		goto out_noapbt;
316	}
317	if (apbt_clocksource_register()) {
318		pr_debug("APBT has failed to register clocksource\n");
319		goto out_noapbt;
320	}
321	if (!apbt_clockevent_register())
322		apb_timer_block_enabled = 1;
323	else {
324		pr_debug("APBT has failed to register clockevent\n");
325		goto out_noapbt;
326	}
327#ifdef CONFIG_SMP
328	/* kernel cmdline disable apb timer, so we will use lapic timers */
329	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
330		printk(KERN_INFO "apbt: disabled per cpu timer\n");
331		return;
332	}
333	pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
334	if (num_possible_cpus() <= sfi_mtimer_num)
335		apbt_num_timers_used = num_possible_cpus();
336	else
337		apbt_num_timers_used = 1;
338	pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
339
340	/* here we set up per CPU timer data structure */
341	for (i = 0; i < apbt_num_timers_used; i++) {
342		adev = &per_cpu(cpu_apbt_dev, i);
343		adev->num = i;
344		adev->cpu = i;
345		p_mtmr = sfi_get_mtmr(i);
346		if (p_mtmr)
347			adev->irq = p_mtmr->irq;
348		else
349			printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
350		snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
351	}
352#endif
353
354	return;
355
356out_noapbt:
357	apbt_clear_mapping();
358	apb_timer_block_enabled = 0;
359	panic("failed to enable APB timer\n");
360}
361
362/* called before apb_timer_enable, use early map */
363unsigned long apbt_quick_calibrate(void)
364{
365	int i, scale;
366	u64 old, new;
367	cycle_t t1, t2;
368	unsigned long khz = 0;
369	u32 loop, shift;
370
371	apbt_set_mapping();
372	dw_apb_clocksource_start(clocksource_apbt);
373
374	/* check if the timer can count down, otherwise return */
375	old = dw_apb_clocksource_read(clocksource_apbt);
376	i = 10000;
377	while (--i) {
378		if (old != dw_apb_clocksource_read(clocksource_apbt))
379			break;
380	}
381	if (!i)
382		goto failed;
383
384	/* count 16 ms */
385	loop = (apbt_freq / 1000) << 4;
386
387	/* restart the timer to ensure it won't get to 0 in the calibration */
388	dw_apb_clocksource_start(clocksource_apbt);
389
390	old = dw_apb_clocksource_read(clocksource_apbt);
391	old += loop;
392
393	t1 = rdtsc();
394
395	do {
396		new = dw_apb_clocksource_read(clocksource_apbt);
397	} while (new < old);
398
399	t2 = rdtsc();
400
401	shift = 5;
402	if (unlikely(loop >> shift == 0)) {
403		printk(KERN_INFO
404		       "APBT TSC calibration failed, not enough resolution\n");
405		return 0;
406	}
407	scale = (int)div_u64((t2 - t1), loop >> shift);
408	khz = (scale * (apbt_freq / 1000)) >> shift;
409	printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
410	return khz;
411failed:
412	return 0;
413}
414