1/* 2 * Copyright 2013 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/* Machine-generated file; do not edit. */ 16 17#ifndef __ARCH_UART_DEF_H__ 18#define __ARCH_UART_DEF_H__ 19#define UART_DIVISOR 0x0158 20#define UART_FIFO_COUNT 0x0110 21#define UART_FLAG 0x0108 22#define UART_INTERRUPT_MASK 0x0208 23#define UART_INTERRUPT_MASK__RDAT_ERR_SHIFT 0 24#define UART_INTERRUPT_MASK__RDAT_ERR_WIDTH 1 25#define UART_INTERRUPT_MASK__RDAT_ERR_RESET_VAL 1 26#define UART_INTERRUPT_MASK__RDAT_ERR_RMASK 0x1 27#define UART_INTERRUPT_MASK__RDAT_ERR_MASK 0x1 28#define UART_INTERRUPT_MASK__RDAT_ERR_FIELD 0,0 29#define UART_INTERRUPT_MASK__WDAT_ERR_SHIFT 1 30#define UART_INTERRUPT_MASK__WDAT_ERR_WIDTH 1 31#define UART_INTERRUPT_MASK__WDAT_ERR_RESET_VAL 1 32#define UART_INTERRUPT_MASK__WDAT_ERR_RMASK 0x1 33#define UART_INTERRUPT_MASK__WDAT_ERR_MASK 0x2 34#define UART_INTERRUPT_MASK__WDAT_ERR_FIELD 1,1 35#define UART_INTERRUPT_MASK__FRAME_ERR_SHIFT 2 36#define UART_INTERRUPT_MASK__FRAME_ERR_WIDTH 1 37#define UART_INTERRUPT_MASK__FRAME_ERR_RESET_VAL 1 38#define UART_INTERRUPT_MASK__FRAME_ERR_RMASK 0x1 39#define UART_INTERRUPT_MASK__FRAME_ERR_MASK 0x4 40#define UART_INTERRUPT_MASK__FRAME_ERR_FIELD 2,2 41#define UART_INTERRUPT_MASK__PARITY_ERR_SHIFT 3 42#define UART_INTERRUPT_MASK__PARITY_ERR_WIDTH 1 43#define UART_INTERRUPT_MASK__PARITY_ERR_RESET_VAL 1 44#define UART_INTERRUPT_MASK__PARITY_ERR_RMASK 0x1 45#define UART_INTERRUPT_MASK__PARITY_ERR_MASK 0x8 46#define UART_INTERRUPT_MASK__PARITY_ERR_FIELD 3,3 47#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_SHIFT 4 48#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_WIDTH 1 49#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RESET_VAL 1 50#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RMASK 0x1 51#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_MASK 0x10 52#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_FIELD 4,4 53#define UART_INTERRUPT_MASK__RFIFO_AFULL_SHIFT 5 54#define UART_INTERRUPT_MASK__RFIFO_AFULL_WIDTH 1 55#define UART_INTERRUPT_MASK__RFIFO_AFULL_RESET_VAL 1 56#define UART_INTERRUPT_MASK__RFIFO_AFULL_RMASK 0x1 57#define UART_INTERRUPT_MASK__RFIFO_AFULL_MASK 0x20 58#define UART_INTERRUPT_MASK__RFIFO_AFULL_FIELD 5,5 59#define UART_INTERRUPT_MASK__TFIFO_RE_SHIFT 7 60#define UART_INTERRUPT_MASK__TFIFO_RE_WIDTH 1 61#define UART_INTERRUPT_MASK__TFIFO_RE_RESET_VAL 1 62#define UART_INTERRUPT_MASK__TFIFO_RE_RMASK 0x1 63#define UART_INTERRUPT_MASK__TFIFO_RE_MASK 0x80 64#define UART_INTERRUPT_MASK__TFIFO_RE_FIELD 7,7 65#define UART_INTERRUPT_MASK__RFIFO_WE_SHIFT 8 66#define UART_INTERRUPT_MASK__RFIFO_WE_WIDTH 1 67#define UART_INTERRUPT_MASK__RFIFO_WE_RESET_VAL 1 68#define UART_INTERRUPT_MASK__RFIFO_WE_RMASK 0x1 69#define UART_INTERRUPT_MASK__RFIFO_WE_MASK 0x100 70#define UART_INTERRUPT_MASK__RFIFO_WE_FIELD 8,8 71#define UART_INTERRUPT_MASK__WFIFO_RE_SHIFT 9 72#define UART_INTERRUPT_MASK__WFIFO_RE_WIDTH 1 73#define UART_INTERRUPT_MASK__WFIFO_RE_RESET_VAL 1 74#define UART_INTERRUPT_MASK__WFIFO_RE_RMASK 0x1 75#define UART_INTERRUPT_MASK__WFIFO_RE_MASK 0x200 76#define UART_INTERRUPT_MASK__WFIFO_RE_FIELD 9,9 77#define UART_INTERRUPT_MASK__RFIFO_ERR_SHIFT 10 78#define UART_INTERRUPT_MASK__RFIFO_ERR_WIDTH 1 79#define UART_INTERRUPT_MASK__RFIFO_ERR_RESET_VAL 1 80#define UART_INTERRUPT_MASK__RFIFO_ERR_RMASK 0x1 81#define UART_INTERRUPT_MASK__RFIFO_ERR_MASK 0x400 82#define UART_INTERRUPT_MASK__RFIFO_ERR_FIELD 10,10 83#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_SHIFT 11 84#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_WIDTH 1 85#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RESET_VAL 1 86#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RMASK 0x1 87#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_MASK 0x800 88#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_FIELD 11,11 89#define UART_INTERRUPT_STATUS 0x0200 90#define UART_RECEIVE_DATA 0x0148 91#define UART_TRANSMIT_DATA 0x0140 92#define UART_TYPE 0x0160 93#define UART_TYPE__SBITS_SHIFT 0 94#define UART_TYPE__SBITS_WIDTH 1 95#define UART_TYPE__SBITS_RESET_VAL 1 96#define UART_TYPE__SBITS_RMASK 0x1 97#define UART_TYPE__SBITS_MASK 0x1 98#define UART_TYPE__SBITS_FIELD 0,0 99#define UART_TYPE__SBITS_VAL_ONE_SBITS 0x0 100#define UART_TYPE__SBITS_VAL_TWO_SBITS 0x1 101#define UART_TYPE__DBITS_SHIFT 2 102#define UART_TYPE__DBITS_WIDTH 1 103#define UART_TYPE__DBITS_RESET_VAL 0 104#define UART_TYPE__DBITS_RMASK 0x1 105#define UART_TYPE__DBITS_MASK 0x4 106#define UART_TYPE__DBITS_FIELD 2,2 107#define UART_TYPE__DBITS_VAL_EIGHT_DBITS 0x0 108#define UART_TYPE__DBITS_VAL_SEVEN_DBITS 0x1 109#define UART_TYPE__PTYPE_SHIFT 4 110#define UART_TYPE__PTYPE_WIDTH 3 111#define UART_TYPE__PTYPE_RESET_VAL 3 112#define UART_TYPE__PTYPE_RMASK 0x7 113#define UART_TYPE__PTYPE_MASK 0x70 114#define UART_TYPE__PTYPE_FIELD 4,6 115#define UART_TYPE__PTYPE_VAL_NONE 0x0 116#define UART_TYPE__PTYPE_VAL_MARK 0x1 117#define UART_TYPE__PTYPE_VAL_SPACE 0x2 118#define UART_TYPE__PTYPE_VAL_EVEN 0x3 119#define UART_TYPE__PTYPE_VAL_ODD 0x4 120#endif /* !defined(__ARCH_UART_DEF_H__) */ 121