1/* pci_common.c: PCI controller common support.
2 *
3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/string.h>
7#include <linux/slab.h>
8#include <linux/pci.h>
9#include <linux/device.h>
10#include <linux/of_device.h>
11
12#include <asm/prom.h>
13#include <asm/oplib.h>
14
15#include "pci_impl.h"
16#include "pci_sun4v.h"
17
18static int config_out_of_range(struct pci_pbm_info *pbm,
19			       unsigned long bus,
20			       unsigned long devfn,
21			       unsigned long reg)
22{
23	if (bus < pbm->pci_first_busno ||
24	    bus > pbm->pci_last_busno)
25		return 1;
26	return 0;
27}
28
29static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
30				 unsigned long bus,
31				 unsigned long devfn,
32				 unsigned long reg)
33{
34	unsigned long rbits = pbm->config_space_reg_bits;
35
36	if (config_out_of_range(pbm, bus, devfn, reg))
37		return NULL;
38
39	reg = (reg & ((1 << rbits) - 1));
40	devfn <<= rbits;
41	bus <<= rbits + 8;
42
43	return (void *)	(pbm->config_space | bus | devfn | reg);
44}
45
46/* At least on Sabre, it is necessary to access all PCI host controller
47 * registers at their natural size, otherwise zeros are returned.
48 * Strange but true, and I see no language in the UltraSPARC-IIi
49 * programmer's manual that mentions this even indirectly.
50 */
51static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
52				   unsigned char bus, unsigned int devfn,
53				   int where, int size, u32 *value)
54{
55	u32 tmp32, *addr;
56	u16 tmp16;
57	u8 tmp8;
58
59	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
60	if (!addr)
61		return PCIBIOS_SUCCESSFUL;
62
63	switch (size) {
64	case 1:
65		if (where < 8) {
66			unsigned long align = (unsigned long) addr;
67
68			align &= ~1;
69			pci_config_read16((u16 *)align, &tmp16);
70			if (where & 1)
71				*value = tmp16 >> 8;
72			else
73				*value = tmp16 & 0xff;
74		} else {
75			pci_config_read8((u8 *)addr, &tmp8);
76			*value = (u32) tmp8;
77		}
78		break;
79
80	case 2:
81		if (where < 8) {
82			pci_config_read16((u16 *)addr, &tmp16);
83			*value = (u32) tmp16;
84		} else {
85			pci_config_read8((u8 *)addr, &tmp8);
86			*value = (u32) tmp8;
87			pci_config_read8(((u8 *)addr) + 1, &tmp8);
88			*value |= ((u32) tmp8) << 8;
89		}
90		break;
91
92	case 4:
93		tmp32 = 0xffffffff;
94		sun4u_read_pci_cfg_host(pbm, bus, devfn,
95					where, 2, &tmp32);
96		*value = tmp32;
97
98		tmp32 = 0xffffffff;
99		sun4u_read_pci_cfg_host(pbm, bus, devfn,
100					where + 2, 2, &tmp32);
101		*value |= tmp32 << 16;
102		break;
103	}
104	return PCIBIOS_SUCCESSFUL;
105}
106
107static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
108			      int where, int size, u32 *value)
109{
110	struct pci_pbm_info *pbm = bus_dev->sysdata;
111	unsigned char bus = bus_dev->number;
112	u32 *addr;
113	u16 tmp16;
114	u8 tmp8;
115
116	switch (size) {
117	case 1:
118		*value = 0xff;
119		break;
120	case 2:
121		*value = 0xffff;
122		break;
123	case 4:
124		*value = 0xffffffff;
125		break;
126	}
127
128	if (!bus_dev->number && !PCI_SLOT(devfn))
129		return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
130					       size, value);
131
132	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
133	if (!addr)
134		return PCIBIOS_SUCCESSFUL;
135
136	switch (size) {
137	case 1:
138		pci_config_read8((u8 *)addr, &tmp8);
139		*value = (u32) tmp8;
140		break;
141
142	case 2:
143		if (where & 0x01) {
144			printk("pci_read_config_word: misaligned reg [%x]\n",
145			       where);
146			return PCIBIOS_SUCCESSFUL;
147		}
148		pci_config_read16((u16 *)addr, &tmp16);
149		*value = (u32) tmp16;
150		break;
151
152	case 4:
153		if (where & 0x03) {
154			printk("pci_read_config_dword: misaligned reg [%x]\n",
155			       where);
156			return PCIBIOS_SUCCESSFUL;
157		}
158		pci_config_read32(addr, value);
159		break;
160	}
161	return PCIBIOS_SUCCESSFUL;
162}
163
164static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
165				    unsigned char bus, unsigned int devfn,
166				    int where, int size, u32 value)
167{
168	u32 *addr;
169
170	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
171	if (!addr)
172		return PCIBIOS_SUCCESSFUL;
173
174	switch (size) {
175	case 1:
176		if (where < 8) {
177			unsigned long align = (unsigned long) addr;
178			u16 tmp16;
179
180			align &= ~1;
181			pci_config_read16((u16 *)align, &tmp16);
182			if (where & 1) {
183				tmp16 &= 0x00ff;
184				tmp16 |= value << 8;
185			} else {
186				tmp16 &= 0xff00;
187				tmp16 |= value;
188			}
189			pci_config_write16((u16 *)align, tmp16);
190		} else
191			pci_config_write8((u8 *)addr, value);
192		break;
193	case 2:
194		if (where < 8) {
195			pci_config_write16((u16 *)addr, value);
196		} else {
197			pci_config_write8((u8 *)addr, value & 0xff);
198			pci_config_write8(((u8 *)addr) + 1, value >> 8);
199		}
200		break;
201	case 4:
202		sun4u_write_pci_cfg_host(pbm, bus, devfn,
203					 where, 2, value & 0xffff);
204		sun4u_write_pci_cfg_host(pbm, bus, devfn,
205					 where + 2, 2, value >> 16);
206		break;
207	}
208	return PCIBIOS_SUCCESSFUL;
209}
210
211static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
212			       int where, int size, u32 value)
213{
214	struct pci_pbm_info *pbm = bus_dev->sysdata;
215	unsigned char bus = bus_dev->number;
216	u32 *addr;
217
218	if (!bus_dev->number && !PCI_SLOT(devfn))
219		return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
220						size, value);
221
222	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
223	if (!addr)
224		return PCIBIOS_SUCCESSFUL;
225
226	switch (size) {
227	case 1:
228		pci_config_write8((u8 *)addr, value);
229		break;
230
231	case 2:
232		if (where & 0x01) {
233			printk("pci_write_config_word: misaligned reg [%x]\n",
234			       where);
235			return PCIBIOS_SUCCESSFUL;
236		}
237		pci_config_write16((u16 *)addr, value);
238		break;
239
240	case 4:
241		if (where & 0x03) {
242			printk("pci_write_config_dword: misaligned reg [%x]\n",
243			       where);
244			return PCIBIOS_SUCCESSFUL;
245		}
246		pci_config_write32(addr, value);
247	}
248	return PCIBIOS_SUCCESSFUL;
249}
250
251struct pci_ops sun4u_pci_ops = {
252	.read =		sun4u_read_pci_cfg,
253	.write =	sun4u_write_pci_cfg,
254};
255
256static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
257			      int where, int size, u32 *value)
258{
259	struct pci_pbm_info *pbm = bus_dev->sysdata;
260	u32 devhandle = pbm->devhandle;
261	unsigned int bus = bus_dev->number;
262	unsigned int device = PCI_SLOT(devfn);
263	unsigned int func = PCI_FUNC(devfn);
264	unsigned long ret;
265
266	if (config_out_of_range(pbm, bus, devfn, where)) {
267		ret = ~0UL;
268	} else {
269		ret = pci_sun4v_config_get(devhandle,
270				HV_PCI_DEVICE_BUILD(bus, device, func),
271				where, size);
272	}
273	switch (size) {
274	case 1:
275		*value = ret & 0xff;
276		break;
277	case 2:
278		*value = ret & 0xffff;
279		break;
280	case 4:
281		*value = ret & 0xffffffff;
282		break;
283	}
284
285
286	return PCIBIOS_SUCCESSFUL;
287}
288
289static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
290			       int where, int size, u32 value)
291{
292	struct pci_pbm_info *pbm = bus_dev->sysdata;
293	u32 devhandle = pbm->devhandle;
294	unsigned int bus = bus_dev->number;
295	unsigned int device = PCI_SLOT(devfn);
296	unsigned int func = PCI_FUNC(devfn);
297
298	if (config_out_of_range(pbm, bus, devfn, where)) {
299		/* Do nothing. */
300	} else {
301		/* We don't check for hypervisor errors here, but perhaps
302		 * we should and influence our return value depending upon
303		 * what kind of error is thrown.
304		 */
305		pci_sun4v_config_put(devhandle,
306				     HV_PCI_DEVICE_BUILD(bus, device, func),
307				     where, size, value);
308	}
309	return PCIBIOS_SUCCESSFUL;
310}
311
312struct pci_ops sun4v_pci_ops = {
313	.read =		sun4v_read_pci_cfg,
314	.write =	sun4v_write_pci_cfg,
315};
316
317void pci_get_pbm_props(struct pci_pbm_info *pbm)
318{
319	const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
320
321	pbm->pci_first_busno = val[0];
322	pbm->pci_last_busno = val[1];
323
324	val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
325	if (val) {
326		pbm->ino_bitmap = (((u64)val[1] << 32UL) |
327				   ((u64)val[0] <<  0UL));
328	}
329}
330
331static void pci_register_legacy_regions(struct resource *io_res,
332					struct resource *mem_res)
333{
334	struct resource *p;
335
336	/* VGA Video RAM. */
337	p = kzalloc(sizeof(*p), GFP_KERNEL);
338	if (!p)
339		return;
340
341	p->name = "Video RAM area";
342	p->start = mem_res->start + 0xa0000UL;
343	p->end = p->start + 0x1ffffUL;
344	p->flags = IORESOURCE_BUSY;
345	request_resource(mem_res, p);
346
347	p = kzalloc(sizeof(*p), GFP_KERNEL);
348	if (!p)
349		return;
350
351	p->name = "System ROM";
352	p->start = mem_res->start + 0xf0000UL;
353	p->end = p->start + 0xffffUL;
354	p->flags = IORESOURCE_BUSY;
355	request_resource(mem_res, p);
356
357	p = kzalloc(sizeof(*p), GFP_KERNEL);
358	if (!p)
359		return;
360
361	p->name = "Video ROM";
362	p->start = mem_res->start + 0xc0000UL;
363	p->end = p->start + 0x7fffUL;
364	p->flags = IORESOURCE_BUSY;
365	request_resource(mem_res, p);
366}
367
368static void pci_register_iommu_region(struct pci_pbm_info *pbm)
369{
370	const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
371					  NULL);
372
373	if (vdma) {
374		struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);
375
376		if (!rp) {
377			pr_info("%s: Cannot allocate IOMMU resource.\n",
378				pbm->name);
379			return;
380		}
381		rp->name = "IOMMU";
382		rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
383		rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
384		rp->flags = IORESOURCE_BUSY;
385		if (request_resource(&pbm->mem_space, rp)) {
386			pr_info("%s: Unable to request IOMMU resource.\n",
387				pbm->name);
388			kfree(rp);
389		}
390	}
391}
392
393void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
394{
395	const struct linux_prom_pci_ranges *pbm_ranges;
396	int i, saw_mem, saw_io;
397	int num_pbm_ranges;
398
399	saw_mem = saw_io = 0;
400	pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
401	if (!pbm_ranges) {
402		prom_printf("PCI: Fatal error, missing PBM ranges property "
403			    " for %s\n",
404			    pbm->name);
405		prom_halt();
406	}
407
408	num_pbm_ranges = i / sizeof(*pbm_ranges);
409	memset(&pbm->mem64_space, 0, sizeof(struct resource));
410
411	for (i = 0; i < num_pbm_ranges; i++) {
412		const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
413		unsigned long a, size;
414		u32 parent_phys_hi, parent_phys_lo;
415		u32 size_hi, size_lo;
416		int type;
417
418		parent_phys_hi = pr->parent_phys_hi;
419		parent_phys_lo = pr->parent_phys_lo;
420		if (tlb_type == hypervisor)
421			parent_phys_hi &= 0x0fffffff;
422
423		size_hi = pr->size_hi;
424		size_lo = pr->size_lo;
425
426		type = (pr->child_phys_hi >> 24) & 0x3;
427		a = (((unsigned long)parent_phys_hi << 32UL) |
428		     ((unsigned long)parent_phys_lo  <<  0UL));
429		size = (((unsigned long)size_hi << 32UL) |
430			((unsigned long)size_lo  <<  0UL));
431
432		switch (type) {
433		case 0:
434			/* PCI config space, 16MB */
435			pbm->config_space = a;
436			break;
437
438		case 1:
439			/* 16-bit IO space, 16MB */
440			pbm->io_space.start = a;
441			pbm->io_space.end = a + size - 1UL;
442			pbm->io_space.flags = IORESOURCE_IO;
443			saw_io = 1;
444			break;
445
446		case 2:
447			/* 32-bit MEM space, 2GB */
448			pbm->mem_space.start = a;
449			pbm->mem_space.end = a + size - 1UL;
450			pbm->mem_space.flags = IORESOURCE_MEM;
451			saw_mem = 1;
452			break;
453
454		case 3:
455			/* 64-bit MEM handling */
456			pbm->mem64_space.start = a;
457			pbm->mem64_space.end = a + size - 1UL;
458			pbm->mem64_space.flags = IORESOURCE_MEM;
459			saw_mem = 1;
460			break;
461
462		default:
463			break;
464		}
465	}
466
467	if (!saw_io || !saw_mem) {
468		prom_printf("%s: Fatal error, missing %s PBM range.\n",
469			    pbm->name,
470			    (!saw_io ? "IO" : "MEM"));
471		prom_halt();
472	}
473
474	printk("%s: PCI IO[%llx] MEM[%llx]",
475	       pbm->name,
476	       pbm->io_space.start,
477	       pbm->mem_space.start);
478	if (pbm->mem64_space.flags)
479		printk(" MEM64[%llx]",
480		       pbm->mem64_space.start);
481	printk("\n");
482
483	pbm->io_space.name = pbm->mem_space.name = pbm->name;
484	pbm->mem64_space.name = pbm->name;
485
486	request_resource(&ioport_resource, &pbm->io_space);
487	request_resource(&iomem_resource, &pbm->mem_space);
488	if (pbm->mem64_space.flags)
489		request_resource(&iomem_resource, &pbm->mem64_space);
490
491	pci_register_legacy_regions(&pbm->io_space,
492				    &pbm->mem_space);
493	pci_register_iommu_region(pbm);
494}
495
496/* Generic helper routines for PCI error reporting. */
497void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
498			       struct pci_bus *pbus)
499{
500	struct pci_dev *pdev;
501	struct pci_bus *bus;
502
503	list_for_each_entry(pdev, &pbus->devices, bus_list) {
504		u16 status, error_bits;
505
506		pci_read_config_word(pdev, PCI_STATUS, &status);
507		error_bits =
508			(status & (PCI_STATUS_SIG_TARGET_ABORT |
509				   PCI_STATUS_REC_TARGET_ABORT));
510		if (error_bits) {
511			pci_write_config_word(pdev, PCI_STATUS, error_bits);
512			printk("%s: Device %s saw Target Abort [%016x]\n",
513			       pbm->name, pci_name(pdev), status);
514		}
515	}
516
517	list_for_each_entry(bus, &pbus->children, node)
518		pci_scan_for_target_abort(pbm, bus);
519}
520
521void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
522			       struct pci_bus *pbus)
523{
524	struct pci_dev *pdev;
525	struct pci_bus *bus;
526
527	list_for_each_entry(pdev, &pbus->devices, bus_list) {
528		u16 status, error_bits;
529
530		pci_read_config_word(pdev, PCI_STATUS, &status);
531		error_bits =
532			(status & (PCI_STATUS_REC_MASTER_ABORT));
533		if (error_bits) {
534			pci_write_config_word(pdev, PCI_STATUS, error_bits);
535			printk("%s: Device %s received Master Abort [%016x]\n",
536			       pbm->name, pci_name(pdev), status);
537		}
538	}
539
540	list_for_each_entry(bus, &pbus->children, node)
541		pci_scan_for_master_abort(pbm, bus);
542}
543
544void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
545			       struct pci_bus *pbus)
546{
547	struct pci_dev *pdev;
548	struct pci_bus *bus;
549
550	list_for_each_entry(pdev, &pbus->devices, bus_list) {
551		u16 status, error_bits;
552
553		pci_read_config_word(pdev, PCI_STATUS, &status);
554		error_bits =
555			(status & (PCI_STATUS_PARITY |
556				   PCI_STATUS_DETECTED_PARITY));
557		if (error_bits) {
558			pci_write_config_word(pdev, PCI_STATUS, error_bits);
559			printk("%s: Device %s saw Parity Error [%016x]\n",
560			       pbm->name, pci_name(pdev), status);
561		}
562	}
563
564	list_for_each_entry(bus, &pbus->children, node)
565		pci_scan_for_parity_error(pbm, bus);
566}
567